Lecture 9: Interconnect

Size: px
Start display at page:

Download "Lecture 9: Interconnect"

Transcription

1 Digital Integrated Circuits (83-313) Lecture 9: Interconnect Semester B, Lecturer: Dr. Adam Teman TAs: Itamar Levi, Robert Giterman 23 May 2017 Disclaimer: This course was prepared, in its entirety, by Adam Teman. Many materials were copied from sources freely available on the internet. When possible, these sources have been cited; however, some references may have been cited incorrectly or overlooked. If you feel that a picture, graph, or code example has been copied from you and either needs to be cited or removed, please feel free to adam.teman@biu.ac.il and I will address this as soon as possible.

2 2 Lecture Content

3 3 A First Glance at Interconnect

4 The Wire Transmitters Receivers schematic view physical realization All-inclusive model Capacitance-only 4

5 Impact of Interconnect Parasitics Interconnect parasitics affect all the metrics we care about Reliability Performance Power Consumption Cost Classes of parasitics Capacitive Resistive Inductive 5

6 6 Modern Interconnect

7 7 Capacitance

8 Capacitance of Wire Interconnect V DD V DD V in C gd12 M2 C db2 V out C g4 M4 V out2 M1 C db1 C w Interconnect C g3 M3 Fanout Simplified Model V in V out C L 8

9 Capacitance: The Parallel Plate Model How can we reduce this capacitance? L Current flow Typical numbers: Wire cap ~0.2 ff/um Gate cap ~2 ff/um Diffusion cap ~2 ff/um W Electrical-field lines H t di Dielectric Substrate c pp t di di WL 9

10 10 Permittivity

11 Fringing Capacitance H H (a) (a) W - H/2 W - H/2 + + w W H /2 11 (b) (b) W H 2 di 2 di CF mm cpp c fringe t log t H di di

12 Fringing versus Parallel Plate C fringe edge 0.05 ff m C C fringe PP L W L (from [Bakoglu89]) 12

13 Top Plate A simple model for deriving wire cap Wiring capacitances in 0.25μm af/µm 2 Bottom Plate C C W L wire parallel _ plate 2C L fringe af/µm fringing parallel 13

14 Impact of Interwire Capacitance 14 Stanford: EE311

15 Coupling Capacitance and Delay C C1 C C2 C L 15 C tot C L

16 Coupling Capacitance and Delay 0 1 C C1 1 C C2 C L 0 16 C C C C tot L C1 C 2

17 Coupling Capacitance and Delay C C1 C C2 C L 17 C C 2 C C tot L C1 C 2

18 Example Coupling Cap A pair of wires, each with a capacitance to ground of 5pF, have a 1pF coupling capacitance between them. A square pulse of 1.8V (relative to ground) is connected to one of the wires. How high will the noise pulse be on the other wire? 18

19 Example Coupling Cap Draw an Equivalent Circuit: V C 2 Vin Ccoupled 1.81p C C 1p 5p coupled 2 0.3V 19

20 Coupling Waveforms Simulated coupling for C agg =C victim 1.8 Aggressor Victim (undriven): 50% Victim (half size driver): 16% Victim (equal size driver): 8% Victim (double size driver): 4% t (ps)

21 21 Shielding

22 22 Feedthrough Cap

23 23 Measuring Capacitance

24 24 Resistance

25 Wire Resistance H H W L L R = L H W R = L H W Sheet Resistance R o R 1 R 2 o Metal Sheet Resistance Bulk resistivity (W*cm) Silver (Ag) 1.6 R W L A L H W R sq R 1 R 2 L, W R sq H Copper (Cu) 1.7 Gold (Au) 2.2 Aluminum (Al) 2.8 Tungsten (W) 5.3 Molybdenum (Mo)

26 Sheet Resistance Typical sheet resistances for 180nm process Layer Sheet Resistance (W/) N-Well/P-Well Diffusion (silicided) 3-10 Diffusion (no silicide) Polysilicon (silicided) 3-10 Polysilicon (no silicide) Metal Metal Silicides: WSi 2, TiSi 2, PtSi 2 and TaSi Conductivity: 8-10 times better than Poly 26 Metal Metal Metal Metal R 100 m W square

27 Contact Resistance Contact/Vias add extra resistance Similar to changing between roads on the way to a destination Contact resistance is generally 2-20 Ω Make contacts bigger BUT current crowds around the perimeter of a contact. There are also problems in deposition Contacts/Vias have a maximum practical size. Use multiple contacts But does this add overlap capacitance? 27

28 Dealing with Resistance Selective Technology Scaling Don t scale the H Use Better Interconnect Materials reduce average wire-length e.g. copper, silicides More Interconnect Layers reduce average wire-length Minimize Contact Resistance Use single layer routing When changing layers, use lots of contacts. 90nm Process 28

29 29 Interconnect Modeling

30 The Ideal Model In schematics, a wire has no parasitics: The wire is a single equipotential region. No effect on circuit behavior. Effective in first stages of design and for very short wires. 30

31 The Lumped Model R wire =1Ω V out Driver c wire R on =1kΩ-10kΩ R driver V out V in C lumped 31

32 The Distributed RC-line But actually, our wire is a distributed entity. We can find its behavior by breaking it up into small RC segments. I C V V V V rdx rdx dv cdx dt i1 i i i1 i rc V t i 2 V x i 2 lim dx0 f x dx f x dx f ' x rc L 2 2 t 0.38 pd RC 32 Quadratic dependence on wire length The lumped model is pessimistic

33 Step-response of RC wire Step-response of RC wire as a function of time and space 33

34 Elmore Delay Approximation Solving the diffusion equation for a given network is complex. Elmore proposed a reasonably accurate method to achieve an approximation of the dominate pole. 34 elmore R C R R C R R R C

35 Elmore Delay Approximation For a complex network use the following method: Find all the resistors on the path from in to out. For every capacitor: Find all the resistors on the path from the input to the capacitor. Multiply the capacitance by the resistors that are also on the path to out. The dominant pole is approximately the sum of all these time constants. 35

36 Simple Elmore Delay Example RC R R C R C elmore

37 General Elmore Delay Example RC RC R R C R R C R R R C elmore i i 37

38 Generalized Ladder Chain Lets apply the Elmore approximation for our original distributed wire. Divide the wire into N equal segments of dx=l/n length with capacitance cdx and resistance rdx. N L L L L c r 2 r.. Nr N N N N 2 L rc 2 rc.. Nrc N lim N D N N 2 rcl 2 2 rcl RC 2 2 2N 1 38

39 RC-Models Pie Model T-Model Pie-2 Model Pie-3 Model T-2 Model T-3 Model 39

40 Wire Delay Example Inverter driving a wire and a load cap. C W C C R C W 2 2 R R driver d inv ext inv w 40

41 A different look Again we ll look at our driver with a distributed wire. For the driver resistance, we can lump the output load as a capacitor. For the wire resistance, we will use the distributed time constant. For the load capacitance, we can lump the wire and driver resistance. C w R ff 0.2 μm W R C C 0.38R C 0.69 R R C D inv d W W W inv w L 41

42 Dealing with long wires Repeater Insertion 42

43 Dealing with long wires Buffer Tree Insertion 43

44 44 Wire Scaling

45 Wire Scaling We could try to scale interconnect at the same rate (S) as device dimensions. This makes sense for local wires that connect smaller devices/gates. But global interconnections, such as clock signals, buses, etc., won t scale in length. Length of global interconnect is proportional to die size or system complexity. Die Size has increased by 6% per year years) Devices have scaled, but complexity has grown! 45

46 46 Nature of Interconnect

47 Local Wire Scaling Looking at local interconnect: W, H, t, L all scale at 1/S C=LW/t1/S R=L/WH S RC=1 Reminder Full Scaling of Transistors R on =V DD /I on α 1 t pd =R on C g α 1/S So the delay of local interconnect stays constant. But the delay of local interconnect increases relative to transistors! 47

48 Local Wire Scaling Full Scaling What about fringe cap? H H/S 48 t C WL pp Cfringe L t R L t R C WH wire p,wire wire wire t/s C S C S pp R S t 1 1 fringe wire p,wire const

49 Local Wire Scaling - Constant Thickness Wire thickness (height) wasn t scaled! 49 H t C WL pp Cfringe L t R L t R C WH wire p,wire wire wire C S C S pp H t/s wire 1 1 fringe R const t S p,wire 1

50 Local Wire Scaling Interwire Capacitance Without scaling height, coupling gets much worse. Aspect ratio is limited and we eventually have to scale the height. Therefore, different metal layers have different heights. 50 C pp, side LH C D pp, side const

51 Global Wire Scaling Looking at global interconnect: W, H, t scale at 1/S L doesn t scale! C=LW/t1 R=L/WH S 2 RC=S 2!!! Long wire delay increases quadratically!! And if chip size grows, L actually increases!! 51

52 Global Wire Scaling Constant Thickness Leave thickness constant for global wires But wire delay still gets quadratically worse than gate delay H H t t/s 52 C WL pp Cfringe L t R L t R C WH wire p,wire wire wire C pp wire const C p,wire fringe R S t S const

53 Wire Scaling So whereas device speed increases with scaling: Local interconnect speed stays constant. Global interconnect delays increase quadratically. Therefore: Interconnect delay is often the limiting factor for speed. What can we do? Keep the wire thickness (H) fixed. This would provide 1/S for local wire delays and S for constant length global wires. But fringing capacitance increases, so this is optimistic. 53

54 Wire Scaling What is done today? Low resistance metals. Low-K insulation. Low metals (M1, M2) are used for local interconnect, so they are thin and dense. Higher metals are used for global routing, so they are thicker, wider and spaced farther apart. 54

55 Modern Interconnect Intel 45 nm Stack [Moon08] 55

56 Further Reading J. Rabaey, Digital Integrated Circuits 2003, Chapter 4 E. Alon, Berkeley EE-141, Lectures 15,16 (Fall 2009) B. Nicolic, Berkeley EE-241, Lecture 3 (Spring 2011) Stanford EE311 56

Digital Integrated Circuits (83-313) Lecture 5: Interconnect. Semester B, Lecturer: Adam Teman TAs: Itamar Levi, Robert Giterman 1

Digital Integrated Circuits (83-313) Lecture 5: Interconnect. Semester B, Lecturer: Adam Teman TAs: Itamar Levi, Robert Giterman 1 Digital Integrated Circuits (83-313) Lecture 5: Interconnect Semester B, 2015-16 Lecturer: Adam Teman TAs: Itamar Levi, Robert Giterman 1 What will we learn today? 1 A First Glance at Interconnect 2 3

More information

Digital Integrated Circuits. The Wire * Fuyuzhuo. *Thanks for Dr.Guoyong.SHI for his slides contributed for the talk. Digital IC.

Digital Integrated Circuits. The Wire * Fuyuzhuo. *Thanks for Dr.Guoyong.SHI for his slides contributed for the talk. Digital IC. Digital Integrated Circuits The Wire * Fuyuzhuo *Thanks for Dr.Guoyong.SHI for his slides contributed for the talk Introduction The Wire transmitters receivers schematics physical 2 Interconnect Impact

More information

The Wire. Digital Integrated Circuits A Design Perspective. Jan M. Rabaey Anantha Chandrakasan Borivoje Nikolic. July 30, 2002

The Wire. Digital Integrated Circuits A Design Perspective. Jan M. Rabaey Anantha Chandrakasan Borivoje Nikolic. July 30, 2002 Digital Integrated Circuits A Design Perspective Jan M. Rabaey Anantha Chandrakasan Borivoje Nikolic The Wire July 30, 2002 1 The Wire transmitters receivers schematics physical 2 Interconnect Impact on

More information

CMPEN 411 VLSI Digital Circuits Spring 2012

CMPEN 411 VLSI Digital Circuits Spring 2012 CMPEN 411 VLSI Digital Circuits Spring 2012 Lecture 09: Resistance & Inverter Dynamic View [Adapted from Rabaey s Digital Integrated Circuits, Second Edition, 2003 J. Rabaey, A. Chandrakasan, B. Nikolic]

More information

The Wire EE141. Microelettronica

The Wire EE141. Microelettronica The Wire 1 Interconnect Impact on Chip 2 Example: a Bus Network transmitters receivers schematics physical 3 Wire Models All-inclusive model Capacitance-only 4 Impact of Interconnect Parasitics Interconnect

More information

Interconnects. Wire Resistance Wire Capacitance Wire RC Delay Crosstalk Wire Engineering Repeaters. ECE 261 James Morizio 1

Interconnects. Wire Resistance Wire Capacitance Wire RC Delay Crosstalk Wire Engineering Repeaters. ECE 261 James Morizio 1 Interconnects Wire Resistance Wire Capacitance Wire RC Delay Crosstalk Wire Engineering Repeaters ECE 261 James Morizio 1 Introduction Chips are mostly made of wires called interconnect In stick diagram,

More information

Interconnects. Introduction

Interconnects. Introduction Interconnects Wire Resistance Wire Capacitance Wire RC Delay Crosstalk Wire Engineering Repeaters ECE 261 Krish Chakrabarty 1 Introduction Chips are mostly made of ires called interconnect In stick diagram,

More information

Integrated Circuits & Systems

Integrated Circuits & Systems Federal University of Santa Catarina Center for Technology Computer Science & Electronics Engineering Integrated Circuits & Systems INE 5442 Lecture 7 Interconnections 1: wire resistance, capacitance,

More information

EE141-Spring 2007 Digital Integrated Circuits. Administrative Stuff. Last Lecture. Wires. Interconnect Impact on Chip. The Wire

EE141-Spring 2007 Digital Integrated Circuits. Administrative Stuff. Last Lecture. Wires. Interconnect Impact on Chip. The Wire EE141-Spring 2007 Digital Integrated Circuits ecture 10 Administrative Stuff No ab this week Midterm 1 on Tu! HW5 to be posted by next Friday Due Fr. March 2 5pm Introduction to wires 1 2 ast ecture ast

More information

EE141-Spring 2008 Digital Integrated Circuits EE141. Announcements EECS141 EE141. Lecture 24: Wires

EE141-Spring 2008 Digital Integrated Circuits EE141. Announcements EECS141 EE141. Lecture 24: Wires EE141-Spring 2008 Digital Integrated Circuits Lecture 24: Wires 1 Announcements Hw 8 posted last graded homework Project phase II feedback to be expected anytime 2 Material Last Lecture: Wire capacitance

More information

Capacitance - 1. The parallel plate capacitor. Capacitance: is a measure of the charge stored on each plate for a given voltage such that Q=CV

Capacitance - 1. The parallel plate capacitor. Capacitance: is a measure of the charge stored on each plate for a given voltage such that Q=CV Capacitance - 1 The parallel plate capacitor Capacitance: is a measure of the charge stored on each plate for a given voltage such that Q=CV Charge separation in a parallel-plate capacitor causes an internal

More information

EE115C Digital Electronic Circuits Homework #5

EE115C Digital Electronic Circuits Homework #5 EE115C Digital Electronic Circuits Homework #5 Due Thursday, May 13, 6pm @ 56-147E EIV Problem 1 Elmore Delay Analysis Calculate the Elmore delay from node A to node B using the values for the resistors

More information

EECS 151/251A Spring 2018 Digital Design and Integrated Circuits. Instructors: Nick Weaver & John Wawrzynek. Lecture 12 EE141

EECS 151/251A Spring 2018 Digital Design and Integrated Circuits. Instructors: Nick Weaver & John Wawrzynek. Lecture 12 EE141 EECS 151/251A Spring 2018 Digital Design and Integrated Circuits Instructors: Nick Weaver & John Wawrzynek Lecture 12 1 Wire Models All-inclusive model Capacitance-only 2 Capacitance Capacitance: The Parallel

More information

ENEE 359a Digital VLSI Design

ENEE 359a Digital VLSI Design SLIDE 1 ENEE 359a Digital VLSI Design & Logical Effort Prof. blj@ece.umd.edu Credit where credit is due: Slides contain original artwork ( Jacob 2004) as well as material taken liberally from Irwin & Vijay

More information

VLSI GATE LEVEL DESIGN UNIT - III P.VIDYA SAGAR ( ASSOCIATE PROFESSOR) Department of Electronics and Communication Engineering, VBIT

VLSI GATE LEVEL DESIGN UNIT - III P.VIDYA SAGAR ( ASSOCIATE PROFESSOR) Department of Electronics and Communication Engineering, VBIT VLSI UNIT - III GATE LEVEL DESIGN P.VIDYA SAGAR ( ASSOCIATE PROFESSOR) contents GATE LEVEL DESIGN : Logic Gates and Other complex gates, Switch logic, Alternate gate circuits, Time Delays, Driving large

More information

Lecture 4: Technology Scaling

Lecture 4: Technology Scaling Digital Integrated Circuits (83-313) Lecture 4: Technology Scaling Semester B, 2016-17 Lecturer: Dr. Adam Teman TAs: Itamar Levi, Robert Giterman 2 April 2017 Disclaimer: This course was prepared, in its

More information

CARNEGIE MELLON UNIVERSITY DEPARTMENT OF ELECTRICAL AND COMPUTER ENGINEERING DIGITAL INTEGRATED CIRCUITS FALL 2002

CARNEGIE MELLON UNIVERSITY DEPARTMENT OF ELECTRICAL AND COMPUTER ENGINEERING DIGITAL INTEGRATED CIRCUITS FALL 2002 CARNEGIE MELLON UNIVERSITY DEPARTMENT OF ELECTRICAL AND COMPUTER ENGINEERING 18-322 DIGITAL INTEGRATED CIRCUITS FALL 2002 Final Examination, Monday Dec. 16, 2002 NAME: SECTION: Time: 180 minutes Closed

More information

Very Large Scale Integration (VLSI)

Very Large Scale Integration (VLSI) Very Large Scale Integration (VLSI) Lecture 4 Dr. Ahmed H. Madian Ah_madian@hotmail.com Dr. Ahmed H. Madian-VLSI Contents Delay estimation Simple RC model Penfield-Rubenstein Model Logical effort Delay

More information

VLSI Design and Simulation

VLSI Design and Simulation VLSI Design and Simulation Performance Characterization Topics Performance Characterization Resistance Estimation Capacitance Estimation Inductance Estimation Performance Characterization Inverter Voltage

More information

Lecture 11: MOSFET Modeling

Lecture 11: MOSFET Modeling Digital Integrated Circuits (83-313) Lecture 11: MOSFET ing Semester B, 2016-17 Lecturer: Dr. Adam Teman TAs: Itamar Levi, Robert Giterman 18 June 2017 Disclaimer: This course was prepared, in its entirety,

More information

ECE520 VLSI Design. Lecture 8: Interconnect Manufacturing and Modeling. Payman Zarkesh-Ha

ECE520 VLSI Design. Lecture 8: Interconnect Manufacturing and Modeling. Payman Zarkesh-Ha ECE520 VLSI Design Lecture 8: Interconnect Manufacturing and Modeling Payman Zarkesh-Ha Office: ECE Bldg. 230B Office hours: Wednesday 2:00-3:00PM or by appointment E-mail: pzarkesh@unm.edu Slide: 1 Review

More information

Lecture 12 CMOS Delay & Transient Response

Lecture 12 CMOS Delay & Transient Response EE 471: Transport Phenomena in Solid State Devices Spring 2018 Lecture 12 CMOS Delay & Transient Response Bryan Ackland Department of Electrical and Computer Engineering Stevens Institute of Technology

More information

CPE/EE 427, CPE 527 VLSI Design I L13: Wires, Design for Speed. Course Administration

CPE/EE 427, CPE 527 VLSI Design I L13: Wires, Design for Speed. Course Administration CPE/EE 427, CPE 527 VLSI Design I L3: Wires, Design for Speed Department of Electrical and Computer Engineering University of labama in Huntsville leksandar Milenkovic ( www.ece.uah.edu/~milenka ) www.ece.uah.edu/~milenka/cpe527-05f

More information

10. Performance. Summary

10. Performance. Summary 10. Performance Summary Interconnect Parameters: Capacitance, Resistance, Inductance Electrical Wire Models Lumped C model Lumped RC model RC chain model Distributed RC line model Transmission line model

More information

ECE260B CSE241A Winter Interconnects. Website:

ECE260B CSE241A Winter Interconnects. Website: ECE260B CSE241A Winter 2004 Interconnects Website: http://vlsicad.ucsd.edu/courses/ece260b-w04 ECE 260B CSE 241A Interconnects 1 Outline Interconnects Resistance Capacitance and Inductance Delay ECE 260B

More information

CMOS Transistors, Gates, and Wires

CMOS Transistors, Gates, and Wires CMOS Transistors, Gates, and Wires Should the hardware abstraction layers make today s lecture irrelevant? pplication R P C W / R W C W / 6.375 Complex Digital Systems Christopher atten February 5, 006

More information

Spiral 2 7. Capacitance, Delay and Sizing. Mark Redekopp

Spiral 2 7. Capacitance, Delay and Sizing. Mark Redekopp 2-7.1 Spiral 2 7 Capacitance, Delay and Sizing Mark Redekopp 2-7.2 Learning Outcomes I understand the sources of capacitance in CMOS circuits I understand how delay scales with resistance, capacitance

More information

Homework #2 10/6/2016. C int = C g, where 1 t p = t p0 (1 + C ext / C g ) = t p0 (1 + f/ ) f = C ext /C g is the effective fanout

Homework #2 10/6/2016. C int = C g, where 1 t p = t p0 (1 + C ext / C g ) = t p0 (1 + f/ ) f = C ext /C g is the effective fanout 0/6/06 Homework # Lecture 8, 9: Sizing and Layout of omplex MOS Gates Reading: hapter 4, sections 4.3-4.5 October 3 & 5, 06 hapter, section.5.5 Prof. R. Iris ahar Weste & Harris vailable on course webpage

More information

! Dynamic Characteristics. " Delay

! Dynamic Characteristics.  Delay EE 57: Digital Integrated ircuits and LI Fundamentals Lecture Outline! Dynamic haracteristics " Delay Lec : February, 8 MO Inverter and Interconnect Delay 3 Review: Propogation Delay Definitions Dynamic

More information

Digital Microelectronic Circuits ( )

Digital Microelectronic Circuits ( ) Digital Microelectronic ircuits (361-1-3021 ) Presented by: Dr. Alex Fish Lecture 5: Parasitic apacitance and Driving a Load 1 Motivation Thus far, we have learned how to model our essential building block,

More information

UNIVERSITY OF CALIFORNIA College of Engineering Department of Electrical Engineering and Computer Sciences. Professor Oldham Fall 1999

UNIVERSITY OF CALIFORNIA College of Engineering Department of Electrical Engineering and Computer Sciences. Professor Oldham Fall 1999 UNIVERSITY OF CLIFORNI College of Engineering Department of Electrical Engineering and Computer Sciences Professor Oldham Fall 1999 EECS 40 FINL EXM 13 December 1999 Name: Last, First Student ID: T: Kusuma

More information

CMOS Cross Section. EECS240 Spring Dimensions. Today s Lecture. Why Talk About Passives? EE240 Process

CMOS Cross Section. EECS240 Spring Dimensions. Today s Lecture. Why Talk About Passives? EE240 Process EECS240 Spring 202 CMOS Cross Section Metal p - substrate p + diffusion Lecture 2: CMOS Technology and Passive Devices Poly n - well n + diffusion Elad Alon Dept. of EECS EECS240 Lecture 2 4 Today s Lecture

More information

and V DS V GS V T (the saturation region) I DS = k 2 (V GS V T )2 (1+ V DS )

and V DS V GS V T (the saturation region) I DS = k 2 (V GS V T )2 (1+ V DS ) ECE 4420 Spring 2005 Page 1 FINAL EXAMINATION NAME SCORE /100 Problem 1O 2 3 4 5 6 7 Sum Points INSTRUCTIONS: This exam is closed book. You are permitted four sheets of notes (three of which are your sheets

More information

ESE 570: Digital Integrated Circuits and VLSI Fundamentals

ESE 570: Digital Integrated Circuits and VLSI Fundamentals ESE 570: Digital Integrated Circuits and VLSI Fundamentals Lec 24: April 19, 2018 Crosstalk and Wiring, Transmission Lines Lecture Outline! Crosstalk! Repeaters in Wiring! Transmission Lines " Where transmission

More information

! Crosstalk. ! Repeaters in Wiring. ! Transmission Lines. " Where transmission lines arise? " Lossless Transmission Line.

! Crosstalk. ! Repeaters in Wiring. ! Transmission Lines.  Where transmission lines arise?  Lossless Transmission Line. ESE 570: Digital Integrated Circuits and VLSI Fundamentals Lec 24: April 19, 2018 Crosstalk and Wiring, Transmission Lines Lecture Outline! Crosstalk! Repeaters in Wiring! Transmission Lines " Where transmission

More information

Interconnect (2) Buffering Techniques. Logical Effort

Interconnect (2) Buffering Techniques. Logical Effort Interconnect (2) Buffering Techniques. Logical Effort Lecture 14 18-322 Fall 2002 Textbook: [Sections 4.2.1, 8.2.3] A few announcements! M1 is almost over: The check-off is due today (by 9:30PM) Students

More information

Interconnect (2) Buffering Techniques.Transmission Lines. Lecture Fall 2003

Interconnect (2) Buffering Techniques.Transmission Lines. Lecture Fall 2003 Interconnect (2) Buffering Techniques.Transmission Lines Lecture 12 18-322 Fall 2003 A few announcements Partners Lab Due Times Midterm 1 is nearly here Date: 10/14/02, time: 3:00-4:20PM, place: in class

More information

EE115C Digital Electronic Circuits Homework #6

EE115C Digital Electronic Circuits Homework #6 Problem 1 Sizing of adder blocks Electrical Engineering Department Spring 2010 EE115C Digital Electronic Circuits Homework #6 Solution Figure 1: Mirror adder. Study the mirror adder cell (textbook, pages

More information

Topics to be Covered. capacitance inductance transmission lines

Topics to be Covered. capacitance inductance transmission lines Topics to be Covered Circuit Elements Switching Characteristics Power Dissipation Conductor Sizes Charge Sharing Design Margins Yield resistance capacitance inductance transmission lines Resistance of

More information

Designing Sequential Logic Circuits

Designing Sequential Logic Circuits igital Integrated Circuits (83-313) Lecture 5: esigning Sequential Logic Circuits Semester B, 2016-17 Lecturer: r. Adam Teman TAs: Itamar Levi, Robert Giterman 26 April 2017 isclaimer: This course was

More information

Interconnect s Role in Deep Submicron. Second class to first class

Interconnect s Role in Deep Submicron. Second class to first class Interconnect s Role in Deep Submicron Dennis Sylvester EE 219 November 3, 1998 Second class to first class Interconnect effects are no longer secondary # of wires # of devices More metal levels RC delay

More information

Lecture 23. Dealing with Interconnect. Impact of Interconnect Parasitics

Lecture 23. Dealing with Interconnect. Impact of Interconnect Parasitics Lecture 23 Dealing with Interconnect Impact of Interconnect Parasitics Reduce Reliability Affect Performance Classes of Parasitics Capacitive Resistive Inductive 1 INTERCONNECT Dealing with Capacitance

More information

EECS240 Spring Today s Lecture. Lecture 2: CMOS Technology and Passive Devices. Lingkai Kong EECS. EE240 CMOS Technology

EECS240 Spring Today s Lecture. Lecture 2: CMOS Technology and Passive Devices. Lingkai Kong EECS. EE240 CMOS Technology EECS240 Spring 2013 Lecture 2: CMOS Technology and Passive Devices Lingkai Kong EECS Today s Lecture EE240 CMOS Technology Passive devices Motivation Resistors Capacitors (Inductors) Next time: MOS transistor

More information

EECS 151/251A Homework 5

EECS 151/251A Homework 5 EECS 151/251A Homework 5 Due Monday, March 5 th, 2018 Problem 1: Timing The data-path shown below is used in a simple processor. clk rd1 rd2 0 wr regfile 1 0 ALU REG 1 The elements used in the design have

More information

Lecture 5: DC & Transient Response

Lecture 5: DC & Transient Response Lecture 5: DC & Transient Response Outline q Pass Transistors q DC Response q Logic Levels and Noise Margins q Transient Response q RC Delay Models q Delay Estimation 2 Activity 1) If the width of a transistor

More information

Lecture 7 Circuit Delay, Area and Power

Lecture 7 Circuit Delay, Area and Power Lecture 7 Circuit Delay, Area and Power lecture notes from S. Mitra Intro VLSI System course (EE271) Introduction to VLSI Systems 1 Circuits and Delay Introduction to VLSI Systems 2 Power, Delay and Area:

More information

Integrated Circuits & Systems

Integrated Circuits & Systems Federal University of Santa Catarina Center for Technology Computer Science & Electronics Engineering Integrated Circuits & Systems INE 5442 Lecture 14 The CMOS Inverter: dynamic behavior (sizing, inverter

More information

Lecture 4: CMOS Transistor Theory

Lecture 4: CMOS Transistor Theory Introduction to CMOS VLSI Design Lecture 4: CMOS Transistor Theory David Harris, Harvey Mudd College Kartik Mohanram and Steven Levitan University of Pittsburgh Outline q Introduction q MOS Capacitor q

More information

CMOS Cross Section. EECS240 Spring Today s Lecture. Dimensions. CMOS Process. Devices. Lecture 2: CMOS Technology and Passive Devices

CMOS Cross Section. EECS240 Spring Today s Lecture. Dimensions. CMOS Process. Devices. Lecture 2: CMOS Technology and Passive Devices EECS240 Spring 2008 CMOS Cross Section Metal p - substrate p + diffusion Lecture 2: CMOS echnology and Passive Devices Poly n - well n + diffusion Elad Alon Dept. of EECS EECS240 Lecture 2 4 oday s Lecture

More information

CMPEN 411 VLSI Digital Circuits Spring 2012 Lecture 17: Dynamic Sequential Circuits And Timing Issues

CMPEN 411 VLSI Digital Circuits Spring 2012 Lecture 17: Dynamic Sequential Circuits And Timing Issues CMPEN 411 VLSI Digital Circuits Spring 2012 Lecture 17: Dynamic Sequential Circuits And Timing Issues [Adapted from Rabaey s Digital Integrated Circuits, Second Edition, 2003 J. Rabaey, A. Chandrakasan,

More information

Practice 7: CMOS Capacitance

Practice 7: CMOS Capacitance Practice 7: CMOS Capacitance Digital Electronic Circuits Semester A 2012 MOSFET Capacitances MOSFET Capacitance Components 3 Gate to Channel Capacitance In general, the gate capacitance is similar to a

More information

ECE 497 JS Lecture - 18 Impact of Scaling

ECE 497 JS Lecture - 18 Impact of Scaling ECE 497 JS Lecture - 18 Impact of Scaling Spring 2004 Jose E. Schutt-Aine Electrical & Computer Engineering University of Illinois jose@emlab.uiuc.edu 1 Announcements Thursday April 8 th Speaker: Prof.

More information

DC and Transient. Courtesy of Dr. Daehyun Dr. Dr. Shmuel and Dr.

DC and Transient. Courtesy of Dr. Daehyun Dr. Dr. Shmuel and Dr. DC and Transient Courtesy of Dr. Daehyun Lim@WSU, Dr. Harris@HMC, Dr. Shmuel Wimer@BIU and Dr. Choi@PSU http://csce.uark.edu +1 (479) 575-604 yrpeng@uark.edu Pass Transistors We have assumed source is

More information

Lecture 25. Dealing with Interconnect and Timing. Digital Integrated Circuits Interconnect

Lecture 25. Dealing with Interconnect and Timing. Digital Integrated Circuits Interconnect Lecture 25 Dealing with Interconnect and Timing Administrivia Projects will be graded by next week Project phase 3 will be announced next Tu.» Will be homework-like» Report will be combined poster Today

More information

EE5780 Advanced VLSI CAD

EE5780 Advanced VLSI CAD EE5780 Advanced VLSI CAD Lecture 4 DC and Transient Responses, Circuit Delays Zhuo Feng 4.1 Outline Pass Transistors DC Response Logic Levels and Noise Margins Transient Response RC Delay Models Delay

More information

Circuits. L5: Fabrication and Layout -2 ( ) B. Mazhari Dept. of EE, IIT Kanpur. B. Mazhari, IITK. G-Number

Circuits. L5: Fabrication and Layout -2 ( ) B. Mazhari Dept. of EE, IIT Kanpur. B. Mazhari, IITK. G-Number EE610: CMOS Analog Circuits L5: Fabrication and Layout -2 (12.8.2013) B. Mazhari Dept. of EE, IIT Kanpur 44 Passive Components: Resistor Besides MOS transistors, sometimes one requires to implement passive

More information

Digital Integrated Circuits A Design Perspective

Digital Integrated Circuits A Design Perspective Semiconductor Memories Adapted from Chapter 12 of Digital Integrated Circuits A Design Perspective Jan M. Rabaey et al. Copyright 2003 Prentice Hall/Pearson Outline Memory Classification Memory Architectures

More information

EE 466/586 VLSI Design. Partha Pande School of EECS Washington State University

EE 466/586 VLSI Design. Partha Pande School of EECS Washington State University EE 466/586 VLSI Design Partha Pande School of EECS Washington State University pande@eecs.wsu.edu Lecture 9 Propagation delay Power and delay Tradeoffs Follow board notes Propagation Delay Switching Time

More information

5.0 CMOS Inverter. W.Kucewicz VLSICirciuit Design 1

5.0 CMOS Inverter. W.Kucewicz VLSICirciuit Design 1 5.0 CMOS Inverter W.Kucewicz VLSICirciuit Design 1 Properties Switching Threshold Dynamic Behaviour Capacitance Propagation Delay nmos/pmos Ratio Power Consumption Contents W.Kucewicz VLSICirciuit Design

More information

EE115C Digital Electronic Circuits Homework #4

EE115C Digital Electronic Circuits Homework #4 EE115 Digital Electronic ircuits Homework #4 Problem 1 Power Dissipation Solution Vdd =1.0V onsider the source follower circuit used to drive a load L =20fF shown above. M1 and M2 are both NMOS transistors

More information

2. (2pts) What is the major difference between an epitaxial layer and a polysilicon layer?

2. (2pts) What is the major difference between an epitaxial layer and a polysilicon layer? EE 330 Exam 1 Spring 2017 Name Instructions: Students may bring 1 page of notes (front and back) to this exam and a calculator but the use of any device that has wireless communication capability is prohibited.

More information

THE INVERTER. Inverter

THE INVERTER. Inverter THE INVERTER DIGITAL GATES Fundamental Parameters Functionality Reliability, Robustness Area Performance» Speed (delay)» Power Consumption» Energy Noise in Digital Integrated Circuits v(t) V DD i(t) (a)

More information

VLSI Design I; A. Milenkovic 1

VLSI Design I; A. Milenkovic 1 ourse dministration PE/EE 47, PE 57 VLSI Design I L3: Wires, Design for Speed Department of Electrical and omputer Engineering University of labama in Huntsville leksandar Milenkovic (.ece.uah.edu/~milenka

More information

Dynamic Repeater with Booster Enhancement for Fast Switching Speed and Propagation in Long Interconnect

Dynamic Repeater with Booster Enhancement for Fast Switching Speed and Propagation in Long Interconnect Wright State University CORE Scholar Browse all Theses and Dissertations Theses and Dissertations 2014 Dynamic Repeater with Booster Enhancement for Fast Switching Speed and Propagation in Long Interconnect

More information

Integrated Circuits & Systems

Integrated Circuits & Systems Federal University of Santa Catarina Center for Technology Computer Science & Electronics Engineering Integrated Circuits & Systems INE 5442 Lecture 13 The CMOS Inverter: dynamic behavior (delay) guntzel@inf.ufsc.br

More information

UNIVERSITY OF CALIFORNIA, BERKELEY College of Engineering Department of Electrical Engineering and Computer Sciences

UNIVERSITY OF CALIFORNIA, BERKELEY College of Engineering Department of Electrical Engineering and Computer Sciences UNIVERSITY OF CAIFORNIA, BERKEEY College of Engineering Department of Electrical Engineering and Computer Sciences Elad Alon Homework #7 - Solutions EECS141 Due Thursday, October 22, 5pm, box in 240 Cory

More information

VLSI Design I; A. Milenkovic 1

VLSI Design I; A. Milenkovic 1 Review Voltage wing of PT Driving an Inverter PE/EE 47, PE 57 VLI Design I L9: MO & Wire apacitances Department of Electrical and omputer Engineering University of labama in Huntsville leksandar Milenkovic

More information

Lecture 6: DC & Transient Response

Lecture 6: DC & Transient Response Lecture 6: DC & Transient Response Slides courtesy of Deming Chen Slides based on the initial set from David Harris CMOS VLSI Design Outline Pass Transistors DC Response Logic Levels and Noise Margins

More information

MOS Transistor Theory

MOS Transistor Theory MOS Transistor Theory So far, we have viewed a MOS transistor as an ideal switch (digital operation) Reality: less than ideal EE 261 Krish Chakrabarty 1 Introduction So far, we have treated transistors

More information

MOSFET: Introduction

MOSFET: Introduction E&CE 437 Integrated VLSI Systems MOS Transistor 1 of 30 MOSFET: Introduction Metal oxide semiconductor field effect transistor (MOSFET) or MOS is widely used for implementing digital designs Its major

More information

The CMOS Inverter: A First Glance

The CMOS Inverter: A First Glance The CMOS Inverter: A First Glance V DD S D V in V out C L D S CMOS Inverter N Well V DD V DD PMOS 2λ PMOS Contacts In Out In Out Metal 1 NMOS Polysilicon NMOS GND CMOS Inverter: Steady State Response V

More information

Lecture 5: DC & Transient Response

Lecture 5: DC & Transient Response Lecture 5: DC & Transient Response Outline Pass Transistors DC Response Logic Levels and Noise Margins Transient Response RC Delay Models Delay Estimation 2 Pass Transistors We have assumed source is grounded

More information

ESE 570: Digital Integrated Circuits and VLSI Fundamentals

ESE 570: Digital Integrated Circuits and VLSI Fundamentals ESE 570: Digital Integrated Circuits and VLSI Fundamentals Lec 15: March 3, 2016 Combination Logic: Ratioed & Pass Logic, and Performance Lecture Outline! CMOS NOR2 Worst Case Analysis! Pass Transistor

More information

Lecture 4: DC & Transient Response

Lecture 4: DC & Transient Response Introduction to CMOS VLSI Design Lecture 4: DC & Transient Response David Harris Harvey Mudd College Spring 004 Outline DC Response Logic Levels and Noise Margins Transient Response Delay Estimation Slide

More information

ECEN 474/704 Lab 2: Layout Design

ECEN 474/704 Lab 2: Layout Design ECEN 474/704 Lab 2: Layout esign Objectives Learn Techniques for successful integrated circuit layout design. Introduction In this lab you will learn in detail how to generate a simple transistor layout.

More information

Digital Integrated Circuits EECS 312. Review. Fringe vs. parallel plate capacitance. Rent s rule. Impact of inter-wire capacitance

Digital Integrated Circuits EECS 312. Review. Fringe vs. parallel plate capacitance. Rent s rule. Impact of inter-wire capacitance 4 8 6 IM ES9 ipolar Fujitsu VP IM 9S Pulsar 4 IM 9 IM RY6 D yber 5 IM 48 IM RY4 IM 8 pache Fujitsu M8 IM 7 Merced IM 6 IM Vacuum Pentium II(DSIP) 95 96 97 98 99 NTT Fujitsu M-78 Year of announcement IM

More information

EE 330 Lecture 6. Improved Switch-Level Model Propagation Delay Stick Diagrams Technology Files - Design Rules

EE 330 Lecture 6. Improved Switch-Level Model Propagation Delay Stick Diagrams Technology Files - Design Rules EE 330 Lecture 6 Improved witch-level Model Propagation elay tick iagrams Technology Files - esign Rules Review from Last Time MO Transistor Qualitative iscussion of n-channel Operation Bulk ource Gate

More information

Homework Assignment #5 EE 477 Spring 2017 Professor Parker

Homework Assignment #5 EE 477 Spring 2017 Professor Parker Homework Assignment #5 EE 477 Spring 2017 Professor Parker Question 1: (15%) Compute the worst-case rising and falling RC time constants at point B of the circuit below using the Elmore delay method. Assume

More information

Switched-Capacitor Circuits David Johns and Ken Martin University of Toronto

Switched-Capacitor Circuits David Johns and Ken Martin University of Toronto Switched-Capacitor Circuits David Johns and Ken Martin University of Toronto (johns@eecg.toronto.edu) (martin@eecg.toronto.edu) University of Toronto 1 of 60 Basic Building Blocks Opamps Ideal opamps usually

More information

EECS 141: SPRING 09 MIDTERM 2

EECS 141: SPRING 09 MIDTERM 2 University of California College of Engineering Department of Electrical Engineering and Computer Sciences J. Rabaey WeFr 2-3:30pm We, April 22, 2:00-3:30pm EECS 141: SPRING 09 MIDTERM 2 NAME Last First

More information

E40M Capacitors. M. Horowitz, J. Plummer, R. Howe

E40M Capacitors. M. Horowitz, J. Plummer, R. Howe E40M Capacitors 1 Reading Reader: Chapter 6 Capacitance A & L: 9.1.1, 9.2.1 2 Why Are Capacitors Useful/Important? How do we design circuits that respond to certain frequencies? What determines how fast

More information

C.K. Ken Yang UCLA Courtesy of MAH EE 215B

C.K. Ken Yang UCLA Courtesy of MAH EE 215B Decoders: Logical Effort Applied C.K. Ken Yang UCLA yang@ee.ucla.edu Courtesy of MAH 1 Overview Reading Rabaey 6.2.2 (Ratio-ed logic) W&H 6.2.2 Overview We have now gone through the basics of decoders,

More information

Lecture 210 Physical Aspects of ICs (12/15/01) Page 210-1

Lecture 210 Physical Aspects of ICs (12/15/01) Page 210-1 Lecture 210 Physical Aspects of ICs (12/15/01) Page 210-1 LECTURE 210 PHYSICAL ASPECTS OF ICs (READING: Text-Sec. 2.5, 2.6, 2.8) INTRODUCTION Objective Illustrate the physical aspects of integrated circuits

More information

Chapter 9. Estimating circuit speed. 9.1 Counting gate delays

Chapter 9. Estimating circuit speed. 9.1 Counting gate delays Chapter 9 Estimating circuit speed 9.1 Counting gate delays The simplest method for estimating the speed of a VLSI circuit is to count the number of VLSI logic gates that the input signals must propagate

More information

EE241 - Spring 2000 Advanced Digital Integrated Circuits. Announcements

EE241 - Spring 2000 Advanced Digital Integrated Circuits. Announcements EE241 - Spring 2000 Advanced Digital Integrated Circuits Lecture 3 Circuit Optimization for Speed Announcements Tu 2/8/00 class will be pre-taped on Friday, 2/4, 4-5:30 203 McLaughlin Class notes are available

More information

Low Power VLSI Circuits and Systems Prof. Ajit Pal Department of Computer Science and Engineering Indian Institute of Technology, Kharagpur

Low Power VLSI Circuits and Systems Prof. Ajit Pal Department of Computer Science and Engineering Indian Institute of Technology, Kharagpur Low Power VLSI Circuits and Systems Prof. Ajit Pal Department of Computer Science and Engineering Indian Institute of Technology, Kharagpur Lecture No. # 08 MOS Inverters - III Hello, and welcome to today

More information

COMP 103. Lecture 10. Inverter Dynamics: The Quest for Performance. Section 5.4.2, What is this lecture+ about? PERFORMANCE

COMP 103. Lecture 10. Inverter Dynamics: The Quest for Performance. Section 5.4.2, What is this lecture+ about? PERFORMANCE COMP 103 Lecture 10 Inverter Dynamics: The Quest for Performance Section 5.4.2, 5.4.3 [All lecture notes are adapted from Mary Jane Irwin, Penn State, which were adapted from Rabaey s Digital Integrated

More information

CMOS logic gates. João Canas Ferreira. March University of Porto Faculty of Engineering

CMOS logic gates. João Canas Ferreira. March University of Porto Faculty of Engineering CMOS logic gates João Canas Ferreira University of Porto Faculty of Engineering March 2016 Topics 1 General structure 2 General properties 3 Cell layout João Canas Ferreira (FEUP) CMOS logic gates March

More information

Announcements. EE141- Fall 2002 Lecture 25. Interconnect Effects I/O, Power Distribution

Announcements. EE141- Fall 2002 Lecture 25. Interconnect Effects I/O, Power Distribution - Fall 2002 Lecture 25 Interconnect Effects I/O, Power Distribution Announcements Homework 9 due next Tuesday Hardware lab this week Project phase 2 due in two weeks 1 Today s Lecture Impact of interconnects»

More information

Digital Integrated Circuits EECS 312. Midterm exam 1 II. Homework 3 walkthrough. Review. Rent s rule. Inter-wire capacitance

Digital Integrated Circuits EECS 312. Midterm exam 1 II. Homework 3 walkthrough. Review. Rent s rule. Inter-wire capacitance 8 6 IM ES9 ipolar Fujitsu VP IM 9S NTT Fujitsu M-78 IM 9 D yber 5 Year of announcement IM RY5 IM RY7 Pulsar IM RY6 IM RY MOS Jayhawk(dual) T-Rex Mckinley IM GP Prescott Squadrons IM 9 Pentium IM 8 IM 8

More information

Lecture #39. Transistor Scaling

Lecture #39. Transistor Scaling Lecture #39 ANNOUNCEMENT Pick up graded HW assignments and exams (78 Cory) Lecture #40 will be the last formal lecture. Class on Friday will be dedicated to a course review (with sample problems). Discussion

More information

EE371 - Advanced VLSI Circuit Design

EE371 - Advanced VLSI Circuit Design EE371 - Advanced VLSI Circuit Design Midterm Examination May 1999 Name: No. Points Score 1. 20 2. 24 3. 26 4. 20 TOTAL / 90 In recognition of and in the spirit of the Stanford University Honor Code, I

More information

Analysis of TSV-to-TSV Coupling with High-Impedance Termination in 3D ICs

Analysis of TSV-to-TSV Coupling with High-Impedance Termination in 3D ICs Analysis of -to- Coupling with -Impedance Termination in 3D ICs Taigon Song, Chang Liu, Dae Hyun Kim, and Sung Kyu Lim School of Electrical and Computer Engineering, Georgia Institute of Technology, U.S.A.

More information

EE 435. Lecture 37. Parasitic Capacitances in MOS Devices. String DAC Parasitic Capacitances

EE 435. Lecture 37. Parasitic Capacitances in MOS Devices. String DAC Parasitic Capacitances EE 435 Lecture 37 Parasitic Capacitances in MOS Devices String DAC Parasitic Capacitances Parasitic Capacitors in MOSFET (will initially consider two) Parasitic Capacitors in MOSFET C GCH Parasitic Capacitors

More information

Semiconductor Memories

Semiconductor Memories Semiconductor References: Adapted from: Digital Integrated Circuits: A Design Perspective, J. Rabaey UCB Principles of CMOS VLSI Design: A Systems Perspective, 2nd Ed., N. H. E. Weste and K. Eshraghian

More information

GMU, ECE 680 Physical VLSI Design 1

GMU, ECE 680 Physical VLSI Design 1 ECE680: Physical VLSI Design Chapter VIII Semiconductor Memory (chapter 12 in textbook) 1 Chapter Overview Memory Classification Memory Architectures The Memory Core Periphery Reliability Case Studies

More information

ESE570 Spring University of Pennsylvania Department of Electrical and System Engineering Digital Integrated Cicruits AND VLSI Fundamentals

ESE570 Spring University of Pennsylvania Department of Electrical and System Engineering Digital Integrated Cicruits AND VLSI Fundamentals University of Pennsylvania Department of Electrical and System Engineering Digital Integrated Cicruits AND VLSI Fundamentals ESE570, Spring 2018 Final Monday, Apr 0 5 Problems with point weightings shown.

More information

ELEN0037 Microelectronic IC Design. Prof. Dr. Michael Kraft

ELEN0037 Microelectronic IC Design. Prof. Dr. Michael Kraft ELEN0037 Microelectronic IC Design Prof. Dr. Michael Kraft Lecture 2: Technological Aspects Technology Passive components Active components CMOS Process Basic Layout Scaling CMOS Technology Integrated

More information

EE 560 CHIP INPUT AND OUTPUT (I/0) CIRCUITS. Kenneth R. Laker, University of Pennsylvania

EE 560 CHIP INPUT AND OUTPUT (I/0) CIRCUITS. Kenneth R. Laker, University of Pennsylvania 1 EE 560 CHIP INPUT AND OUTPUT (I/0) CIRCUITS 2 -> ESD PROTECTION CIRCUITS (INPUT PADS) -> ON-CHIP CLOCK GENERATION & DISTRIBUTION -> OUTPUT PADS -> ON-CHIP NOISE DUE TO PARASITIC INDUCTANCE -> SUPER BUFFER

More information

UNIVERSITY OF CALIFORNIA, BERKELEY College of Engineering Department of Electrical Engineering and Computer Sciences

UNIVERSITY OF CALIFORNIA, BERKELEY College of Engineering Department of Electrical Engineering and Computer Sciences UNIVERSITY OF CALIFORNIA, BERKELEY College of Engineering Department of Electrical Engineering and Computer Sciences Elad Alon Homework #2 EECS141 Due Thursday, September 9, 5pm, box in 240 Cory PROBLEM

More information