ESE 570: Digital Integrated Circuits and VLSI Fundamentals


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1 ESE 570: Digital Integrated Circuits and VLSI Fundamentals Lec 2: January 17, 2017 MOS Fabrication pt. 1: Physics and Methodology
2 Lecture Outline! Digital CMOS Basics! VLSI Fundamentals! Fabrication Process 2
3 Digital CMOS Basics 3
4 Classification of Digital CMOS Circuits! Static Circuit " In steadystate the output is evaluated via a lowimpedance path between the output and VDD or GND, respectively.! Dynamic Circuit " In steadystate the output is evaluated due to the presence or absence of charge, respectively, stored on the output node capacitance. 4
5 MOS Transistors S D G B G B D S 5
6 MOS Transistors S D G B G B D S 6
7 Ideal nmos and pmos Characteristics High Impedance or High Z G D S B D D S g = 0 S g = 1 D D S g = 1 S g = 1 g G S g D B a S S D b S Da g = 0 g = 0 D S b Da g = 1 g = 0 7
8 Complementary CMOS Switch g g g g g g g 8
9 Ideal CMOS Inverter Inverter Truth Table Inverter Symbol 9
10 CMOS Gates! Complementary Metal Oxide Semiconductor 10
11 CMOS Gates Inputs A B C D A B C D V DD PUN PDN PUN and PDN are Dual Networks When the PUN is conducting, the output F will be 1. Hence,the PUN is determined by a Boolean expression for the uncomplemented output F in terms of the complemented inputs (A,B,C,D). F = f(a,b,c,d) Output When the PDN is conducting, the output F will be 0. Hence,the PDN is determined by a Boolean expression for the complemented output F in terms of the uncomplemented inputs (A,B,C,D). 11
12 Static CMOS Source/Drains! With PMOS on top, NMOS on bottom " PMOS source always at top (near V dd ) " NMOS source always at bottom (near Gnd) " Why not use NMOS for pullup network? 12
13 What gate is this? a b f 13
14 Static CMOS Gate Structure! Drives railtorail " Power rails are V dd and Gnd " output is V dd or Gnd! Input connects to gates # load is capacitive! Once output node is charged doesn t use energy (no static current)! Output actively driven 14
15 TwoInput CMOS NOR Gate NOR A B F Z = High Impedance (open circuit) 15
16 TwoInput CMOS NAND Gate A F 1 1 B 1 0 Z = High Impedance (open circuit) 16
17 Gate Design Example! Design gate to perform: f = (a + b) c! Strategy: 1. Use static CMOS structure 2. Design PMOS pullup for f 3. Use DeMorgan s Law to determine f 4. Design NMOS pulldown for f 17
18 Gate Design Example! Design gate to perform: f = (a + b) c a b c f Convince yourself with a truth table. 18
19 Constructing Compound CMOS Gates F = (A B + C D) 19
20 VLSI Fundamentals
21 Oracle SPARC M7 Processor 21
22 VLSI Hierarchical Representations fabricated?  Circuit  Component 22
23 YChart: Abstractions in 3 Domains Behavioral Domain System Level Algorithmic Level RegisterTransfer Level System Specification Logic Level Algorithm RegisterTransfer Spec. Circuit Level Boolean Expression Transistor Model Equation Transistor Layout Standardcell/Subcell Layout Macrocell/Module Layout Block/Die Layout Chip/SoC/Board Structural Domain CPU, ASIC Processor, Subsystem ALU, Register, MUX Gate/Flipflop Transistor symbols Physical Domain 23
24 YChart: Abstractions in 3 Domains 24
25 Goal of All VLSI Design Enterprises! Convert system specs into an IC design in MINIMUM TIME and with MAXIMUM LIKLIHOOD that the Design will PEFORM AS SPECIFIED when fabricated.! MAX YIELD + MIN DEVELOPMENT TIME + MIN DIE AREA=> MIN COST 25
26 Fabrication Details
27 Silicon Ingot and Wafer Manufacturing Crystal Puller with rotation mechanism Crystal Seed SingleCrystal Silicon Molten Polysilicon Quartz Crucible Heating Element Heat Shield Water Image from Quirk & Serda Jacket 27
28 Silicon Wafer Manufacturing Si Ingots 300 mm (12 in.) Si Wafers! The ROI of 450mm wafers is compelling: " A 450mm fab with equal wafer capacity to a 300mm fab can produce 2x the amount of die. " A 14nm die from a 450mm wafer will cost 23% less than the same die from a 300mm wafer. 28
29 Silicon Lattice! Forms into crystal lattice Penn ESE Spring Fall Khanna 29
30 Silicon Lattice! Cartoon twodimensional view 30
31 Doping! Add impurities to Silicon Lattice " Replace a Si atom at a lattice site with another 31
32 Doping Elements! (periodic table) 32
33 Doping with P (Ntype)! End up with extra electrons " Donor electrons! Not tightly bound to atom " Low energy to displace " Easy for these electrons to move 33
34 Doping with B (Ptype)! End up with electron vacancies  Holes " Acceptor electron sites! Easy for electrons to shift into these sites " Low energy to displace " Easy for the electrons to move " Movement of an electron best viewed as movement of hole 34
35 IC Manufacturing Steps 35
36 Fabrication! Start with Silicon wafer! Dope! Grow Oxide (SiO 2 )! Deposit Metal! Mask/Etch to define where features go Time Code: 2:004:30 36
37 Photolithography 37
38 CMOS Processing Technology Boron atoms deposited on surface time = 0 s time = 60 s 38
39 Fabricated nmos Transistor 39
40 nmos Transistor Representations Physical Structure poly field metal 1 gate oxide S n + L drawn gate oxide n + p substrate (bulk) D L effective Layout Representation S G D n+ n+ L drawn W drawn Schematic Representation 40
41 nmos Transistor from a 3D Perspective Gate Oxide Field Oxide PType Source/Drain Regions Field Oxide 41
42 Fabrication Process Grow field oxide. Create contact window, deposit & pattern metal film. 42
43 Typical NWell CMOS Process 43
44 Typical NWell CMOS Process 44
45 Big Idea! Systematic construction of any gate from transistors with CMOS PUN and PDN! Hierarchical design process in three domains (behavioural, structural, and physical) allows for complicated designs motivated cost as a function of performance, yield and design time 45
46 Admin! Enroll in Piazza site " piazza.com/upenn/spring2017/ese570! Homework 1 due Thursday " Journal articles will come back in lecture 46
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