Lecture 4: Implementing Logic in CMOS


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1 Lecture 4: Implementing Logic in CMOS Mark Mcermott Electrical and Computer Engineering The University of Texas at ustin
2 Review of emorgan s Theorem Recall that: () = + and = ( + ) (+) = and + = ( ) () + ( + ) (+) + () Page 2
3 ubble Pushing Start with network of N / OR gates Convert to NN / NOR + inverters Push bubbles around to simplify logic (a) (b) (c) (d) Page 3
4 Static CMOS Circuits N and P channel networks implement logic functions Each network connected between Output and V or VSS Parallel network: "OR" function Series network: "N" function Page 4
5 uality in CMOS Circuits N and P networks must implement complementary functions uality is sufficient for correct operation P What are the values of, and C which will produce a connection between P and Q C + * C Q Page 5
6 Constructing Complex Gates Example: F = ( * ) + (C * ) Take uninverted function F = ( + C) and derive Nnetwork Identify N, OR components; F is OR of,c Make connections of transistors N, Series connection, OR, Parallel F C Page 6
7 Construction of Complex Gates, Cont d Construct Pnetwork by taking complement of Nexpression ( +C), which gives the expression, ( + ) * (C + ) Combine P and N circuits V C F C C Page 7
8 Layout of Complex Gate V NORINVERT (OI) gate Metal 2 V dd C C F Metal 1 F C Layout GN Page 8
9 Example of Compound Gate V F = ( + + C) * C F C Page 9
10 Example of More Complex Gate +V E C F G H OUT OUT = (+)*(C+)*(E+F+GH) C E F G H Page 10
11 ExclusiveNOR Gate in CMOS IN1 IN2 OUTPUT V P P P N N OUTPUT = + OUT P N IN1 () IN2 () N Page 11
12 Pseudo nmos Logic V Generally a weak device Z C E Page 12
13 uality is not Necessary Functions realized by N and P networks must be complementary, and one of them must conduct for every input combination V a b c d F = ab + a b + a c + cd + c d a b c a b c d d F The N and P networks are NOT duals, but the switching functions they implement are complementary a b "Hybrid" CMOS Circuit a b a c c d c d GN Page 13
14 Example of ual Rail Complex CMOS Gate V F = G z z F G = x x x x y y Page 14
15 Signal Strength Strength of signal How close it approximates ideal voltage source V and GN rails are strongest 1 and 0 nmos pass strong 0 ut degraded or weak 1 pmos pass strong 1 ut degraded or weak 0 Thus nmos are best for pulldown network Page 15
16 Pass Transistors Transistors can be used as switches s g d s s g = 0 g = 1 d d Input g = 1 Output 0 strong 0 g = 1 1 degraded 1 s g d s s g = 0 g = 1 d d Input g = 0 Output 0 degraded 0 g = 0 strong 1 Page 16
17 Transmission Gates Pass transistors produce degraded outputs Transmission gates pass both 0 and 1 well a g gb b g = 0, gb = 1 a b g = 1, gb = 0 a b Input Output g = 1, gb = 0 0 strong 0 g = 1, gb = 0 1 strong 1 a g b a g b a g b gb gb gb Page 17
18 Pass Transistor Logic What is the difference between the two circuits? P 1 C, C F(,,C) P 2 F(,) P 3 P 4 Page 18
19 Pass Transistor Logic  etter Layout Group similar transistors, so they can be in the same well P 4 F(,) P 3 P 2 P 1 Page 19
20 Pass Transistor Logic PullUp Version How do voltage levels at the output of this gate differ from that of the passtransistor multiplexer in the previous foil? F(,) Page 20
21 Tristates Tristate buffer produces Z when not enabled EN 0 0 EN EN 1 1 EN Page 21
22 Nonrestoring Tristate Transmission gate acts as Tristate buffer Only two transistors ut nonrestoring Noise on is passed on to EN EN Page 22
23 Tristate Inverter Tristate inverter produces restored output Violates conduction complement rule ecause we want a Z output EN EN EN = 0 = 'Z' EN = 1 = Page 23
24 Multiplexers (mux) 2:1 multiplexer chooses between two inputs S X X S 1 0 X X 1 Page 24
25 GateLevel Mux esign How many transistors are needed? = S + S 1 0 (too many transistors) 20 1 S 0 1 S Page 25
26 Transmission Gate Mux Nonrestoring mux uses two transmission gates Only 4 transistors if both of the select signals are available If not then it takes 6 transistors S 0 1 S S Page 26
27 Inverting Mux Inverting multiplexer Use compound OI22 Or pair of tristate inverters Essentially the same thing Noninverting multiplexer requires adding an inverter 0 S S S 1 S 0 S S 1 S S S Page 27
28 4:1 Multiplexer 4:1 mux chooses one of 4 inputs using two selects Two levels of 2:1 muxes Or four tristates Requires predecoded signals S1S0 S1S0 S1S0 S1S0 0 S0 S Page 28
29 Latch** When = 1, latch is transparent flows through to Q like a buffer When = 0, the latch is opaque Q holds its old value independent of Latch Q Q ** transparent latch or levelsensitive latch Page 29
30 Latch esign Multiplexer chooses or old Q 1 0 Q Q Q Q Page 30
31 Flipflop esign uilt from master and slave latches QM Q Latch QM Latch Q Page 31
32 Questions? Page 32
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