nmos IC Design Report Module: EEE 112

Transcription

1 nmos IC Design Report Author: Zhao Ruimin Module: EEE 112 Lecturer: Date: Dr.Zhao Ce Zhou June/5/2015

2 Abstract This lab intended to train the experimental skills of the layout designing of the nmosbased logic circuit and the understanding of the IC fabrication process. This report provided a brief summary of the fabrication techniques and process of IC chips, the detailed calculation process of the parameters required for designing the circuit such as aspect ratios of transistors, the resistance of resistor, and the the graph of the layout and masks that were drawn based on provided design rule. The IC fabrication process basically includes three steps which are Thin Film Formation, Photolithography and Doping. The design of the IC resistor and the nmos were all based on these principles. The relationship between the V OUT of NOR gate and the aspect ratio of its transistor is that the ratio increase with the increase of the voltage. The aspect ratios of three nmos placed in lower place in circuit were set to be 12 while the load transistor ratio was calculated to be 0.5. The set V OUT of the NOR gate was 0.1V which is less enough than the threshold voltage which was 0.3V, fits perfectly with the worst case where ratio is 12 and is not too small to increase the cost largely. The layout of the design drawn in grided coordinate paper is approximately 52λ 25λ. i

3 Contents Abstract Contents i ii 1 Introduction Background and Objective Apparatus Design Specification Design Rule List Parameter Methodology Theory Fabrication Process of IC chips Procedure Logic Date Truth Table Parameter Calculation Mask Drawing with Design Rule Discussion Outcome Layout Worst Case Anslysis Conclusion Achievement Limitation and Suggestion A Graph 12 A.1 Layout A.2 Masks ii

4 Section 1 Introduction 1.1 Background and Objective IC fabrication technique is an essential section for electronic engineering students to master. After gaining the skill of designing nmos-based logic gates circuit layout, it will be possible for us to design much more complicated circuit in the future when working on designing IC chips. In this particular lab, the layout of a simple logic circuit composed of a NOR gate and an inverter is required to be designed and minimised. The masks for each layer that is required for the manufacture of this circuit are expected to be drawn on a piece of grided paper. The target circuit is presented in Figure below: (a) (b) 1.2 Apparatus Table 1.1: Apparatus Apparatus Coordinate Paper Design Rule List Functionality Grided paper used to draw the layout on To be referred to when drawing the layout 1

5 1.3 Design Specification Design Rule List [1] Active Area Rules R 1 Minimum Active are Width 3λ R 2 Minimum Active are Spacing 3λ Poly-Silicon Rules R 3 Minimum Poly Width 2λ R 4 Minimum Poly Spacing 2λ R 5 Minimum Gate extension of Poly over Active 2λ R 6 Minimum Poly-Active Edge Spacing 1λ R 7 Minimum Poly-Active Edge Spacing 3λ Metal Rules R 8 Minimum Metal Width 3λ R 9 Minimum Metal Spacing 3λ Contact Rules R 1 0 Poly Contact size 2λ R 1 1 Minimum Poly Contact Spacing 2λ R 1 2 Minimum Poly Contact to Poly Edge Spacing 1λ R 1 3 Minimum Poly Contact to Metal Edge Spacing 1λ R 1 4 Minimum Poly Contact to Active Edge Spacing 3λ R 1 5 Active Contact size 2λ R 1 6 Minimum Active Contact Spacing 2λ R 1 7 Minimum Active Contact to Active Edge Spacing 1λ R 1 8 Minimum Active Contact to Metal Edge Spacing 1λ R 1 9 Minimum Active Contact to Poly Edge Spacing 2λ R 2 0 Minimum Active Contact Spacing 6λ Supply Rail Rules R 2 1 V DD > 3λ R 2 2 Ground > 3λ Resistor Rules R 2 3 Minimum resistor width 2λ Parameter Load Resistor: R L = 5kΩ Aspect Ratio: W L = 12(A/B/C); W L = 0.5(L) Normalized Device Constant: β 0 = A V 2 2

6 Section 2 Methodology 2.1 Theory [2] Fabrication Process of IC chips A nmos-based device mainly consists of four layers in terms of layout design including: Active layer Mask, Poly-Silicon layer Mask, Contact layer Mask and Metal Mask. To actually fabricate it, there are primarily three steps which are Thin Film Formation, Photolithography and Doping. Thin Film Formation First, the wafers serve as the bottom materials, and then thin and uniform deposited films ranging from metals to semiconductors and even to insulators are placed onto the wafers. There concrete commonly utilized placing process are oxidation, chemical vapour deposition (CVD) forming and physical vapour deposition (PVD). For the thermal oxidation, there are dry type and wet type: the dry type uses the reaction Si+O 2 SiO 2 and usually serves as gate oxide; while the wet type uses reaction Si + 2H 2 O SiO 2 + 2H 2 and usually serves as field oxide/diffusion barrier. Also, during the silicon-silicon dioxide interface moves into the silicon during this process. Figure 2.1: Thermal Oxidation 3

7 For the CVD, this process uses chemical reaction of a gas mixture to deposit a solid firm and usually used in depositing conformal. Also, it uses an energy source to break reactant gases into reactive species for deposition. (a) NOR gate (b) NOT gate Figure 2.2: CVD For the PVD, the first stage is evaporation where the materials to be deposited is heated to a high vapor pressure; the second stage is sputtering where some materials were sputtered away for subsequent deposition without any chemical reaction. Figure 2.3: PVD Photolithography The subsequent step is photolithography and etching. For the photolithography stage: a layer that is sensitive to ultraviolet (UV) radiation is put on the wafer and then this coated wafer is placed in an illumination system shining UV radiation through a lens mask. The etching removes materials selectively. Figure 2.4: UV Exposure 4

8 Doping This step has two stage: first is the thermal diffusion where dopant gases are fisted diffused into silicon and then turned off using silicon dioxide; and second is ion implantation where damaged region and non-saturation location are caused. The implantation stage possesses advantages including precise control of dose and depth profile, with low temperature and allow wide selection of materials. (a) NOR gate (b) NOT gate Figure 2.5: Dopant Diffusion nmos Fabrication This primarily consists of the four mask manufacture. First, the thermal oxidation was applied to build SiO2 layer upon a p-type silicon bulk. Then, Mask one was added to form the Active region and then, the top is coated with an oxide layer and a poly-si layer is subsequently placed using CVD. Then a gate layer is added as a Mask two after one more oxide layer. Next, it is exposed to the UV to be etched so as to be ready for being doped with n-type. Subsequently, the contact hole layer is placed as a Mask three after one more oxide layer added. Finally Mask four is established by taking away some sections of the just placed metal layer. IC Resistor Fabrication P-type silicon is used as substrate, and a thin oxide layer is placed onto the wafer. Then a n-type doped region is created using ion implantation, and another oxide layer is added after which the contact hole mask is placed. finally, the metal mask is used to pattern the metal after a metal layer is added. Figure 2.6: IC Resistor 5

9 2.2 Procedure Logic Date Truth Table The Boolean Expression of NOR gate is that OUT = A + B, while the expression of the NOT gate is that OUT = A. Therefore, by combining these two gates, we can obtain their output relation thus derive the relationship between the OUT in this particular project and the inputs A and B. The Truth Table of this logic gates composed of a NOR gate and a NOT gate in series is presented below, where 0 stands for LOW and 1 stands for HIGH. Table 2.1: Truth Table A B C OUT Parameter Calculation Aspect Ratio of NOR (a) NOR gate (b) NOT gate As can be seen in Figure above, in the NOR gate circuit, for both transistor A and transistor B, when their V DD = V in = 5V (High), the output voltage V OUT is expected to be Low due to the working principle of NOR gate. In this case of detailed calculation, we set V OUT = 0.1V, which is less than the threshold voltage V T H = 0.3V. 6

10 Subsequently, based on these assumptions and the rule of voltage division, the equivalent resistance of transistor channel can be obtained: V OUT V DD = Solving the equation above, we obtained R D = 100Ω. R D R D + R L (2.1) Then, we worked on the drain current I D. First, we decided that the mode is nonsaturation mode by observing that the drain-source voltage is in the same potential level with that of the output voltage V OUT, which has been assumed to be 0.1V, thus V g V T = = 4.7V > V OUT = V D must be correct. Therefore, according to the learnt formula for calculating the drain current, we obtain: I D = β 0 W L [(V g V T )V OUT V OUT 2 ] (2.2) 2 Also, by analysing the circuit configuration, it can be obtained that: R D = V OUT I D (2.3) Grouping the above two equations 2.2 and 2.3, and solving, we obtained that the aspect ratio for both two transistor A and B are all W L 12 Aspect Ratio of NOT The aspect ratio calculated for transistors in NOR gate could be also utilized here in inverter for the lower transistor as well. While for the Load transistor L, its drain-source voltage V DS can be obtained: Solving the above equation, we obtained that V DS V DS = V DD V OUT (2.4) = 4.9V, which is bigger than the saturation voltage V sat which is 4.7V. Therefore, the transistor L is also in saturation mode. Thus we obtained the drain current using formula: I D = β 0 W L V sat 2 Solving the above equation, we obtained that W L 0.5 Resistor 2 = 1mA (2.5) Finally, for the resistor, since it has a resistance of 5kΩ, the sheet resistance can be obtained is 100Ω/sq. Then we worked out the length-width ratio of it: We obtained that L W = 50. R = L W R S = 5kΩ (2.6) 7

11 2.2.3 Mask Drawing with Design Rule The process of drawing the layout graph was first simulated using software named L-Edit to help observing all the distances among sections clearly so as to ensure that the design can strictly agree with the Design Rule List. The masks graph drawn using software are presented below. (c) NOR gate (d) NOT gate (e) NOR gate (f) NOT gate Then, real drawing of the layout was conducted. Each smallest grid of that coordinate paper was regarded as 1λ, and each mask used numbers of grids. The pictures of graphs can be seen in Appendix A. 8

12 Section 3 Discussion 3.1 Outcome Layout Figure 3.1: The Layout Minimization During the drawing, the width was minimized as much as possible by for example setting the distance of contacts with adjacent poly edge to the minimum distance to achieve the goal of minimize the size of layout. Also, for the resistor, one terminal of it did not consume contact but saves the space by being connected with the active area directly. 9

13 Practical Approximation However, for the metal, the mask was not designed to be all in the minimum size since in the fabrication stage, metal mask is obtained by removing some part selectively and the cost of using slightly thinker or longer metal bar is not much thus the design of metal took the connection clarity and effectiveness as the top priority rather than simply the size. Also, for the resistor design, the real drawing of the resistor is 51 grids rather than 50 as calculated. This is to protect the circuit and ensure the clarity of the shape of the layout (avoid strange shape of resistor) since this slightly larger resistor can cause an output that is slightly less than 0.1V which still logically effective in this case. 3.2 Worst Case Anslysis When we set the V OUT of NOR gate, we first knew that this should be smaller than the threshold voltage V T which is 0.3V since the High or LOW is decided with regard to the V T in this logic system. Therefore, the V OUT should be set less enough than the V T. Then, we verify the real situation by setting the NOR V OUT to be V c. By varying the value of V c from 0.01V to 0.1. The worked out corresponding value of aspect ratio using the same method of that used in previous parameter calculation section was found to be increasing with the increase of the V c. However, if the V OUT is set too small thus much smaller than the worst case situation, the aspect ratio would be high thus increase the cost. Therefore, the set V OUT should be close to the one that meets the worst case. Practically, the worst case is where the NOR gate inputs are a 1(HIGH) and 0(LOW) respectively. When the V b and V a (inputs A and B) are all High, the calculated aspect ratio is 6, while when these two are a High and a Low, the calculated aspect ratio is 12 which is the worst case. Thus 0.1V should be a suitable value since it is not too large to break the circuit function nor too small to increase the cost. 10

14 Section 4 Conclusion 4.1 Achievement To conclude, this project deepened the understanding of the manufacturing processes of the MOS-based device and the calculations principles to obtain the aspect ratio for logic gates components. In this particular case, the aspect ratios of three MOS were are 12 while the load transistor ratio was calculated specially to be 0.5. After comprehensive verification using calculation and worst case analysis, it has been observed that increasing the (W/L) will decrease the output voltage. Here, we set the 4.2 Limitation and Suggestion One limitation of this project is that the layout pattern is quite fundamental without quite advanced minimization such as combing two parallel nmos together in one body. This was because that the drawing was conducted in a hurry without comprehensive online searching about the technique of minimizations that were not limited to those learnt in classes or set by Design Rule List. The corresponding future suggestion of this case is that source searching and enough interaction with teachers about intention of trying new techniques should be done before actually getting down to the task. 11

15 Appendix A Graph A.1 Layout Figure A.1: The Layout Figure A.2: The Scale Indication 12

16 A.2 Masks Mask One Figure A.3: Mask One Mask Two Figure A.4: Mask Two 13

17 Mask Three Figure A.5: Mask Three Mask Four Figure A.6: Mask Four 14

18 Reference [1] EEE112 Integrated Electronics and Design nmos IC Design Project, XJTLU [2] IC Fabrication Techniques Layouts: revision, XJTLU 15