ESE 570: Digital Integrated Circuits and VLSI Fundamentals


 Frank Garrett
 3 years ago
 Views:
Transcription
1 ESE 570: Digital Integrated Circuits and VLSI Fundamentals Lec 15: March 3, 2016 Combination Logic: Ratioed & Pass Logic, and Performance
2 Lecture Outline! CMOS NOR2 Worst Case Analysis! Pass Transistor Logic! Performance 2
3 Parasitic Caps for NOR2 (worst case) bn1 = bn2 = bp1 = bp2 = V x C sb1p = C sb2p = 2C g Cd V 1 = 0, V 2 = V DD > & V x V out = 0 > V DD 3
4 Parasitic Caps for NOR2 (worst case) bn1 = bn2 = bp1 = bp2 = V x C sb1p = C sb2p = 2C g Cd V 1 = 0, V 2 = V DD > & V x V out = 0 > V DD C loadnr C int + 2C g R peqv = R p2 +R p1 Elmore Model? 4
5 Parasitic Caps for NOR2 (worst case) V x 2C g 5
6 Parasitic Caps for NOR2 (worst case) V x 2C g τ = (2 )(R p2 )+(3 +C int +2C g )(R p1 +R p2 ) 6
7 Parasitic Caps for NOR2 (worst case) bn1 = bn2 = bp1 = bp2 = V x C sb1p = C sb2p = 2C g Cd V 1 = 0, V 2 = 0 >V & V x V out =V DD > 0 7
8 Parasitic Caps for NOR2 (worst case) bn1 = bn2 = bp1 = bp2 = V x C sb1p = C sb2p = 2C g Cd V 1 = 0, V 2 = 0 >V & V x V out =V DD > 0 Elmore Model? 8
9 Parasitic Caps for NOR2 (worst case) V x 2C g 9
10 Parasitic Caps for NOR2 (worst case) V x 2C g τ = (2 )(R p1 +R n2 )+(3 +C int +2C g )(R n2 ) 10
11 Pass Transistor Logic
12 Teaser! What does this do? 12
13 Identify Function! What function is this? 13
14 Output! What is Vout if A=1, B=1? A B Y
15 Output! What is Vout if A=1, B=1? A B Y
16 Output! What is Vout if A=0, B=1? A B Y
17 Output! What is Vout if A=0, B=1? A B Y
18 Output! What is Vout if A=0, B=0? if A=1, B=0? A B Y
19 Output! What is Vout if A=0, B=0? if A=1, B=0? A B Y
20 Area! Compare PT with CMOS circuit? 20
21 Output! Is this a regenerating/restoring gate? A B Y
22 Output! What does output look like (DC transfer)? " (B=1, notb=0, sweep A, nota=cmos inv(a)) 22
23 Pass TR transfer (B=1) Sweep A 23
24 CMOS Inverter Transfer 24
25 Reasonable Input to CMOS Inverter? 25
26 Pass Transistor xor2 with inv restore 26
27 Compare CMOS! Is this a fair comparison? 27
28 Required to use?! What should we add to make substitutable with CMOS? 28
29 Restore Output 29
30 Restore Output! Area? (compare to CMOS) 30
31 Chain Together 31
32 Analyze Stage 32
33 Delay A=1, B=0, C DB =iff =0? 33
34 Delay A=1, B=0, iff =0?! What s the equivalent RC circuit? 34
35 Delay A=1, B=0, iff =0?! What s the equivalent RC circuit? 35
36 Delay A=1, B=1, iff =0? 36
37 Delay A=1, B=1, iff =0?! What s the equivalent RC circuit? 37
38 Delay A=1, B=1, iff =0?! What s the equivalent RC circuit? " What are we ignoring? 38
39 iff >0 39
40 Contact/Diffusion Capacitance! C j diffusion depletion! C jsw sidewall capacitance! L S length of diffusion C = C L W + C ( 2L +W ) diff j S jsw S L S 40
41 Inverter Delay! Delay driving another minsized inverter? " Include iff W=1 41
42 Delay A=1, B=1, iff 0? (W=1) 42
43 Delay A=1, B=1, iff 0? (W=1)! What s the equivalent RC circuit? 43
44 Bonus! What does this do? A B Y B A 44
45 Transmission Gates
46 CMOS Transmission Gates 46
47 CMOS Transmission Gates Note at t = 0  : V in = 0, V out = 0 at t = 0 + : V in = 0 > V DD 47
48 CMOS Transmission Gates Note at t = 0  : V in = 0, V out = 0 at t = 0 + : V in = 0 > V DD  V Tp 48
49 CMOS Transmission Gates Note at t = 0  : V in = 0, V out = 0 at t = 0 + : V in = 0 > V DD  V Tp 49
50 CMOS Transmission Gates Note at t = 0  : V in = 0, V out = 0 at t = 0 + : V in = 0 > V DD  V Tp 50
51 CMOS Transmission Gates  V Tp 51
52 Transmission Gate, R eq k p ( V DD  V Tp ) 2 k p [2( V DD  V tp ) (V out V DD )  (V out V DD ) 2 ] k p [2( V DD  V tp )  (V out V DD )] k p [2( V DD  V tp )  (V out V DD )] 52
53 Transmission Gate, R eq 53
54 Transmission Gate, R eq 54
55 Transmission Gate Layouts 55
56 Performance Design
57 NOR2 Layout 57
58 NAND2 Layout 58
59 Layout of Complex CMOS Gate S DDS GND 59
60 Layout of Complex CMOS Gate 60
61 Layout of Complex CMOS Gate diffusion breaks d d d. d d i.e. n, p Euler paths with identical sequences of inputs 61
62 Minimize Number of Diffusion Paths 62
63 Minimize Number of Diffusion Paths 63
64 Minimize Number of Diffusion Paths 64
65 Minimize Number of Diffusion Paths 65
66 Gate Layout Algorithm! 1. Find all Euler paths that cover the graph! 2. Find common n and p Euler paths! If no common n and p Euler paths are found in step 2, partition the gate n and p graphs into the minimum number of subgraphs that will result in separate common n and p Euler paths 66
67 Idea! CMOS " Design for worst case input switching case and delay! There are other logic disciplines " Ratioed logic " Can use pass transistors for logic " Transmission gates " Will see in use in dynamic logic! Gate layout optimization " Euler Paths 67
68 Midterm Exam! Midterm 3/15 " In class in Towne 303 " Starts at exactly 4:30pm, ends at exactly 5:50pm (80 minutes) " Covers Lec 114 (slides 126) " Closed book, no notes or cheat sheets " Calculators allowed " Old exams posted online with and without solutions " Review Session by TA on Sunday 3/13 78:30pm in Moore 100C " Office Hours " cancelled during spring break, use Piazza for questions " Tania: Monday (3/14) 24pm and Tuesday (3/15) 122pm " Di and Ao: Monday (3/14) 79pm in TBD 68
69 Midterm Topics List! Identify CMOS/non CMOS! Any logic function #$ CMOS gate! Noise Margins! Circuit first order switching rise/fall times " Output equivalent resistance " Load capacitance! Transistor " Regions of operation " Parasitic Capacitance Model! Layout and stick diagrams! Sizing! Lumped 1 st order delay " Worst case estimation! Elmoredelay " Worst case estimation 69
70 Admin! Happy Spring Break! 70
Lecture Outline. ESE 570: Digital Integrated Circuits and VLSI Fundamentals. Review: 1st Order RC Delay Models. Review: TwoInput NOR Gate (NOR2)
ESE 570: Digital Integrated Circuits and VLSI Fundamentals Lec 14: March 1, 2016 Combination Logic: Ratioed and Pass Logic Lecture Outline! CMOS Gates Review " CMOS Worst Case Analysis! Ratioed Logic Gates!
More informationMidterm. ESE 570: Digital Integrated Circuits and VLSI Fundamentals. Lecture Outline. Pass Transistor Logic. Restore Output.
ESE 570: Digital Integrated Circuits and VLSI Fundamentals Lec 16: March 21, 2017 Transmission Gates, Euler Paths, Energy Basics Review Midterm! Midterm " Mean: 79.5 " Standard Dev: 14.5 2 Lecture Outline!
More informationLecture Outline. ESE 570: Digital Integrated Circuits and VLSI Fundamentals. Restore Output. Pass Transistor Logic. How compare.
ESE 570: igital Integrated ircuits and VLSI undamentals Lec 16: March 19, 2019 Euler Paths and Energy asics & Optimization Lecture Outline! Pass Transistor Logic! Logic omparison! Transmission Gates! Euler
More informationESE 570: Digital Integrated Circuits and VLSI Fundamentals
ESE 570: Digital Integrated Circuits and VLSI Fundamentals Lec 15: March 15, 2018 Euler Paths, Energy Basics and Optimization Midterm! Midterm " Mean: 89.7 " Standard Dev: 8.12 2 Lecture Outline! Euler
More informationName: Grade: Q1 Q2 Q3 Q4 Q5 Total. ESE370 Fall 2015
University of Pennsylvania Department of Electrical and System Engineering CircuitLevel Modeling, Design, and Optimization for Digital Systems ESE370, Fall 205 Midterm Wednesday, November 4 Point values
More information! Delay when A=1, B=0? ! CMOS Gates. " Dual pulldown and pullup networks, only one enabled at a time
ESE370: CircuitLevel Modeling, Design, and Optimization for Digital Systems Pass Transistor XOR Delay when A, B0? Start with equivalent RC circuit Lec : October 9, 08 Driving Large Capacitive Loads 3
More informationLecture 4: DC & Transient Response
Introduction to CMOS VLSI Design Lecture 4: DC & Transient Response David Harris Harvey Mudd College Spring 004 Outline DC Response Logic Levels and Noise Margins Transient Response Delay Estimation Slide
More informationLecture 6: DC & Transient Response
Lecture 6: DC & Transient Response Slides courtesy of Deming Chen Slides based on the initial set from David Harris CMOS VLSI Design Outline Pass Transistors DC Response Logic Levels and Noise Margins
More informationLecture 5: DC & Transient Response
Lecture 5: DC & Transient Response Outline q Pass Transistors q DC Response q Logic Levels and Noise Margins q Transient Response q RC Delay Models q Delay Estimation 2 Activity 1) If the width of a transistor
More informationCARNEGIE MELLON UNIVERSITY DEPARTMENT OF ELECTRICAL AND COMPUTER ENGINEERING DIGITAL INTEGRATED CIRCUITS FALL 2002
CARNEGIE MELLON UNIVERSITY DEPARTMENT OF ELECTRICAL AND COMPUTER ENGINEERING 18322 DIGITAL INTEGRATED CIRCUITS FALL 2002 Final Examination, Monday Dec. 16, 2002 NAME: SECTION: Time: 180 minutes Closed
More informationAnswers. Name: Grade: Q1 Q2 Q3 Q4 Total mean: 83, stdev: 14. ESE370 Fall 2017
University of Pennsylvania Department of Electrical and System Engineering CircuitLevel Modeling, Design, and Optimization for Digital Systems ESE370, Fall 2017 Midterm 2 Monday, November 6 Point values
More informationInterconnect (2) Buffering Techniques. Logical Effort
Interconnect (2) Buffering Techniques. Logical Effort Lecture 14 18322 Fall 2002 Textbook: [Sections 4.2.1, 8.2.3] A few announcements! M1 is almost over: The checkoff is due today (by 9:30PM) Students
More informationEE5780 Advanced VLSI CAD
EE5780 Advanced VLSI CAD Lecture 4 DC and Transient Responses, Circuit Delays Zhuo Feng 4.1 Outline Pass Transistors DC Response Logic Levels and Noise Margins Transient Response RC Delay Models Delay
More informationLecture 5: DC & Transient Response
Lecture 5: DC & Transient Response Outline Pass Transistors DC Response Logic Levels and Noise Margins Transient Response RC Delay Models Delay Estimation 2 Pass Transistors We have assumed source is grounded
More informationInterconnect (2) Buffering Techniques.Transmission Lines. Lecture Fall 2003
Interconnect (2) Buffering Techniques.Transmission Lines Lecture 12 18322 Fall 2003 A few announcements Partners Lab Due Times Midterm 1 is nearly here Date: 10/14/02, time: 3:004:20PM, place: in class
More informationESE 570: Digital Integrated Circuits and VLSI Fundamentals
ESE 570: Digital Integrated Circuits and VLSI Fundamentals Lec 10: February 16, 2016 MOS Inverter: Dynamic Characteristics Lecture Outline! Review: Symmetric CMOS Inverter Design! Inverter Power! Dynamic
More informationCMOS logic gates. João Canas Ferreira. March University of Porto Faculty of Engineering
CMOS logic gates João Canas Ferreira University of Porto Faculty of Engineering March 2016 Topics 1 General structure 2 General properties 3 Cell layout João Canas Ferreira (FEUP) CMOS logic gates March
More informationCPE/EE 427, CPE 527 VLSI Design I Delay Estimation. Department of Electrical and Computer Engineering University of Alabama in Huntsville
CPE/EE 47, CPE 57 VLSI Design I Delay Estimation Department of Electrical and Computer Engineering University of labama in Huntsville leksandar Milenkovic ( www.ece.uah.edu/~milenka ) Review: CMOS Circuit
More informationEE115C Digital Electronic Circuits Homework #5
EE115C Digital Electronic Circuits Homework #5 Due Thursday, May 13, 6pm @ 56147E EIV Problem 1 Elmore Delay Analysis Calculate the Elmore delay from node A to node B using the values for the resistors
More informationECE321 Electronics I
ECE31 Electronics Lecture 1: CMOS nverter: Noise Margin & Delay Model Payman ZarkeshHa Office: ECE Bldg. 30B Office hours: Tuesday :003:00PM or by appointment Email: payman@ece.unm.edu Slide: 1 CMOS
More informationESE 570: Digital Integrated Circuits and VLSI Fundamentals
ESE 570: Digital Integrated Circuits and VLSI Fundamentals Lec 24: April 19, 2018 Crosstalk and Wiring, Transmission Lines Lecture Outline! Crosstalk! Repeaters in Wiring! Transmission Lines " Where transmission
More informationEE115C Digital Electronic Circuits Homework #6
Problem 1 Sizing of adder blocks Electrical Engineering Department Spring 2010 EE115C Digital Electronic Circuits Homework #6 Solution Figure 1: Mirror adder. Study the mirror adder cell (textbook, pages
More information! Crosstalk. ! Repeaters in Wiring. ! Transmission Lines. " Where transmission lines arise? " Lossless Transmission Line.
ESE 570: Digital Integrated Circuits and VLSI Fundamentals Lec 24: April 19, 2018 Crosstalk and Wiring, Transmission Lines Lecture Outline! Crosstalk! Repeaters in Wiring! Transmission Lines " Where transmission
More informationDC and Transient. Courtesy of Dr. Daehyun Dr. Dr. Shmuel and Dr.
DC and Transient Courtesy of Dr. Daehyun Lim@WSU, Dr. Harris@HMC, Dr. Shmuel Wimer@BIU and Dr. Choi@PSU http://csce.uark.edu +1 (479) 575604 yrpeng@uark.edu Pass Transistors We have assumed source is
More informationEE371  Advanced VLSI Circuit Design
EE371  Advanced VLSI Circuit Design Midterm Examination May 1999 Name: No. Points Score 1. 20 2. 24 3. 26 4. 20 TOTAL / 90 In recognition of and in the spirit of the Stanford University Honor Code, I
More informationEEC 118 Lecture #6: CMOS Logic. Rajeevan Amirtharajah University of California, Davis Jeff Parkhurst Intel Corporation
EEC 118 Lecture #6: CMOS Logic Rajeevan mirtharajah University of California, Davis Jeff Parkhurst Intel Corporation nnouncements Quiz 1 today! Lab 2 reports due this week Lab 3 this week HW 3 due this
More informationIntegrated Circuits & Systems
Federal University of Santa Catarina Center for Technology Computer Science & Electronics Engineering Integrated Circuits & Systems INE 5442 Lecture 16 CMOS Combinational Circuits  2 guntzel@inf.ufsc.br
More information5. CMOS Gate Characteristics CS755
5. CMOS Gate Characteristics Last module: CMOS Transistor theory This module: DC Response Logic Levels and Noise Margins Transient Response Delay Estimation Transistor ehavior 1) If the width of a transistor
More informationVery Large Scale Integration (VLSI)
Very Large Scale Integration (VLSI) Lecture 4 Dr. Ahmed H. Madian Ah_madian@hotmail.com Dr. Ahmed H. MadianVLSI Contents Delay estimation Simple RC model PenfieldRubenstein Model Logical effort Delay
More informationEE 466/586 VLSI Design. Partha Pande School of EECS Washington State University
EE 466/586 VLSI Design Partha Pande School of EECS Washington State University pande@eecs.wsu.edu Lecture 9 Propagation delay Power and delay Tradeoffs Follow board notes Propagation Delay Switching Time
More informationEEC 118 Lecture #5: CMOS Inverter AC Characteristics. Rajeevan Amirtharajah University of California, Davis Jeff Parkhurst Intel Corporation
EEC 8 Lecture #5: CMOS Inverter AC Characteristics Rajeevan Amirtharajah University of California, Davis Jeff Parkhurst Intel Corporation Acknowledgments Slides due to Rajit Manohar from ECE 547 Advanced
More informationLecture Outline. ESE 570: Digital Integrated Circuits and VLSI Fundamentals. Review: CMOS Inverter: Visual VTC. Review: CMOS Inverter: Visual VTC
ESE 570: Digital Integrated Circuits and LSI Fundamentals Lec 0: February 4, 207 MOS Inverter: Dynamic Characteristics Lecture Outline! Review: Symmetric CMOS Inverter Design! Inverter Power! Dynamic Characteristics
More informationLecture 12 CMOS Delay & Transient Response
EE 471: Transport Phenomena in Solid State Devices Spring 2018 Lecture 12 CMOS Delay & Transient Response Bryan Ackland Department of Electrical and Computer Engineering Stevens Institute of Technology
More informationStatic CMOS Circuits. Example 1
Static CMOS Circuits Conventional (ratioless) static CMOS Covered so far Ratioed logic (depletion load, pseudo nmos) Pass transistor logic ECE 261 Krish Chakrabarty 1 Example 1 module mux(input s, d0,
More informationESE570 Spring University of Pennsylvania Department of Electrical and System Engineering Digital Integrated Cicruits AND VLSI Fundamentals
University of Pennsylvania Department of Electrical and System Engineering Digital Integrated Cicruits AND VLSI Fundamentals ESE570, Spring 2018 Final Monday, Apr 0 5 Problems with point weightings shown.
More informationVLSI Design, Fall Logical Effort. Jacob Abraham
6. Logical Effort 6. Logical Effort Jacob Abraham Department of Electrical and Computer Engineering The University of Texas at Austin VLSI Design Fall 207 September 20, 207 ECE Department, University of
More informationLogic Gate Sizing. The method of logical effort. João Canas Ferreira. March University of Porto Faculty of Engineering
Logic Gate Sizing The method of logical effort João Canas Ferreira University of Porto Faculty of Engineering March 016 Topics 1 Modeling CMOS Gates Chain of logic gates João Canas Ferreira (FEUP) Logic
More informationVLSI Design and Simulation
VLSI Design and Simulation Performance Characterization Topics Performance Characterization Resistance Estimation Capacitance Estimation Inductance Estimation Performance Characterization Inverter Voltage
More informationProperties of CMOS Gates Snapshot
MOS logic 1 Properties of MOS Gates Snapshot High noise margins: V OH and V OL are at V DD and GND, respectively. No static power consumption: There never exists a direct path between V DD and V SS (GND)
More informationMOSFET and CMOS Gate. Copy Right by Wentai Liu
MOSFET and CMOS Gate CMOS Inverter DC Analysis  Voltage Transfer Curve (VTC) Find (1) (2) (3) (4) (5) (6) V OH min, V V OL min, V V IH min, V V IL min, V OHmax OLmax IHmax ILmax NM L = V ILmax V OL max
More informationESE 570: Digital Integrated Circuits and VLSI Fundamentals
ESE 570: Digital Integrated Circuits and VLSI Fundamentals Lec 18: March 27, 2018 Dynamic Logic, Charge Injection Lecture Outline! Sequential MOS Logic " DLatch " Timing Constraints! Dynamic Logic " Domino
More informationEEC 116 Lecture #5: CMOS Logic. Rajeevan Amirtharajah Bevan Baas University of California, Davis Jeff Parkhurst Intel Corporation
EEC 116 Lecture #5: CMOS Logic Rajeevan mirtharajah Bevan Baas University of California, Davis Jeff Parkhurst Intel Corporation nnouncements Quiz 1 today! Lab 2 reports due this week Lab 3 this week HW
More informationHomework #2 10/6/2016. C int = C g, where 1 t p = t p0 (1 + C ext / C g ) = t p0 (1 + f/ ) f = C ext /C g is the effective fanout
0/6/06 Homework # Lecture 8, 9: Sizing and Layout of omplex MOS Gates Reading: hapter 4, sections 4.34.5 October 3 & 5, 06 hapter, section.5.5 Prof. R. Iris ahar Weste & Harris vailable on course webpage
More information9/18/2008 GMU, ECE 680 Physical VLSI Design
ECE680: Physical VLSI Design Chapter III CMOS Device, Inverter, Combinational circuit Logic and Layout Part 3 Combinational Logic Gates (textbook chapter 6) 9/18/2008 GMU, ECE 680 Physical VLSI Design
More informationUniversity of Toronto. Final Exam
University of Toronto Final Exam Date  Apr 18, 011 Duration:.5 hrs ECE334 Digital Electronics Lecturer  D. Johns ANSWER QUESTIONS ON THESE SHEETS USING BACKS IF NECESSARY 1. Equation sheet is on last
More information5.0 CMOS Inverter. W.Kucewicz VLSICirciuit Design 1
5.0 CMOS Inverter W.Kucewicz VLSICirciuit Design 1 Properties Switching Threshold Dynamic Behaviour Capacitance Propagation Delay nmos/pmos Ratio Power Consumption Contents W.Kucewicz VLSICirciuit Design
More informationand V DS V GS V T (the saturation region) I DS = k 2 (V GS V T )2 (1+ V DS )
ECE 4420 Spring 2005 Page 1 FINAL EXAMINATION NAME SCORE /100 Problem 1O 2 3 4 5 6 7 Sum Points INSTRUCTIONS: This exam is closed book. You are permitted four sheets of notes (three of which are your sheets
More informationEECS 141: SPRING 09 MIDTERM 2
University of California College of Engineering Department of Electrical Engineering and Computer Sciences J. Rabaey WeFr 23:30pm We, April 22, 2:003:30pm EECS 141: SPRING 09 MIDTERM 2 NAME Last First
More informationENEE 359a Digital VLSI Design
SLIDE 1 ENEE 359a Digital VLSI Design Prof. blj@eng.umd.edu Credit where credit is due: Slides contain original artwork ( Jacob 2004) as well as material taken liberally from Irwin & Vijay s CSE477 slides
More informationName: Answers. Grade: Q1 Q2 Q3 Q4 Q5 Total. ESE370 Fall 2015
University of Pennsylvania Department of Electrical and System Engineering CircuitLevel Modeling, Design, and Optimization for Digital Systems ESE370, Fall 2015 Midterm 1 Monday, September 28 5 problems
More informationName: Answers. Mean: 83, Standard Deviation: 12 Q1 Q2 Q3 Q4 Q5 Q6 Total. ESE370 Fall 2015
University of Pennsylvania Department of Electrical and System Engineering CircuitLevel Modeling, Design, and Optimization for Digital Systems ESE370, Fall 2015 Final Tuesday, December 15 Problem weightings
More informationESE 570: Digital Integrated Circuits and VLSI Fundamentals
ESE 570: Digital Integrated Circuits and VLSI Fundamentals Lec 17: March 26, 2019 Energy Optimization & Design Space Exploration Penn ESE 570 Spring 2019 Khanna Lecture Outline! Energy Optimization! Design
More informationEE141Fall 2011 Digital Integrated Circuits
EE4Fall 20 Digital Integrated Circuits Lecture 5 Memory decoders Administrative Stuff Homework #6 due today Project posted Phase due next Friday Project done in pairs 2 Last Lecture Last lecture Logical
More informationTopic 4. The CMOS Inverter
Topic 4 The CMOS Inverter Peter Cheung Department of Electrical & Electronic Engineering Imperial College London URL: www.ee.ic.ac.uk/pcheung/ Email: p.cheung@ic.ac.uk Topic 41 Noise in Digital Integrated
More informationEECS 141: FALL 05 MIDTERM 1
University of California College of Engineering Department of Electrical Engineering and Computer Sciences D. Markovic TuTh 111:3 Thursday, October 6, 6:38:pm EECS 141: FALL 5 MIDTERM 1 NAME Last SOLUTION
More informationLecture 11 VTCs and Delay. No lab today, Mon., Tues. Labs restart next week. Midterm #1 Tues. Oct. 7 th, 6:308:00pm in 105 Northgate
EE4Fall 2008 Digital Integrated Circuits Lecture VTCs and Delay Lecture # Announcements No lab today, Mon., Tues. Labs restart next week Midterm # Tues. Oct. 7 th, 6:308:00pm in 05 Northgate Exam is
More informationEE 434 Lecture 33. Logic Design
EE 434 Lecture 33 Logic Design Review from last time: Ask the inverter how it will interpret logic levels V IN V OUT V H =? V L =? V LARGE V H V L V H Review from last time: The twoinverter loop X Y X
More informationHomework Assignment #3 EE 477 Spring 2017 Professor Parker , .. = 1.8 , 345 = 0 
Homework Assignment #3 EE 477 Spring 2017 Professor Parker Note:! " = $ " % &' ( ) * ),! + = $ + % &' (, *,, .. = 1.8 , 345 = 0  Question 1: a) (8%) Define the terms V OHmin, V IHmin, V ILmax and V
More informationEE M216A.:. Fall Lecture 4. Speed Optimization. Prof. Dejan Marković Speed Optimization via Gate Sizing
EE M216A.:. Fall 2010 Lecture 4 Speed Optimization Prof. Dejan Marković ee216a@gmail.com Speed Optimization via Gate Sizing Gate sizing basics P:N ratio Complex gates Velocity saturation ti Tapering Developing
More informationECE321 Electronics I
ECE321 Electronics I Lecture 1: Introduction to Digital Electronics Payman ZarkeshHa Office: ECE Bldg. 230B Office hours: Tuesday 2:003:00PM or by appointment Email: payman@ece.unm.edu Slide: 1 Textbook
More informationCOMBINATIONAL LOGIC. Combinational Logic
COMINTIONL LOGIC Overview Static CMOS Conventional Static CMOS Logic Ratioed Logic Pass Transistor/Transmission Gate Logic Dynamic CMOS Logic Domino npcmos Combinational vs. Sequential Logic In Logic
More informationESE570 Spring University of Pennsylvania Department of Electrical and System Engineering Digital Integrated Cicruits AND VLSI Fundamentals
University of Pennsylvania Department of Electrical and System Engineering Digital Integrated Cicruits AND VLSI Fundamentals ESE570, Spring 017 Final Wednesday, May 3 4 Problems with point weightings shown.
More informationENEE 359a Digital VLSI Design
SLIDE 1 ENEE 359a Digital VLSI Design & Logical Effort Prof. blj@ece.umd.edu Credit where credit is due: Slides contain original artwork ( Jacob 2004) as well as material taken liberally from Irwin & Vijay
More informationESE 570: Digital Integrated Circuits and VLSI Fundamentals
ESE 570: Digital Integrated Circuits and VLSI Fundamentals Lec 17: March 23, 2017 Energy and Power Optimization, Design Space Exploration, Synchronous MOS Logic Lecture Outline! Energy and Power Optimization
More informationLecture 7 Circuit Delay, Area and Power
Lecture 7 Circuit Delay, Area and Power lecture notes from S. Mitra Intro VLSI System course (EE271) Introduction to VLSI Systems 1 Circuits and Delay Introduction to VLSI Systems 2 Power, Delay and Area:
More informationEE141Microelettronica. CMOS Logic
Microelettronica CMOS Logic CMOS logic Power consumption in CMOS logic gates Where Does Power Go in CMOS? Dynamic Power Consumption Charging and Discharging Capacitors Short Circuit Currents Short Circuit
More informationChapter 9. Estimating circuit speed. 9.1 Counting gate delays
Chapter 9 Estimating circuit speed 9.1 Counting gate delays The simplest method for estimating the speed of a VLSI circuit is to count the number of VLSI logic gates that the input signals must propagate
More informationTopics to be Covered. capacitance inductance transmission lines
Topics to be Covered Circuit Elements Switching Characteristics Power Dissipation Conductor Sizes Charge Sharing Design Margins Yield resistance capacitance inductance transmission lines Resistance of
More informationDigital Integrated Circuits A Design Perspective
igital Integrated Circuits esign Perspective esigning Combinational Logic Circuits 1 Combinational vs. Sequential Logic In Combinational Logic Circuit Out In Combinational Logic Circuit Out State Combinational
More informationDigital Integrated Circuits A Design Perspective
Digital Integrated Circuits Design Perspective Jan M. Rabaey nantha Chandrakasan orivoje Nikolić Designing Combinational Logic Circuits November 2002. 1 Combinational vs. Sequential Logic In Combinational
More information! Dynamic Characteristics. " Delay
EE 57: Digital Integrated ircuits and LI Fundamentals Lecture Outline! Dynamic haracteristics " Delay Lec : February, 8 MO Inverter and Interconnect Delay 3 Review: Propogation Delay Definitions Dynamic
More informationESE 570: Digital Integrated Circuits and VLSI Fundamentals
ESE 570: Digital Integrated Circuits and VLSI Fundamentals Lec 10: February 15, 2018 MOS Inverter: Dynamic Characteristics Penn ESE 570 Spring 2018 Khanna Lecture Outline! Inverter Power! Dynamic Characteristics
More informationVLSI Circuit Design (EEC0056) Exam
Mestrado Integrado em Engenharia Eletrotécnica e de omputadores VLSI ircuit esign (EE0056) Exam 205/6 4 th year, 2 nd sem. uration: 2:30 Open notes Note: The test has 5 questions for 200 points. Show all
More informationENGR890 Digital VLSI Design Fall Lecture 4: CMOS Inverter (static view)
ENGR89 Digital VLSI Design Fall 5 Lecture 4: CMOS Inverter (static view) [Adapted from Chapter 5 of Digital Integrated Circuits, 3, J. Rabaey et al.] [Also borrowed from Vijay Narayanan and Mary Jane Irwin]
More information! MOS Capacitances. " Extrinsic. " Intrinsic. ! Lumped Capacitance Model. ! First Order Capacitor Summary. ! Capacitance Implications
ESE 570: Digital Integrated Circuits and VLSI Fundamentals Lec 7: February, 07 MOS SPICE Models, MOS Parasitic Details Lecture Outline! MOS Capacitances " Extrinsic " Intrinsic! Lumped Capacitance Model!
More informationCMOS Digital Integrated Circuits Lec 10 Combinational CMOS Logic Circuits
Lec 10 Combinational CMOS Logic Circuits 1 Combinational vs. Sequential Logic In Combinational Logic circuit Out In Combinational Logic circuit Out State Combinational The output is determined only by
More informationUniversity of California at Berkeley College of Engineering Department of Electrical Engineering and Computer Sciences
University of California at Berkeley College of Engineering Department of Electrical Engineering and Computer Sciences EECS151/251A V. Stojanovic, J. Wawrzynek Fall 2015 10/13/15 Midterm Exam Name: ID
More informationDigital VLSI Design I
The University of Toledo Section f04ms  EES:460/560 Digital VLSI Design I: Basic Subsystems Digital VLSI Design I MIDTERM EXAMINATION Problems Points. 4. 3. 5 Total Was the exam fair? yes no The University
More informationESE 570: Digital Integrated Circuits and VLSI Fundamentals
ESE 570: Digital Integrated Circuits and VLSI Fundamentals Lec 19: March 29, 2018 Memory Overview, Memory Core Cells Today! Charge Leakage/Charge Sharing " Domino Logic Design Considerations! Logic Comparisons!
More informationIntroduction to Computer Engineering ECE 203
Introduction to Computer Engineering ECE 203 Northwestern University Department of Electrical Engineering and Computer Science Teacher: Robert Dick Office: L477 Tech Email: dickrp@ece.northwestern.edu
More informationDigital Integrated Circuits. The Wire * Fuyuzhuo. *Thanks for Dr.Guoyong.SHI for his slides contributed for the talk. Digital IC.
Digital Integrated Circuits The Wire * Fuyuzhuo *Thanks for Dr.Guoyong.SHI for his slides contributed for the talk Introduction The Wire transmitters receivers schematics physical 2 Interconnect Impact
More informationCMPEN 411 VLSI Digital Circuits. Lecture 04: CMOS Inverter (static view)
CMPEN 411 VLSI Digital Circuits Lecture 04: CMOS Inverter (static view) Kyusun Choi [Adapted from Rabaey s Digital Integrated Circuits, Second Edition, 2003 J. Rabaey, A. Chandrakasan, B. Nikolic] CMPEN
More informationEECS 312: Digital Integrated Circuits Midterm Exam 2 December 2010
Signature: EECS 312: Digital Integrated Circuits Midterm Exam 2 December 2010 obert Dick Show your work. Derivations are required for credit; end results are insufficient. Closed book. No electronic mental
More informationVLSI GATE LEVEL DESIGN UNIT  III P.VIDYA SAGAR ( ASSOCIATE PROFESSOR) Department of Electronics and Communication Engineering, VBIT
VLSI UNIT  III GATE LEVEL DESIGN P.VIDYA SAGAR ( ASSOCIATE PROFESSOR) contents GATE LEVEL DESIGN : Logic Gates and Other complex gates, Switch logic, Alternate gate circuits, Time Delays, Driving large
More informationEEE 421 VLSI Circuits
EEE 421 CMOS Properties Full railtorail swing high noise margins» Logic levels not dependent upon the relative device sizes transistors can be minimum size ratioless Always a path to V dd or GND in steady
More informationPractice 7: CMOS Capacitance
Practice 7: CMOS Capacitance Digital Electronic Circuits Semester A 2012 MOSFET Capacitances MOSFET Capacitance Components 3 Gate to Channel Capacitance In general, the gate capacitance is similar to a
More informationHomework Assignment #5 EE 477 Spring 2017 Professor Parker
Homework Assignment #5 EE 477 Spring 2017 Professor Parker Question 1: (15%) Compute the worstcase rising and falling RC time constants at point B of the circuit below using the Elmore delay method. Assume
More informationLecture Outline. ESE 570: Digital Integrated Circuits and VLSI Fundamentals. Total Power. Energy and Power Optimization. Worksheet Problem 1
ESE 570: Digital Integrated Circuits and VLSI Fundamentals Lec 16: March 20, 2018 Energy and Power Optimization, Design Space Exploration Lecture Outline! Energy and Power Optimization " Tradeoffs! Design
More informationESE570 Spring University of Pennsylvania Department of Electrical and System Engineering Digital Integrated Cicruits AND VLSI Fundamentals
University of Pennsylvania Department of Electrical and System Engineering Digital Integrated Cicruits AND VLSI Fundamentals ESE570, Spring 2016 Final Friday, May 6 5 Problems with point weightings shown.
More informationECE429 Introduction to VLSI Design
ECE429 Introduction to VLSI Design Lecture 5: LOGICAL EFFORT Erdal Oruklu Illinois Institute of Technology Some of these slides have been adapted from the slides provided by David Harris, Harvey Mudd College
More informationIntegrated Circuits & Systems
Federal University of Santa Catarina Center for Technology Computer Science & Electronics Engineering Integrated Circuits & Systems INE 5442 Lecture 14 The CMOS Inverter: dynamic behavior (sizing, inverter
More informationCMPEN 411 VLSI Digital Circuits Spring 2012
CMPEN 411 VLSI Digital Circuits Spring 2012 Lecture 09: Resistance & Inverter Dynamic View [Adapted from Rabaey s Digital Integrated Circuits, Second Edition, 2003 J. Rabaey, A. Chandrakasan, B. Nikolic]
More informationLecture 8: Combinational Circuits
Introduction to CMOS VLSI Design Lecture 8: Combinational Circuits David Harris Harvey Mudd College Spring 004 Outline ubble Pushing Compound Gates Logical Effort Example Input Ordering symmetric Gates
More information! Charge Leakage/Charge Sharing. " Domino Logic Design Considerations. ! Logic Comparisons. ! Memory. " Classification. " ROM Memories.
ESE 57: Digital Integrated Circuits and VLSI Fundamentals Lec 9: March 9, 8 Memory Overview, Memory Core Cells Today! Charge Leakage/ " Domino Logic Design Considerations! Logic Comparisons! Memory " Classification
More informationESE 570: Digital Integrated Circuits and VLSI Fundamentals
ESE 570: Digital Integrated Circuits and VLSI Fundamentals Lec 8: February 9, 016 MOS Inverter: Static Characteristics Lecture Outline! Voltage Transfer Characteristic (VTC) " Static Discipline Noise Margins!
More informationESE 570: Digital Integrated Circuits and VLSI Fundamentals
ESE 570: Digital Integrated Circuits and VLSI Fundamentals Lec 2: January 17, 2017 MOS Fabrication pt. 1: Physics and Methodology Lecture Outline! Digital CMOS Basics! VLSI Fundamentals! Fabrication Process
More informationCHAPTER 15 CMOS DIGITAL LOGIC CIRCUITS
CHAPTER 5 CMOS DIGITAL LOGIC CIRCUITS Chapter Outline 5. CMOS Logic Gate Circuits 5. Digital Logic Inverters 5.3 The CMOS Inverter 5.4 Dynamic Operation of the CMOS Inverter 5.5 Transistor Sizing 5.6 Power
More informationPassTransistor Logic
all 26 Digital tegrated ircuits nnouncements No new homework this week roject phase one due on Monday Midterm 2 next Thursday Review session on Tuesday Lecture 8 Logic Dynamic Logic EE4 EE4 2 lass Material
More informationStep 1. Finding V M. Goal: Þnd V M = input voltage for the output = V M both transistors are saturated at V IN = V M since
Step 1. Finding V M Goal: Þnd V M = input voltage for the output = V M both transistors are saturated at V IN = V M since V DSn = V M  0 > V M  V Tn V SDp = V DD  V M = (V DD  V M ) V Tp Equate drain
More informationAnnouncements. EE141 Spring 2003 Lecture 8. Power Inverter Chain
 Spring 2003 Lecture 8 Power Inverter Chain Announcements Homework 3 due today. Homework 4 will be posted later today. Special office hours from :303pm at BWRC (in lieu of Tuesday) Today s lecture Power
More information