ECE 342 Electronic Circuits. Lecture 34 CMOS Logic


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1 ECE 34 Electronic Circuits Lecture 34 CMOS Logic Jose E. SchuttAine Electrical & Computer Engineering University of Illinois 1
2 De Morgan s Law Digital Logic  Generalization ABC... ABC... ABC... ABC... Distributive Law AB AC BC BD A( B C) B( C D) General Procedure 1. Design PDN to satisfy logic function. Construct PUN to be complementary of PDN in every way 3. Optimize using distributive rule
3 CMOS Logic Gate Circuits Two Networks Pulldown network (PDN) with NMOS Pullup network (PUN) with PMOS PUN conducts when inputs are low and consists of PMOS transistors PDN consists of NMOS transistors and is active when inputs are high PDN and PUN utilize devices In parallel to form OR functions In series to form AND functions 3
4 PullDown Networks Y AB Y AB 4
5 PullUp Networks Y AB Y AB 5
6 Basic Logic Function Basic Function INVERTER NOR NAND Symbol # Devices PUN 1 PMOS PMOSSeries PMOSParallel # Devices PDN 1 NMOS NMOSParallel NMOSSeries Truth Table 6
7 PullDown and PullUp Functions Pullup network (PUN) Pulldown network (PDN) Key features When PDN switch is on, PUN switch is off and vice versa Conditions for being on and off are complementary 7
8 PullDown and PullUp PDNparallel NMOS PUNseries PMOS Truth Tables YDP AB YUS AB 8
9 PullDown and PullUp When Y DP in PDNparallel is low, this means that either A or B (or both) is high. When either A or B (or both) is high, either transistor (or both) in PUNseries are offy US =low When Y DP in PDNparallel is high, both A and B are low. Both transistors in PUNSeries are on creating a path to VDD. Y US =highy US =Y DP. PDNParallel and PUNseries are complementary 9
10 PullDown and PullUp PDNSeries NMOS PUNParallel PMOS YDS AB Truth Tables Y A B UP 10
11 PullDown and PullUp If Y DS is low, both A and B must be high in which case both transistors in PUNParallel are off providing no path to V DD Y UP =lowy UP =Y DS. If Y DS is high, then either A or B (or both) are off (low) in which case either Q PA or Q PB in PUNParallel will be on and present a path to V DD ; thus Y UP =high Y UP =Y DS PDNSeries and PUNParallel are complementary 11
12 TwoInput NOR Gate Y AB AB 1
13 TwoInput NOR Gate Actual Ideal 13
14 TwoInput NAND Gate Y AB AB 14
15 Y ABCD Using De Morgan s Law Example Y ABCD ABCD( AB) ( C D) Pulldown network Pullup network 15
16 Example 1 Evaluate Logic Function Y ( A B) C from pull down from pull up Y AB C AB C AB C ( A B) C 16
17 pull down Example Implement the function Y AB C pull up Y ABC ABC ( AB) C 17
18 ExclusiveOR (XOR) Function Y AB AB Y ( AB)( AB) XOR pull down A B Y pull up 18
19 Transistor Sizing Objectives PDN provides discharge current of at least that of an NMOS PUN provides charging current of at least that of a PMOS Worst case gate delay equal to that of basic inverter Find combination that results in lowest output current For transistors in parallel aspect ratios add For transistors in series, inverses of aspect ratios add Series :... W / L W / L W / L W / L eq 1 M Parallel : W / L W / L W / L... W / L eq 1 n W L p W L / p / n 19 M
20 Transistor Sizing NOR NAND 0
21 Transistor Sizing Example 1 Two approaches to realizing the OR function of six input variables. Assuming that the transistors in both circuits are properly sized to provide each gate with a currentdriving capability equal to that of the basic matched inverter, find the number of transistors and the total area of each circuit. Assume the basic inverter to have a (W/L) n ratio of 1. m/0.8 m and a (W/L) p ratio of 3.6 m/0.8 m
22 Transistor Sizing Example 1 For design (a), there are (6)+=14 transistors: All 7 NMOS use (W/L) n = n 1 PMOS uses (W/L) p = p 6 PMOS use (W/L) p = 6p Total Area = 7(1.)0.8+ 1(3.6) (6)(3.6)0.8 = m For design (b), there are (3) + 1()=16 transistors: 6 NMOS use (W/L) n = n 6 PMOS use (W/L) p = 3p PMOS use (W/L) p = p NMOS use (W/L) n = n Total Area = 70(1.)0.8 = 67. m, or 59% of (a)
23 Transistor Sizing Example Transistors in twoinput NOR gate are properly sized so that the currentdriving capability in each direction is equal to that of a matched inverter. For V t = 1 V and V DD = 5 V, find the gate threshold in the cases for which (a) input terminal A is connected to ground and (b) the two input terminals are tied together. Neglect the body effect in Q PB
24 Transistor Sizing Example Corresponding to a matched inverter characterized by n and p where k p =k n = k, the twoinput NOR uses transistors n and p where k p = k n a) For A grounded, V thb occurs near V DD /, with Q PB and Q NB in saturation and Q PA in triode. Let V th = v, and the voltage across Q PA be x Thus and and id k p 51 xx / i D kp xv i 1 1 D kn v 4
25 Transistor Sizing Example For k k, i k 4 xx / k 8xx p n D n n and and id kn 4 xv i 1 1 D kn v (1) () (3) v xv From ) 3): Thus, 1.707v x x v or, 0.93v 3.93 x x v 5
26 Transistor Sizing Example Now x 0, in which case, v / (ok) or v 3.93 / (Clearly too large) Thus, x v (4) v xx Now from 1) 3) : 1 8 With 4), v v v or v v v v5.83v or 6.83v v or 6.83v 6.81v
27 1/ whence v / (6.83) (1) Check: Transistor Sizing Example ( ) / V.5 V probably ok since one PMOS is full on Thus V.65V th b) For A and B joined, the PMOS can be approximated as a single device with twice the length, for which the width is twice that in a matched inverter. Thus, for the equivalent PMOS device, (W/L) peq = p and k p =k. For each of the two NMOS, (W/L) n = n and k n = k. Thus, at V th = v with all devices in saturation: k k id v1 5v1 7
28 Transistor Sizing Example v v and v v 1 4, 1 4 Thus 1.414v v,.414v whence V v.4v th See this is reduced from the singleinput value (of.65v)! Note that this fact can be used to control the relative threshold of multiple gates connected to a single fanout node, in order to guarantee operation sequence for slowly changing signals 8
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