ESE 570: Digital Integrated Circuits and VLSI Fundamentals
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1 EE 570: igital Integrated Circuits and VLI Fundamentals Lec 2: January 22, 2019 MO Fabrication pt. 1: Physics and Methodology
2 Lecture Outline! igital CMO Basics! VLI Fundamentals! Fabrication Process 2
3 igital CMO Basics 3
4 Classification of igital CMO Circuits igital Circuits tatic Circuits ynamic Circuits! tatic Circuit " In steady-state the output is evaluated via a low-impedance path between the output and V or GN, respectively. I.e the output is actively driven.! ynamic Circuit " In steady-state the output is evaluated due to the presence or absence of charge, respectively, stored on the output node capacitance. 4
5 MO Transistors G B G B 5
6 MO Transistors G B G B 6
7 Ideal nmo and pmo Characteristics G B g = 0 g = 1 g = 1 g = 1 7
8 Ideal nmo and pmo Characteristics G B g = 0 g = 1 g = 1 g = 1 8
9 Ideal nmo and pmo Characteristics G B g = 0 g = 1 g = 1 g = 1 g G g B a b a g = 0 g = 0 b a g = 1 g = 0 9
10 Ideal nmo and pmo Characteristics G B g = 0 g = 1 g = 1 g = 1 g G g B a b a g = 0 g = 0 b a g = 1 g = 0 10
11 Ideal CMO Inverter Inverter Truth Table Inverter ymbol 11
12 CMO Gates! Complementary Metal Oxide emiconductor 12
13 CMO Gates Inputs A B C A B C V PUN PN PUN and PN are ual Networks When the PUN is conducting, the output F will be 1. Hence,the PUN is determined by a Boolean expression for the un-complemented output F in terms of the complemented inputs (A,B,C,). F = f(a,b,c,) Output When the PN is conducting, the output F will be 0. Hence,the PN is determined by a Boolean expression for the complemented output F in terms of the un-complemented inputs (A,B,C,). 13
14 tatic CMO ource/rains! With PMO on top, NMO on bottom " PMO source always at top (near V dd ) " NMO source always at bottom (near Gnd) " Why not use NMO for pullup network? 14
15 What gate is this? A B F 15
16 tatic CMO Gate tructure! rives rail-to-rail " Power rails are V dd and Gnd " output is V dd or Gnd! Input connects to gates # load is capacitive! Once output node is charged doesn t use energy (no static current only leakage)! Output actively driven 16
17 Two-Input CMO NOR Gate NOR A B F 0 U = Low Impedance (short circuit) Z = High Impedance (open circuit) 17
18 Two-Input CMO NAN Gate F A Out 2 1 B = Low Impedance (short circuit) Z = High Impedance (open circuit) 18
19 Two-Input CMO NAN Gate A F Out 0 U 0 U 1 1 B U = Low Impedance (short circuit) Z = High Impedance (open circuit) 19
20 Gate esign Example! esign gate to perform: f = (a + b) c! trategy: 1. Use static CMO structure 2. esign PMO pullup for f 3. Use emorgan s Law to determine f 4. esign NMO pulldown for f 20
21 Gate esign Example! esign gate to perform: f = (a + b) c a b c f Convince yourself with a truth table. 21
22 Constructing Compound CMO Gates F = (A B + C ) 22
23 VLI Fundamentals
24 Oracle PARC M7 Processor 24
25 VLI Hierarchical Representations! Complex digital systems can be sub-divided in a hierarchical manner! Highly automated techniques exist for converting high level descriptions of system behaviour to a detailed implementation prescription to fabricate a chip! To do this, a set of abstractions and domains have been developed to describe integrated electronic systems 25
26 esign omains! esigns are represented in three domains " Behavioral What does the system do? " tructural How are the elements connected? " Physical How is the structure to be fabricated? 26
27 esign Abstractions! Each domain can be specified at a variety of levels of abstraction " Architectural " Algorithmic " Module or Functional Block " Logical " witch " Circuit Higher Level Lower Level 27
28 Y-Chart: Abstractions in three omains Behavioral omain ystem Level Algorithmic Level Register-Transfer Level ystem pecification Logic Level Algorithm Register-Transfer pec. Circuit Level Boolean Expression Transistor Model Equation Transistor Layout tandard-cell/ub-cell Layout Macro-cell/Module Layout Block/ie Layout Chip/oC/Board tructural omain CPU, AIC Processor, ub-system ALU, Register, MUX Gate/Flip-flop Transistor symbols Physical omain 28
29 Y-Chart: Abstractions in three omains 29
30 Goal of All VLI esign Enterprises! Convert system specs into an IC design in MINIMUM TIME and with MAXIMUM LIKLIHOO that the esign will PEFORM A PECIFIE when fabricated.! MAX YIEL + MIN EVELOPMENT TIME + MIN IE AREA=> MIN COT 30
31 Fabrication etails
32 ilicon Ingot and Wafer Manufacturing Crystal Puller with rotation mechanism Crystal eed ingle-crystal ilicon Quartz Crucible Heating Element Molten Polysilicon Heat hield Water Jacket Image from Quirk & erda 32
33 ilicon Wafer Manufacturing i Ingots 300 mm (12 in.) i Wafers! The ROI of 450mm wafers is compelling: " A 450mm fab with equal wafer capacity to a 300mm fab can produce 2x the amount of die. " A 14nm die from a 450mm wafer will cost 23% less than the same die from a 300mm wafer. 33
34 ilicon Lattice! Forms into crystal lattice 34
35 ilicon Lattice! Cartoon two-dimensional view 35
36 oping! Add impurities to ilicon Lattice " Replace a i atom at a lattice site with another 36
37 oping Elements! (periodic table) 37
38 oping with P (N-type)! End up with extra electrons " onor electrons! Not tightly bound to atom " Low energy to displace " Easy for these electrons to move 38
39 oping with B (P-type)! End up with electron vacancies -- Holes " Acceptor electron sites! Easy for electrons to shift into these sites " Low energy to displace " Easy for the electrons to move " Movement of an electron best viewed as movement of hole 39
40 IC Manufacturing teps 40
41 Fabrication! tart with ilicon wafer! ope! Grow Oxide (io 2 )! eposit Metal! Mask/Etch to define where features go Time Code: 2:00-4:30 41
42 Photolithography 42
43 CMO Processing Technology Boron atoms deposited on surface time = 0 s time = 60 s 43
44 Fabricated n-mo Transistor 44
45 n-mo Transistor Representations Physical tructure poly field metal 1 gate oxide n + L drawn gate oxide n + p substrate (bulk) L effective Layout Representation G n+ n+ L drawn W drawn chematic Representation 45
46 nmo Transistor from a 3 Perspective Gate Oxide Field Oxide P-Type ource/rain Regions Field Oxide 46
47 Fabrication Process Grow field oxide. Create contact window, deposit & pattern metal film. 47
48 Typical N-Well CMO Process 48
49 Typical N-Well CMO Process 49
50 Big Idea! ystematic construction of any gate from transistors with CMO PUN and PN! Hierarchical design process in three domains (behavioural, structural, and physical) allows for complicated designs motivated cost as a function of performance, yield and design time 50
51 Admin! New classroom: Towne 311! Behind the scenes programming note: " Additional grader: Yifeng Zhang! Enroll in Piazza site " piazza.com/upenn/spring2019/ese570! Homework 1 due Friday " Journal articles may show up in lecture 51
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