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1 ESE 57: Digital Integrated Circuits and VLSI Fundamentals Lec 9: March 9, 8 Memory Overview, Memory Core Cells Today! Charge Leakage/ " Domino Logic Design Considerations! Logic Comparisons! Memory " Classification " ROM Memories " RAM Memory " Architecture " Memory core " SRAM " DRAM " Periphery (time permitting) Penn ESE 57 Spring 8 - Khanna Charge Leakage 4 Charge Storage and Leakage Example Overview: Min Hold Time! Find min voltage value for storage node to maintain data " V x = voltage across storage capacitor! With dimensions of switch MOS and load MOS " Calculate C ext = C gb + C int = C gb + C poly + C metal " Calculate C j = junction capacitance! With max leakage value " Calculate min hold time (i.e. min time for storage capacitor to leak to min V x ) C x min C x min min(t hold ) = Δt = ΔV x = (V x max V x min ) I leakage max I leakage max 5 Penn ESE 57 Spring 8 - Khanna 6

2 Dynamic Circuit Techniques 8 Shift Register! Shift registers store and delay data! Simple design: cascade of latches Shift Register with Dynamic D Latches D D- D- ϕ Latch ϕ Latch ϕ D- Latch Out When V out(i) = V (or 5V) and V in(i+) = 5V (or V) for i =, (stage) is an issue when ϕ /ϕ close. 9 >> V a >> V a

3 Rule of Thumb make C out = C in >> V a << V a 3 4 << V a << V a C in If = and V a >> # V R C out + C in C in If = and V a >> # V R C out + C in 5 If C out >> C in # V R C in << C out 6 << V a Rule of Thumb make C out = C in Domino Logic Design Considerations C in If = and V a >> # V R C out + C in If C out >> C in # V R C in << C out 7 3

4 Requirements Cascaded Domino CMOS Logic Gates! Single transition " Once transitioned, it is done # like domino falling! All inputs at during precharge " Outputs pre-charged to then inverted to " I.e. Inputs are pre-charge to! Non-inverting gates propagating 9 Pre-charge Leakage within PDN weak keeper (W/L) p-keeper < (W/L) n-min within PDN within PDN 3 4 4

5 within PDN within PDN 5 6 within PDN P Since all nodes are precharged there is no chargesharing. Z4 Z = G + P * P Z = G + P * G + P * P * P = G + P * Z Z3 = G3 + P3 * G + P3 * P * G + P3 * P * P * P = G3 + P3 * Z Z4 = G4 + P4 * G3 + P4 * P3 * G + P4 * P3 * P * G + P4 * P3 *P * P = G4 + P4 * Z3 C 4 C 3 C C Z3 Z Z 7 CMOS Logic! Best option in the majority of CMOS circuits! Advantages: " Noise-immunity not sensitive to k n /k p " does not involve pre-charging of nodes " dissipates no DC power " layout can be automated! Disadvantages: " Large fan-in gates lead to complex circuit structures (N transistors) " larger parasitics " slower and higher dynamic power dissipation than alternatives " no clock and no synchronization. 8 Pseudo-nMOS/Ratioed Logic! Finds widest utility in large fan-in gates! Advantages: " Requires only N+ transistors for N fan-in " smaller parasitics " faster and lower dynamic power dissipation than full CMOS! Disadvantages: " Noise-immunity sensitive to k n /k p " dissipates DC power when pulled down " not well-suited for automated layout " no clock and no synchronization. CMOS domino-logic! Used for low-power, high-speed applications.! Advantages: " Requires N+k transistors for N fan-in (size advantages of pseudonmos) " dissipates no DC power " noise immunity not sensitive to k n /k p " use of clocks enables synchronous operation! Disadvantages: " Relies on storage on soft nodes " will require thorough simulation at all the process corners to insure proper operation " some of the speed advantage over static gates is diminished by the required pre-charge (pre-discharge) time 9 3 5

6 CPU Memory Hierarchy Memory Overview CPU Chip L on-cpu cache off-chip cache memory L L3 L4 k to 64 k SRAM (register file) 64k to 4M 4M to 3M SRAM or DRAM 8M 3 Locality and Cacheing Semiconductor Memory Classification! Memory hierarchies exploit locality by cacheing (keeping close to the processor) data likely to be used again! This is done because we can build " large, slow memories OR " small, fast memories BUT " we can t build large, fast memories! If hierarchy works, we get the illusion of SRAM access time with disk based memory capacity. " SRAM (static RAM) ns access time, very expensive (on-cpu faster) " DRAM (dynamic RAM) ns, cheaper " Disk -- access time measured in milliseconds, very cheap Random Access SRAM DRAM RWM NVRWM ROM Non-Random Access FIFO LIFO Shift Register CAM EPROM E PROM FLASH Mask-Programmed Programmable (PROM) 33 Penn ESE 57 Spring 8 - Khanna Memory Architecture: Core Memory Architecture: Decoders M bits M bits M bits M bits N Words S S S S N- S N_ Word Word Word Word N- Word N- Storage Cell A A A K- Decoder S Word Word Word Word N- Word N- Storage Cell N Words S S S S N- S N_ Word Word Word Word N- Word N- Storage Cell A A A K- Decoder S Word Word Word Word N- Word N- Storage Cell Input-Output (M bits) Input-Output (M bits) Input-Output (M bits) Input-Output (M bits) N words => N select signals Too many select signals Decoder reduces # of select signals K = logn N words => N select signals Too many select signals Decoder reduces # of select signals K = logn Penn ESE 57 Spring 8 - Khanna Penn ESE 57 Spring 8 - Khanna 6

7 Array-Structured Memory Architecture Latches/Register Can Store a State Problem: ASPECT RATIO or HEIGHT >> WIDTH L-K Bit Line Storage Cell! Build master-slave register from pair of latches! Control with non-overlapping clocks A K A K+ A L- Row Decoder Word Line Sense Amplifiers / Drivers M. K Amplify swing to rail-to-rail amplitude A A K- Column Decoder Selects appropriate word Input-Output (M bits) Penn ESE 57 Spring 8 - Khanna Penn ESE 57 Spring 8 - Khanna 38 MOS NOR ROM ROM Memories [] [] [] [3] [] [] [] [3] Penn ESE 57 Spring 8 - Khanna 39 Penn ESE 57 Spring 8 - Khanna MOS NOR ROM MOS NOR ROM [] [] [] [] [] [3] [] [3] [] [] [] [3] [] [] [] [3] Penn ESE 57 Spring 8 - Khanna Penn ESE 57 Spring 8 - Khanna 7

8 MOS NOR ROM MOS NOR ROM [] [] [] [] [3] [] [] [3] [] [] [] [3] [] Penn ESE 57 Spring 8 - Khanna [] [] [3] Penn ESE 57 Spring 8 - Khanna MOS NAND ROM MOS NAND ROM [] [] [] [3] [] [] [] [] [] [] [] [3] [3] All word lines high by default with exception of selected row Penn ESE 57 Spring 8 - Khanna [] [] [3] All word lines high by default with exception of selected row Penn ESE 57 Spring 8 - Khanna MOS NAND ROM MOS NAND ROM [] [] [] [] [3] [] [] [] [] [] [] [3] [3] All word lines high by default with exception of selected row Penn ESE 57 Spring 8 - Khanna [] [] [3] All word lines high by default with exception of selected row Penn ESE 57 Spring 8 - Khanna 8

9 Non-Volatile Memory ROM Contact-Mask Programmable ROM PseudonMOS NOR gate 49 5 Contact-Mask Programmable ROM Read-Write Memories (RAM)! Static (SRAM) " Data stored as long as supply is applied " Large (6 transistors/cell) " Fast " Differential! Dynamic (DRAM) " Periodic refresh required " Small (-3 transistors/cell) " Slower " Single ended 5 Penn ESE 57 Spring 8 - Khanna 6T SRAM Cell 6-transistor CMOS SRAM Cell! Cell size accounts for most of memory array size! 6T SRAM Cell " Used in most commercial chips " Data stored in cross-coupled inverters! Read: " Precharge, bit " Raise word! Write: " Drive data onto, " Raise bit_b M M M3 53 Penn ESE 57 Spring 8 - Khanna 9

10 6-transistor CMOS SRAM Cell 6-transistor CMOS SRAM Cell M Assume is stored (=) M M M3 M M3 Penn ESE 57 Spring 8 - Khanna Penn ESE 57 Spring 8 - Khanna CMOS SRAM Analysis (stored ) 6-transistor CMOS SRAM Cell = M = Assume is stored (=) Read Operation: - First bitlines get precharged high (Vdd) - Then wordline goes high (Vdd) M M M3 Penn ESE 57 Spring 8 - Khanna Penn ESE 57 Spring 8 - Khanna CMOS SRAM Analysis (Read) CMOS SRAM Analysis (Read) = = = = V M V M k n, ΔV V Tn ( ) = k n,m ( V Tn )ΔV ΔV k n, V Tn k nm, ( V ) = Tn V DD (W/L)n, (W/L)n,M (supercedes read constraint) Penn ESE 57 Spring 8 - Khanna Penn ESE 57 Spring 8 - Khanna

11 CMOS SRAM Analysis (Read) CMOS SRAM Analysis (Read) = = = = V M V M W k n,m L ( V DD ΔV V Tn ) = = k n,m 5 W (V L DD V Tn )ΔV ΔV Penn ESE 57 Spring 8 - Khanna 5 W k n,m L ( V DD ΔV V Tn ) = = k n,m 5 W (V L DD V Tn )ΔV ΔV Penn ESE 57 Spring 8 - Khanna 5 ΔV =V Tn W L ( V DD V Tn ) = W (V DD.5V Tn )V Tn L 5 CMOS SRAM Analysis (Read) CMOS SRAM Analysis (Read) Voltage Rise (V) V = M =.5..5 Cell Ratio (CR).5 3 Penn ESE 57 Spring 8 - Khanna 6-transistor CMOS SRAM Cell CMOS SRAM Analysis (Write) Assume is stored (=) Write Operation: - Want to write a - First drive bitlines with input data - Then wordline goes high (Vdd) M M M3 k n, ( V ) Tn = = = M k p, ( V ) Tp = = (W/L) n,.33 (W/L) p, k n, V Tn kn, ( M ) V DD V VTn DD = (W/L) n, (W/L) n,m Penn ESE 57 Spring 8 - Khanna Penn ESE 57 Spring 8 - Khanna

12 CMOS SRAM Analysis (Write) CMOS SRAM Analysis (Write) = = = = M M = = = = Penn ESE 57 Spring 8 - Khanna ( ) = k n,m 4 ( V Tp )V V k n,m 6 V Tn k n,m 4 k n,m 6 = ( V Tn ) ( V Tp )V V Penn ESE 57 Spring 8 - Khanna CMOS SRAM Analysis (Write) CMOS SRAM Analysis (Write) = = PR = W 4 L 4 W 6 L 6 PR = W 4 L 4 W 6 L 6 M = = k n,m 4 k n,m 6 = ( V Tn ) ( V Tp )V V V =V Tn k n,m 4 k n,m 6 = ( V Tn ) ( V Tp )V Tn V Tn Penn ESE 57 Spring 8 - Khanna CMOS SRAM Analysis (Write) DRAM = = PR = W 4 L 4 W 6 L 6! Smaller than SRAM! Require data refresh to compensate for leakage M = = Penn ESE 57 Spring 8 - Khanna 7

13 3-Transistor DRAM Cell -Transistor DRAM Cell W W Write "" Read "" R R M C S X V T X M3 M M C S X -VT -VT No constraints on device ratios Reads are non-destructive Value stored at node X when writing a = V W-V Tn ΔV C / C ΔV V V ( PRE V BIT V ) S = = PRE C S + C sensing / Write: CS is charged or discharged by asserting and. Read: Charge redistribution takes places between bit line and storage capacitance Voltage swing is small; typically around 5 mv. DRAM Cell Observations! T DRAM requires a sense amplifier for each bit line, due to charge redistribution read-out! DRAM memory cells are single ended in contrast to SRAM cells! The read-out of the T DRAM cell is destructive " Read and refresh operations are necessary for correct operation! Unlike 3T cell, T cell requires presence of an extra capacitance that must be explicitly included in the design! When writing a into a DRAM cell, a threshold voltage is lost " This charge loss can be circumvented by bootstrapping the word lines to a higher value than Idea! Memory for compact state storage! Share circuitry across many bits " Minimize area per bit # maximize density! Aggressively use: " Pass transistors, Ratioing " Precharge, Amplifiers to keep area down Penn ESE 57 Spring 8 - Khanna 76 Admin! Homework 7 due Thursday! Final Project " Design and layout memory " Handout posted before Thursday class " Due 4/4 (last day of class) " Everyone gets an extension until 5/4 " Keep in mind our final exam is on 4/3 " Leave time to study! Penn ESE 57 Spring 8 - Khanna 77 3

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