Midterm. ESE 570: Digital Integrated Circuits and VLSI Fundamentals. Lecture Outline. Pass Transistor Logic. Restore Output.


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1 ESE 570: Digital Integrated Circuits and VLSI Fundamentals Lec 16: March 21, 2017 Transmission Gates, Euler Paths, Energy Basics Review Midterm! Midterm " Mean: 79.5 " Standard Dev: Lecture Outline! Pass Transistor Logic! Euler Path for Layout! Energy and Power Basics! Energy and Power Optimization Pass Transistor Logic 3 Output! What is Vout if A=0, B=0? if A=1, B=0? Restore Output A B Y
2 Chain Together Analyze Stage 7 8 Delay A=1, B=1, C diff 0? (W=1) Delay A=1, B=1, C diff 0? (W=1)! What s the equivalent RC circuit? 9 10 Transmission Gates CMOS Transmission Gates 12 2
3 CMOS Transmission Gates CMOS Transmission Gates Note at t = 0  : V in = 0, V out = 0 at t = 0 + : V in = 0 > V DD Note at t = 0  : V in = 0, V out = 0 at t = 0 + : V in = 0 > V DD 13  V Tp 14 CMOS Transmission Gates CMOS Transmission Gates Note at t = 0  : V in = 0, V out = 0 at t = 0 + : V in = 0 > V DD Note at t = 0  : V in = 0, V out = 0 at t = 0 + : V in = 0 > V DD  V Tp 15  V Tp 16 CMOS Transmission Gates Transmission Gate, R eq k p ( V DD  V Tp ) 2 k p [2( V DD  V tp ) (V out V DD )  (V out V DD ) 2 ] k p [2( V DD  V tp )  (V out V DD )]  V Tp 17 k p [2( V DD  V tp )  (V out V DD )] 18 3
4 Transmission Gate, R eq Transmission Gate, R eq Transmission Gate Layouts Performance Design 21 NOR2 Layout NAND2 Layout
5 Layout of Complex CMOS Gate Layout of Complex CMOS Gate S DDS GND Layout of Complex CMOS Gate Minimize Number of Diffusion Paths diffusion breaks d d d. d d i.e. n, p Euler paths with identical sequences of inputs Minimize Number of Diffusion Paths Minimize Number of Diffusion Paths
6 Minimize Number of Diffusion Paths Gate Layout Algorithm! 1. Find all Euler paths that cover the graph! 2. Find common n and p Euler paths! 3. If no common n and p Euler paths are found in step 2, partition the gate n and p graphs into the minimum number of subgraphs that will result in separate common n and p Euler paths Digital Logic: Gate Level Review Motivation, Abstraction, and Design Tradeoffs! We care about design for performance " Functionality (e.g. F = A + B*C) " Speed " Each gate has a delay caused by the output resistance and capacitive load (which is the input capacitive load of the gate on the output) " Critical path defines delay " Power " Switching power (comprised of dynamic and short circuit power) and static power (I.e P tot =P dyn +P SC + P stat ) " Area " For a gate the standard cell area, dependent on W and L of transistors 34 Digital Logic: Transistor Level Digital Logic: Transistor Level! We care about design for performance " Functionality (e.g. F = A + B*C) " Design for abstraction (VTC: switching voltage, high gain, noise margins) " Speed " Transistor sizing affects the output resistance and capacitance " Power " Switching power (comprised of dynamic and short circuit power) and static power (I.e P tot =P dyn +P SC + P stat ). Transistor sizing affects drive current and impacts power consumption " Area " For a gate the standard cell area, dependent on W and L of transistors
7 Review: MOS Inverter Dynamic Performance Review: nmos IV Characteristics! ANALYSIS (OR SIMULATION): For a given MOS inverter schematic and C load, estimate (or measure) the propagation delays! DESIGN: For given specs for the propagation delays and C load*, determine the MOS inverter schematic METHODS: 1. Average Current Model ΔV HL V τ PHL C load = C OH V 50% load I avg,hl I avg,hl 2. Differential Equation Model dv i C = C out dv load dt = C load out dt dt τ PHL or τ PLH 3. 1 st Order RC delay Model τ PHL 0.69 C load R n i C Assume V in ideal 2! V! W $ GS V th $ # &!! V DS $ # " nkt /q % I S # &e 1 e & $ 4 " kt /q % 4 " L % # &( 1+ λv DS ) 4 " % V GS V Tn Subthreshold 4 µ n C ox W 4 ( I D = 2 L 2( V V (V ) GS Tn SB DS DS )(1+ λ V DS ) 3 V GS > V Tn,V DS < V GS Linear 4 µ n C ox W 4 2 L V V (V ) GS Tn SB (1+ λ V DS ) 4 V GS > V Tn,V DS V GS V Tn Saturation 4, v sat C OX W ( V GS V th ) V / dsat E y > E cn (short channel) Velocity Saturation nmos 1st Order RC Delay Model Equiv. R n κ n C d Energy and Power Basics R n = R un /κ n κ n κ n C g ON/ OFF Where W n = κ n W un κ n 1, usually κ n = 1 κ n C d s κ p C d R p = R up /κ p Where W p = κ p W up κ p κ p C g ON/ OFF κ p 1, usually κ p µ n /µ p d κ p C d 39 Today Power! Power Sources " Static power " Dynamic switching power " Short circuit power! P = I V! Tricky part: " Understanding I " (pairing with correct V)
8 Operating Modes Understanding Currents! SteadyState: What modes are the transistors in? " V in =V dd Static Power " V in =Gnd! What current flows in steady state? Operating Modes Operating Modes! SteadyState: V in =V dd " PMOS: subthreshold! SteadyState: V in =V dd " PMOS: subthreshold " NMOS: resistive " NMOS: resistive $ I DSp = I S # W ' & ) e & % % L ( $ V GS V T nkt / q ' $ $ V DS '' ) & ) ( 1 e % kt / q ( & ) 1 λv DS % ( ( )! W $ ( I DSn = µ n C OX # & ( V GS V T )V DS V 2 + DS *  " L %) 2, Operating Modes Operating Modes! SteadyState: V in =V dd " PMOS: subthreshold! SteadyState: V in =V dd " PMOS: subthreshold " NMOS: resistive $ I DSp = I S # W ' & ) e & % % L ( $ V GS V T nkt / q ' $ $ V DS '' ) & ) ( 1 e % kt / q ( & ) 1 λv DS % ( ( ) " NMOS: resistive $ I DSp = I S # W ' & ) e & % % L ( $ V GS V T nkt / q ' $ $ V DS '' ) & ) ( 1 e % kt / q ( & ) 1 λv DS % ( ( )! W $ ( I DSn = µ n C OX # & ( V GS V T )V DS V 2 + DS *  " L %) 2,! W $ ( I DSn = µ n C OX # & ( V GS V T )V DS V 2 + DS *  " L %) 2, Which current determines I static? Which current determines I static?
9 Static Power! P = I V! What V should we use? Understanding Currents " Where is the static current flowing? Dynamic Switching Currents Power: During Switching Power: During Switching! P = IV! P = IV! Input switch: 1#0! Where does I go?! Input switch: 1#0! Where does I go? " V in =Gnd " V in =Gnd Power: During Switching Power: During Switching! P = IV! Input switch: 1#0! Where does I go? " V in =Gnd (Saturation/Linear)! P = IV! Input switch 0#1! Where does I go? " V in =V dd Subtheshold Leakage
10 Power: During Switching! P = IV! Input switch 0#1! Where does I go? " V in =V dd Power: During Switching! P = IV! Input switch 0#1! Where does I go? " V in =V dd Subtheshold Leakage (Saturation/Linear) Switching Currents! Dynamic current flow: Understanding Currents Short Circuit Currents Power: During Switching Power: During Switching! P = IV! Where does I go? " V in =V dd /2 " And V dd >V thn + V thp! P = IV! Where does I go? " V in =V dd /2 " And V dd >V thn + V thp Saturation CMOS Inverter DC Transfer Vout Vin Saturation
11 Switching Currents! Dynamic current flow: Currents Summary! I changes over time! At least two components " I static no switching " I switch when switching " and I sc! If both transistor on: " Current path from V dd to Gnd " Short circuit current Switching Currents Switching! I total (t) = I static (t)+i switch (t) Dynamic Power! I switch (t) = I sc (t) + (t) I static I sc 63 Penn ESE 570 Spring Khanna 64 Charging Switching Energy focus on (t)! (t) why changing? " I ds = f(v ds,v gs ) " and V gs, V ds changing % I DS ν sat C OX W V GS V T V ( DSAT ' * & 2 ) " W %) I DS = µ n C OX $ ' ( V # L & GS V T )V DS V 2, DS +. * 2  I sc I static
12 Switching Energy focus on (t) Switching Energy! Do we know what this is? (t)dt E = P(t)dt = I(t)V dd dt = V dd I(t)dt E = P(t)dt = I(t)V dd dt = V dd I(t)dt Switching Energy Switching Energy! Do we know what this is?! Do we know what this is? Q = (t)dt Q = (t)dt! What is Q? E = P(t)dt = I(t)V dd dt = V dd I(t)dt E = P(t)dt = I(t)V dd dt = V dd I(t)dt Switching Energy Switching Energy! Do we know what this is?! Do we know what this is? Q = (t)dt Q = (t)dt! What is Q? E = P(t)dt = I(t)V dd dt = V dd I(t)dt Q = CV = I(t)dt! What is Q? E = P(t)dt = I(t)V dd dt = V dd I(t)dt Q = CV = E = CV dd 2 I(t)dt Capacitor charging energy
13 Switching Power! Every time output switches 0#1 pay: " E = CV 2 Switching! P dyn = (# 0#1 trans) CV 2 / time Short Circuit Power! # 0#1 trans = ½ # of transitions! P dyn = (# trans) ½CV 2 / time Short Circuit Power Short Circuit Power! Between V TN and V dd  V TP " Both N and P devices conducting! Between V TN and V dd  V TP " Both N and P devices conducting! Roughly: I sc Vin VddVthp Vthn Vdd time Vdd Isc Penn ESE 570 Spring Khanna 75 Vout tsc tsc time 76 Peak Current Peak Current! I peak around V dd /2 " If V TN = V TP and sized equal rise/fall % I DS ν sat C OX W V GS V T V ( DSAT ' * & 2 )! I peak around V dd /2 " If V TN = V TP and sized equal rise/fall % I DS ν sat C OX W V GS V T V ( DSAT ' * & 2 ) I(t)dt I t % ' 1( peak sc & 2 * ) Vin VddVthp Vthn Vdd Vin VddVthp Vthn Vdd time time Vdd Isc Vdd Isc Vout tsc tsc time 77 Vout tsc tsc time 78 13
14 Peak Current! I peak around V dd /2 " If V TN = V TP and sized equal rise/fall % I DS ν sat C OX W V GS V T V ( DSAT ' * & 2 ) I(t)dt I t % ' 1( peak sc 2 * & ) # E = V dd I peak t sc % 1& ( Vin $ 2' Vdd VddVthp Vthn time Vdd Isc Short Circuit Energy! Make it look like a capacitance, C SC " Q=I t " Q=CV " " E = V dd I peak t sc 1 %% $ $ '' # # 2 && E = V dd Q SC E = V dd (C SC V dd ) = C SC V 2 dd Vout tsc tsc time 79 Penn ESE 570 Spring Khanna 80 Short Circuit Energy! Every time switch " Also dissipate shortcircuit energy: E = CV 2 " Different C = C sc " C cs fake capacitance (for accounting) Switching Power! Every time output switches 0#1 pay: " E = CV 2! P dyn = (# 0#1 trans) CV 2 / time! # 0#1 trans = ½ # of transitions! P dyn = (# trans) ½CV 2 / time Penn ESE 570 Spring Khanna Charging Power Switching Power! P dyn = (# trans) ½CV 2 / time! Often like to think about switching frequency! Useful to consider per clock cycle " Frequency f = 1/clockperiod! P dyn = (#trans/clock) ½CV 2 f! P dyn = (#trans/clock) ½CV 2 f! Let a = activity factor a = average #tran/clock! P dyn = a½cv 2 f! P sc = ac sc V 2 f
15 Switching Power! P dyn = (#0#1 trans/clock) CV 2 f! Let a = activity factor a = average #tran 0#1 /clock! P dyn = acv 2 f! P sc = ac sc V 2 f Activity Factor! Let a = activity factor " a = average #tran 0#1 /clock a = p(out i = 0)p(out i+1 =1) a = N 0 N 1 2 N 2 = N 0(2 N N 0 ) N 2 2 N Penn ESE 570 Spring Khanna 85 Penn ESE 570 Spring Khanna 86 Reduce Dynamic Power? Reduce Activity Factor! P dyn = acv 2 f Tree Chain! How do we reduce dynamic power? A B C D O 1 O 2 F A B C O 1 D O 2 F a = p(out i = 0)p(out i+1 =1) a = N 0 N 1 2 N 2 = N 0(2 N N 0 ) N 2 2 N Penn ESE 570 Spring Khanna 87 Penn ESE 570 Spring Khanna 88 Reduce Activity Factor Reduce Activity Factor Tree Chain Tree Chain A B C D O 1 O 2 F A B C 3/16 O 1 a = p(out i = 0)p(out i+1 =1) D 7/64 O 2 15/256 F A B C D 3/16 O 1 O 2 3/16 15/256 F A B C 3/16 O 1 a = p(out i = 0)p(out i+1 =1) D 7/64 O 2 15/256 F a = N 0 N 1 2 N 2 = N 0(2 N N 0 ) N 2 2 N a = N 0 N 1 2 N 2 = N 0(2 N N 0 ) N 2 2 N Penn ESE 570 Spring Khanna 89 Penn ESE 570 Spring Khanna 90 15
16 Total Power! P tot = P static + P sc + P dyn Energy and Power Optimization! P sw = P dyn + P sc = a(c load V 2 f) + C sc V 2 f! P tot a(c load V 2 f) + C sc V 2 f + VI s(w/l)e Vt/(nkT/q)! Let a = activity factor a = average #tran 0#1 /clock 91 Worksheet Problem 1 Power Sources Review: P tot = P static + P dyn + P sc V in I static amic I sc 0V 140mV 400mV 500mV 600mV 860mV 1V 94 Worksheet Problem 1 Idea! CMOS V in I static amic I sc " Design for worst case input switching case and delay 0V 180pA 126uA! There are other logic disciplines 140mV 6nA 100uA " Ratioed logic 400mV 36uA 18uA 500mV 36uA 600mV 36uA 18uA " Can use pass transistors for logic " Transmission gates " Will see in use in dynamic logic! Gate layout optimization 860mV 6nA 100uA " Euler Paths 1V 180pA 126uA! Power Basics Review
17 Admin! HW 6 " Out now " Due Tuesday 3/28 Penn ESE 570 Spring Khanna 97 17
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