MOS Transistor Properties Review


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1 MOS Transistor Properties Review 1
2 VLSI Chip Manufacturing Process Photolithography: transfer of mask patterns to the chip Diffusion or ion implantation: selective doping of Si substrate Oxidation: SiO 2 growth Deposition: Al and polysilicon thin films 2
3 NMOS Enhancement Device 3
4 Establishing a Channel v GS V t v DS =0 v GD =v GS v DS =v GS C ox = ox t ox F /cm 2 C gb =C ox WLF 4
5 Acts as a VoltageControlled Resistor v GD =v GS v DS v GS 5
6 NMOS Operation as v DS Increases 1. For small v DS : v GD =v GS v DS v GS 2. As v DS is increased for fixed v GS : v GD=v GS v DS > decreases 3. When v DS =v DSsat =v GS V t v GD =V t channel pinches off at drainend 4. As v DS is increased v DS v DSsat =v GS V t v GD V t channel L decreases. 6
7 Curve Flattens With Increased v DS 7
8 NMOS Enhancement Model Background If v GS V t,the drain to source current, i DS, increases until: v DS v GS V t The MOSFET saturates at this value of v DS and (except for an Early Effect ) i DS does not increase with further increases in v DS. This channel current is proportional to the channel width W, inversely proportional to its length L, and proportional to its transconductance parameter, k' n : ' k n = n C ox = cm2 V sec F cm2 C /V = 2 cm V sec cm = A 2 V 2 C ox is the capacitance per unit area of the gatechannel interface and n is the fabricationdependent channel electron mobility. 8
9 Uniform Channel Width (Small v DS ) Model Draintosource current with fixed gatetosource voltage is proportional to drain to source voltage: g DS =k n L v GS V t i D =i DS =g DS v DS =k n L v GS V t v DS r DS =1/ g DS = voltagecontrolled resistance k n Intuitively, conductance g DS is proportional to the conductor crosssection  channel width, W, times channel depth (set by the gate to source voltage, v GS V t ) and the conductivity of the channel material. Conductance is inversely proportional to L, the length of the current path. 1 L v GS V t 9
10 NMOS Enhancement Model Structure A satisfactory v DS  i DS model for the triode region is a quadratic expression that is linear for small v DS and reaches a maximum where the device saturates: Small v DS, where i D =i DS =k n L [ v GS V t v DS 1 2 v DS Saturation, where v DS =v GS V t : i D =i DS =k n 2 ] 1 2 v 2 v V v : DS i =i =k GS t DS D DS n L v GS V t v DS [ L v GS V t v GS V t 1 2] 2 v GS V t = k ' n 2 i D =i DS = k ' n 2 W L v GS V t 2 Triode region W L v GS V t 2 Saturation region 10
11 NMOS Enhancement Models For the NMOS enhancement mode (stronginversion) transistor: For: For: v GS V t 0 i DS =0 v GS V t 0 (Channel nonexistent) (Channel exists) v DS v GS V t 2 ] i D =i DS =k n L [ v GS V t v DS 1 2 v DS (Triode) v DS v GS V t i D =i DS = 1 2 k n L v V GS t 2 (Saturation) 11
12 Channel Length Modulation v DS v DSsat =v GS V t v GD V t L= Lv DS process parameter withunits V 1 Modify the saturation model to account for L: i D =i DS = 1 2 k n L v GS V t k n L L v GS V t 2 = 1 2 k n L L L 1 L 1 L/ L v GS V t 2 i D =i DS 1 2 k n L 1 L L v GS V t 2 = 1 2 k n L v GS V t 2 1 n v DS 12
13 V A Early Voltage Relation to Lambda Saturation: i D =i DS 1 2 k n L v GS V t 2 1 n v DS smallsignal outputresistance r o = V A I D = 1 I D where I D = 1 2 k n L V GS V t 2 slope=1/r o V A = 1 Triode: [ i D =i DS k n L v GS V t v DS 1 2 v ] 2 1 DS nv DS 13
14 NMOS Enhancement Circuit Symbols Sedra Symbols Multisim Symbols The body diode is indicated by the B terminal arrow. The substrate typically is connected to the most negative circuit voltage so the body diode is back biased. 14
15 NMOS Physical Representations 15
16 PMOS Enhancement Device PMOS Transistor on a ptype body (CMOS circuit). NOTE: ptype body is substrate for NMOS transistor nwell is local substrate for PMOS transistor 16
17 PMOS Enhancement Model PMOS device model is NMOS model with all polarities reversed: For: For: v SG V 0 t i D =i SD =0 v SG V 0 t v SD v SG V t (Channel nonexistent) (Channel exists) [ i D =i SD =k p L v SG V t v SD 1 2 v ] 2 1 SD p v SD v SD v SG V t i D =i SD = 1 2 k p L v SG V 2 t 1 p v SD (Triode) (Saturation) 17
18 PMOS Enhancement Circuit Symbols Sedra Symbols Multisim Symbols another PMOS symbol 18
19 nmos Small Signal Model Low Frequency (approximate) v gs g m v gs r o g m= 2 nc ox W L I D r o = 1 n I D C gd C gs C High Frequency (approximate) V gs C gs g m V gs r o C gd C 19
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