# Lecture 4: DC & Transient Response

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1 Introduction to CMOS VLSI Design Lecture 4: DC & Transient Response David Harris Harvey Mudd College Spring 004

2 Outline DC Response Logic Levels and Noise Margins Transient Response Delay Estimation Slide

3 Activity 1) If the width of a transistor increases, the current will increase decrease not change ) If the length of a transistor increases, the current will increase decrease not change 3) If the supply voltage of a chip increases, the maximum transistor current will increase decrease not change 4) If the width of a transistor increases, its gate capacitance will increase decrease not change 5) If the length of a transistor increases, its gate capacitance will increase decrease not change 6) If the supply voltage of a chip increases, the gate capacitance of each transistor will increase decrease not change Slide 3

4 Activity 1) If the width of a transistor increases, the current will increase decrease not change ) If the length of a transistor increases, the current will increase decrease not change 3) If the supply voltage of a chip increases, the maximum transistor current will increase decrease not change 4) If the width of a transistor increases, its gate capacitance will increase decrease not change 5) If the length of a transistor increases, its gate capacitance will increase decrease not change 6) If the supply voltage of a chip increases, the gate capacitance of each transistor will increase decrease not change Slide 4

5 DC Response DC Response: vs. V in for a gate Ex: Inverter When V in = 0 -> = When V in = -> = 0 In between, depends on transistor size and current By KCL, must settle such that I dsn = I dsp We could solve equations V in But graphical solution gives more insight I dsp I dsn Slide 5

6 Transistor Operation Current depends on region of transistor behavior For what V in and are nmos and pmos in Cutoff? Linear? Saturation? Slide 6

7 nmos Operation Cutoff V gsn < Linear V gsn > V dsn < Saturated V gsn > V dsn > V in I dsp I dsn Slide 7

8 nmos Operation Cutoff V gsn < V tn Linear V gsn > V tn Saturated V gsn > V tn V dsn < V gsn V tn V dsn > V gsn V tn V in I dsp I dsn Slide 8

9 nmos Operation Cutoff V gsn < V tn Linear V gsn > V tn Saturated V gsn > V tn V dsn < V gsn V tn V dsn > V gsn V tn V gsn = V in V dsn = V in I dsp I dsn Slide 9

10 nmos Operation Cutoff V gsn < V tn V in < V tn Linear V gsn > V tn V in > V tn V dsn < V gsn V tn < V in - V tn Saturated V gsn > V tn V in > V tn V dsn > V gsn V tn > V in - V tn V gsn = V in V dsn = V in I dsp I dsn Slide 10

11 pmos Operation Cutoff V gsp > Linear V gsp < V dsp > Saturated V gsp < V dsp < V in I dsp I dsn Slide 11

12 pmos Operation Cutoff V gsp > V tp Linear V gsp < V tp Saturated V gsp < V tp V dsp > V gsp V tp V dsp < V gsp V tp V in I dsp I dsn Slide 1

13 pmos Operation Cutoff V gsp > V tp Linear V gsp < V tp Saturated V gsp < V tp V dsp > V gsp V tp V dsp < V gsp V tp V gsp = V in - V dsp = - V tp < 0 V in I dsp I dsn Slide 13

14 pmos Operation Cutoff V gsp > V tp V in > + V tp Linear V gsp < V tp V in < + V tp V dsp > V gsp V tp > V in - V tp Saturated V gsp < V tp V in < + V tp V dsp < V gsp V tp < V in - V tp V gsp = V in - V dsp = - V tp < 0 V in I dsp I dsn Slide 14

15 I-V Characteristics Make pmos is wider than nmos such that β n = β p V gsn5 I dsn V gsn4 V gsn3 -V dsp V gsp1 V gsp - 0 V gsn V gsn1 V gsp3 V dsn V gsp4 -I dsp V gsp5 Slide 15

16 Current vs., V in V in0 V in5 I dsn, I dsp V in1 V in4 V in V in3 V in3 V in4 V in V in1 Slide 16

17 Load Line Analysis For a given V in : Plot I dsn, I dsp vs. must be where currents are equal in V in0 V in5 I dsn, I dsp V in1 V in4 V in V in3 I dsp V in3 V in4 V in V in1 V in I dsn Slide 17

18 Load Line Analysis V in = 0 V in0 I dsn, I dsp V in0 Slide 18

19 Load Line Analysis V in = 0. I dsn, I dsp V in1 V in1 Slide 19

20 Load Line Analysis V in = 0.4 I dsn, I dsp V in V in Slide 0

21 Load Line Analysis V in = 0.6 I dsn, I dsp V in3 V in3 Slide 1

22 Load Line Analysis V in = 0.8 I dsn, I dsp V in4 V in4 Slide

23 Load Line Analysis V in = V in0 V in5 I dsn, I dsp V in1 V in V in3 V in4 Slide 3

24 Load Line Summary V in0 V in5 I dsn, I dsp V in1 V in4 V in V in3 V in3 V in4 V in V in1 Slide 4

25 DC Transfer Curve Transcribe points onto V in vs. plot A B V in0 V in5 V in1 V in4 C V in V in3 V in3 V in4 V in V in1 0 D E V tn / +V tp V in Slide 5

26 Operating Regions Revisit transistor operating regions Region nmos pmos A B A B C C D E 0 D E V tn / +V tp V in Slide 6

27 Operating Regions Revisit transistor operating regions Region nmos pmos A B A Cutoff Linear B C Saturation Saturation Linear Saturation C D E Linear Linear Saturation Cutoff 0 D E V tn / +V tp V in Slide 7

28 Beta Ratio If β p / β n 1, switching point will move from / Called skewed gate Other gates: collapse into equivalent inverter β p 0.1 β = n β p 10 β = n V in Slide 8

29 Noise Margins How much noise can a gate input see before it does not recognize the input? Logical High Output Range Output Characteristics V OH NM H Input Characteristics Logical High Input Range V IH V IL Indeterminate Region Logical Low Output Range V OL NM L GND Logical Low Input Range Slide 9

30 Logic Levels To maximize noise margins, select logic levels at β p /β n > 1 V in 0 V in Slide 30

31 Logic Levels To maximize noise margins, select logic levels at unity gain point of DC transfer characteristic Unity Gain Points Slope = -1 V OH β p /β n > 1 V in V OL 0 V tn V IL V IH - V tp V in Slide 31

32 Transient Response DC analysis tells us if V in is constant Transient analysis tells us (t) if V in (t) changes Requires solving differential equations Input is usually considered to be a step or ramp From 0 to or vice versa Slide 3

33 Inverter Step Response Ex: find step response of inverter driving load cap V in ( t) V ( t < t ) = out dv out dt = ( t) 0 = V in (t) I dsn (t) (t) C load Slide 33

34 Inverter Step Response Ex: find step response of inverter driving load cap V V in out dv () t ( t< t ) out dt = () t ut ( t ) V 0 = = 0 DD V in (t) I dsn (t) (t) C load Slide 34

35 Inverter Step Response Ex: find step response of inverter driving load cap V V in out dv ( t) ( t ot u dt = ut ( t ) V < ( t) t 0 ) = 0 = V DD DD V in (t) I dsn (t) (t) C load Slide 35

36 Inverter Step Response Ex: find step response of inverter driving load cap V V in out dv () t = ut ( ( t< t ) out dt ( t) 0 = t ) V 0 = V I DD dsn C DD () t load V in (t) I dsn (t) (t) C load t t I t V V V < V V 0 dsn () = Vout > DD t out DD t Slide 36

37 Inverter Step Response I Ex: find step response of inverter driving load cap V V in out dv () t = ut ( ( t< t ) out dt ( t) 0 = t ) V 0 = V I DD dsn C 0 DD () t load ( ) β dsn ( t) = VDD V Vout > VDD Vt Vout ( t) β VDD V t V () t V < V D V out out D t t t 0 V in (t) I dsn (t) (t) C load Slide 37

38 Inverter Step Response I Ex: find step response of inverter driving load cap V V in out dv () t = ut ( ( t< t ) out dt ( t) 0 = t ) V 0 = V I DD dsn C 0 DD () t load ( ) β dsn ( t) = VDD V Vout > VDD Vt Vout ( t) β VDD V t V () t V < V D V out out D t t t 0 V in (t) t 0 I dsn (t) V in (t) (t) (t) C load t Slide 38

39 Delay Definitions t pdr : t pdf : t pd : t r : t f : fall time Slide 39

40 Delay Definitions t pdr : rising propagation delay From input to rising output crossing / t pdf : falling propagation delay From input to falling output crossing / t pd : average propagation delay t pd = (t pdr + t pdf )/ t r : rise time From output crossing 0. to 0.8 t f : fall time From output crossing 0.8 to 0. Slide 40

41 Delay Definitions t cdr : rising contamination delay From input to rising output crossing / t cdf : falling contamination delay From input to falling output crossing / t cd : average contamination delay t pd = (t cdr + t cdf )/ Slide 41

42 Simulated Inverter Delay Solving differential equations by hand is too hard SPICE simulator solves the equations numerically Uses more accurate I-V models too! But simulations take time to write (V) V in t pdf = 66ps t pdr = 83ps p 400p 600p 800p 1n t(s) Slide 4

43 Delay Estimation We would like to be able to easily estimate delay Not as accurate as simulation But easier to ask What if? The step response usually looks like a 1 st order RC response with a decaying exponential. Use RC delay models to estimate delay C = total capacitance on output node Use effective resistance R So that t pd = RC Characterize transistors by finding their effective R Depends on average current as gate switches Slide 43

44 RC Delay Models Use equivalent circuits for MOS transistors Ideal switch + capacitance and ON resistance Unit nmos has resistance R, capacitance C Unit pmos has resistance R, capacitance C Capacitance proportional to width Resistance inversely proportional to width g d k s g R/k kc d s kc kc Slide 44 g d k s g kc s d R/k kc kc

45 Example: 3-input NAND Sketch a 3-input NAND with transistor widths chosen to achieve effective rise and fall resistances equal to a unit inverter (R). Slide 45

46 Example: 3-input NAND Sketch a 3-input NAND with transistor widths chosen to achieve effective rise and fall resistances equal to a unit inverter (R). Slide 46

47 Example: 3-input NAND Sketch a 3-input NAND with transistor widths chosen to achieve effective rise and fall resistances equal to a unit inverter (R) Slide 47

48 3-input NAND Caps Annotate the 3-input NAND gate with gate and diffusion capacitance Slide 48

49 3-input NAND Caps Annotate the 3-input NAND gate with gate and diffusion capacitance. C C C C C C C C C 3C 3C 3C C 3C 3C 3C Slide 49

50 3-input NAND Caps Annotate the 3-input NAND gate with gate and diffusion capacitance. 5C 5C 5C C 3C 3C Slide 50

51 Elmore Delay ON transistors look like resistors Pullup or pulldown network modeled as RC ladder Elmore delay of RC ladder t R C pd i to source i nodes i = RC + R + R C R + R R C ( ) ( ) R 1 R R 3 R N N N C 1 C C 3 C N Slide 51

52 Example: -input NAND Estimate worst-case rising and falling delay of - input NAND driving h identical gates. A B x Y h copies Slide 5

53 Example: -input NAND Estimate rising and falling propagation delays of a - input NAND driving h identical gates. A B x 6C C Y 4hC h copies Slide 53

54 Example: -input NAND Estimate rising and falling propagation delays of a - input NAND driving h identical gates. A B x 6C C Y 4hC h copies R Y (6+4h)C t pdr = Slide 54

55 Example: -input NAND Estimate rising and falling propagation delays of a - input NAND driving h identical gates. A B x 6C C Y 4hC h copies R Y ( ) (6+4h)C t pdr = 6+ 4h RC Slide 55

56 Example: -input NAND Estimate rising and falling propagation delays of a - input NAND driving h identical gates. A B x 6C C Y 4hC h copies Slide 56

57 Example: -input NAND Estimate rising and falling propagation delays of a - input NAND driving h identical gates. A B x 6C C Y 4hC h copies R/ x R/ C Y (6+4h)C t pdf = Slide 57

58 Example: -input NAND Estimate rising and falling propagation delays of a - input NAND driving h identical gates. A B x 6C C Y 4hC h copies R/ x R/ C Y (6+4h)C tpdf = C + + h C + = 7+ 4h RC ( )( R ) ( 6 4 ) ( R R ) ( ) Slide 58

59 Delay Components Delay has two parts Parasitic delay 6 or 7 RC Independent of load Effort delay 4h RC Proportional to load capacitance Slide 59

60 Contamination Delay Best-case (contamination) delay can be substantially less than propagation delay. Ex: If both inputs fall simultaneously A B x 6C C Y 4hC R R Y (6+4h)C tcdr = 3+ h RC ( ) Slide 60

61 Diffusion Capacitance we assumed contacted diffusion on every s / d. Good layout minimizes diffusion area Ex: NAND3 layout shares one diffusion contact Reduces output capacitance by C Merged uncontacted diffusion might help too Shared Contacted Diffusion Merged Uncontacted Diffusion C C Isolated Contacted Diffusion 3 3 7C 3C 3C 3C 3C 3 3C Slide 61

62 Layout Comparison Which layout is better? A B A B Y Y GND GND Slide 6

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