VLSI Design Issues. ECE 410, Prof. F. Salem/Prof. A. Mason notes update

Transcription

1 VLSI Design Issues Scaling/Moore s Law has limits due to the hysics of material. Now L (L=20nm??) affects tx delays (seed), noise, heat (ower consumtion) Scaling increases density of txs and requires more interconnect (highways & buses)-more delays (lowering seed) and heat. Possible Solutions: New fabrication solutions/material. E.g., Interconnect layers, new material (coer & low k-material) Imrove hysical Designs at the transistor level. Create better cell libraries (min Power, min-delay, max seed) Exloit transister analog/hysics characteristics Invent new transistors Invent new architectures Lecture Notes 7.1

2 CMOS Inverter: DC Analysis Analyze DC Characteristics of CMOS Gates by studying an Inverter DC Analysis DC value of a signal in static conditions DC Analysis of CMOS Inverter Vin, inut voltage Vout, outut voltage single ower suly, VDD Ground reference find Vout = f(vin) Voltage Transfer Characteristic (VTC) lot of Vout as a function of Vin vary Vin from 0 to VDD (and in reverse!) find Vout at each value of Vin Lecture Notes 7.2

3 Inverter Voltage Transfer Characteristics Outut High Voltage, V OH maximum outut voltage occurs when inut is low (Vin = 0V) MOS is ON, nmos is OFF MOS ulls Vout to VDD V OH = VDD Outut Low Voltage, V OL minimum outut voltage occurs when inut is high (Vin = VDD) MOS is OFF, nmos is ON nmos ulls Vout to Ground V OL = 0 V Logic Swing Max swing of outut signal V L = V OH - V OL V L = VDD Lecture Notes 7.3

4 Inverter Voltage Transfer Characteristics Gate Voltage, f(vin) V GSn =Vin, V SG =VDD-Vin Transition Region (between V OH and V OL ) Vin low Vin < Vtn Mn in Cutoff, OFF M in Triode, Vout ulled to VDD Vin > Vtn < ~Vout Mn in Saturation, strong current M in Triode, V SG & current reducing Vout decreases via current through Mn Vin = Vout (mid oint) ½ VDD Mn and M both in Saturation maximum current at Vin = Vout Vin high Vin > ~Vout, Vin < VDD - Vt Mn in Triode, M in Saturation Vin > VDD - Vt Mn in Triode, M in Cutoff Drain Voltage, f(vout) V DSn =Vout, V SD =VDD-Vout + V SG - + V GSn - Vin < V IL inut logic LOW Vin > V IH inut logic HIGH Lecture Notes 7.4

5 Noise Margin Inut Low Voltage, V IL Vin such that Vin < V IL = logic 0 oint a on the lot where sloe, Vin Vout Inut High Voltage, V IH Vin such that Vin > V IH = logic 1 oint b on the lot where sloe =-1 Voltage Noise Margins measure of how stable inuts are with resect to signal interference VNM H = V OH - V IH = VDD - V IH = VNM L = V IL - V OL = V IL desire large VNM H and VNM L for best noise immunity 1 Lecture Notes 7.5

6 Switching Threshold Switching threshold = oint on VTC where Vout = Vin also called midoint voltage, V M here, Vin = Vout = V M Calculating V M at V M, both nmos and MOS in Saturation in an inverter, I Dn = I D, always! solve equation for V M µ C 2 W L 2 n OX 2 n 2 2 I Dn = ( VGSn Vtn) = ( VGSn Vtn) = ( VSG Vt ) = 2 I D n 2 exress in terms of V M ( V M V tn ) 2 = 2 ( V DD V M V t ) 2 n ( V M V ) = V tn DD V M V t solve for V M V M VDD V = 1+ t + V n tn n Lecture Notes 7.6

7 Recall Effect of Transistor Size on VTC If nmos and MOS are same size If n = k' n W L n (W/L)n = (W/L) Coxn = Cox (always) W L W L µ =, then = 1 µ n n n W k' n L = W k' L n n µ nc = µ C W L W L Effect on switching threshold if n and Vtn = Vt, V M = VDD/2, exactly in the middle oxn ox n = µ n 2or3 µ V M = VDD V 1+ since L normally min. size for all tx, can get betas equal by making W larger than Wn t + V n tn n Effect on noise margin if n, V IH and V IL both close to V M and noise margin is good Lecture Notes 7.7

8 Given Examle k n = 140uA/V 2, Vtn = 0.7V, VDD = 3V k = 60uA/V 2, Vt = -0.7V Find a) tx size ratio so that V M = 1.5V b) V M if tx are same size transition ushed lower as beta ratio increases Lecture Notes 7.8

9 CMOS Inverter: Transient Analysis Analyze Transient Characteristics of CMOS Gates by studying an Inverter Transient Analysis signal value as a function of time Transient Analysis of CMOS Inverter Vin(t), inut voltage, function of time Vout(t), outut voltage, function of time VDD and Ground, DC (not function of time) find Vout(t) = f(vin(t)) Transient Parameters outut signal rise and fall time roagation delay Lecture Notes 7.9

10 Transient Resonse Recall: the RC nmos Transistor Model Lecture Notes 7.10

11 Transient Resonse Resonse to ste change in inut delays in outut due to arasitic R & C Inverter RC Model Resistances (linear model) Rn = 1/[ n (V DD -Vtn)] R = 1/[ (V DD - Vt )] Outut Ca. (only outut is imortant) C Dn (nmos drain caacitance) C Dn = ½ Cox W n L + C j A Dnbot + C jsw P Dnsw C D (MOS drain caacitance) C L + Vout - C D = ½ Cox W L + C j A Dbot + C jsw P Dsw Load caacitance, due to gates attached at the outut C L = 3 Cin = 3 (C Gn + C G ), 3 is a tyical load Total Outut Caacitance Cout = C Dn + C D + C L term fan-out describes # gates attached at outut Lecture Notes 7.11

12 Fall Time Fall Time, t f time for outut to fall from 1 to 0 derivation: Vout Vout i = Cout = t Rn initial condition, Vout(0) = VDD solution Vout VDD t= τ n ln Vout definition t f is time to fall from 90% value [V 1,t x ] to 10% value [V 0,t y ] t f = 2.2 τ n t time constant τn ( t) = V DD e τ n = R n C out V t= τn ln 0.1V DD DD V ln 0.9V DD DD Lecture Notes 7.12

13 Rise Time Rise Time, t r time for outut to rise from 0 to 1 derivation: initial condition, Vout(0) = 0V t f is time to rise from 10% value [V 0,t u ] to 90% value [V 1,t v ] t r = 2.2 τ i= C Maximum Signal Frequency f max = 1/(t r + t f ) out solution Vout( t) V DD 1 e definition = V t t τ out V = time constant τ = R C out faster than this and the outut can t settle DD V R out Lecture Notes 7.13

14 Proagation Delay Proagation Delay, t measures seed of outut reaction to inut change t = ½ (t f + t r ) Fall roagation delay, t f time for outut to fall by 50% reference to inut switch Rise roagation delay, t r time for outut to rise by 50% reference to inut switch Ideal exression (if inut is ste change) t f = ln(2) τ n t r = ln(2) τ Total Proagation Delay t = 0.35(τ n + τ ) Proagation delay measurement: - from time inut reaches 50% value - to time outut reaches 50% value Add rise and fall roagation delays for total value Lecture Notes 7.14

15 Switching Seed -Resistance Rise & Fall Time t f = 2.2 τ n, t r = 2.2 τ, Proagation Delay t = 0.35(τ n + τ ) In General delay τ n + τ τ n + τ = Cout (Rn+R) Define delay in terms of design arameters Rn+R = (V DD -Vt)( n + ) n (V DD -Vt) 2 τ n = R n C out Rn = 1/[ n (V DD -Vtn)] τ = R C out R = 1/[ (V DD - Vt )] Cout = C Dn + C D + C L Beta Matched if n = =, = µcox (W/L) Rn+R = 2 = 2 L (V DD -Vt) µcox W (V DD -Vt) Width Matched if W n =W =W, and L=L n =L Rn+R = n + n (V DD -Vt) if Vt = Vtn = Vt Rn+R = L (µ n + µ ) (µ n µ ) Cox W (V DD -Vt) To decrease R s, L, W, VDD, ( µ, Cox ) Lecture Notes 7.15

16 Switching Seed -Caacitance From Resistance we have L, W, VDD, ( µ, Cox ) but VDD increases ower W increases Cout Cout Cout = ½ Cox L (W n +W ) + C j 2L (W n +W ) + 3 Cox L (W n +W ) assuming junction area ~W 2L neglecting sidewall caacitance Cout L (W n +W ) [3½ Cox +2 C j ] Cout L (W n +W ) To decrease Cout, L, W, ( Cj, Cox ) Delay Cout(Rn+R) L W L Cout = C Dn + C D + C L L W VDD if L=L n =L estimate C L = 3 (C Gn + C G ) = 3 Cox (W n L+W L) C Dn = ½ Cox W n L + C j A Dnbot + C jsw P Dnsw C D = ½ Cox W L + C j A Dbot + C jsw P Dsw ~2L W = L 2 VDD Decreasing L (reducing feature size) is best way to imrove seed! Lecture Notes 7.16

17 Switching Seed -Local Modification Previous analysis alies to the overall design shows that reducing feature size is critical for higher seed general result useful for creating cell libraries How do you imrove seed within a secific gate? increasing W in one gate will not increase C G of the load gates Cout = C Dn + C D + C L increasing W in one logic gate will increase C Dn/ but not C L C L deends on the size of the tx gates at the outut as long as they kee minimum W, C L will be constant thus, increasing W is a good way to imrove the seed within a local oint But, increasing W increases chi area needed, which is bad fast circuits need more chi area (chi real estate ) Increasing VDD is not a good choice because it increases ower consumtion Lecture Notes 7.17

18 CMOS Power Consumtion P = P DC + P dyn P DC : DC (static) term P dyn : dynamic (signal changing) term P DC P = I DD V DD I DD DC current from ower suly ideally, I DD = 0 in CMOS: ideally only current during switching action leakage currents cause I DD > 0, define quiescent leakage current, I DDQ (due largely to leakage at substrate junctions) P DC = I DDQ V DD Pdyn, ower required to switch the state of a gate charge transferred during transition, Qe = Cout VDD assume each gate must transfer this charge 1x/clock cycle Paverage = V DD Qe f = Cout V DD2 f, f = frequency of signal change Power increases with Cout and frequency, and strongly with VDD (second order). Total Power, P = I DDQ V DD + Cout V DD2 f Lecture Notes 7.18

19 Multi-Inut Gate Signal Transitions In multi-inut gates multile signal transitions roduce outut changes What signal transitions need to be analyzed? for a general N-inut gate with M 0 low outut states and M 1 high outut states # high-to-low outut transitions = M 0 M 1 # low-to-high outut transitions = M 1 M 0 total transitions to be characterized = 2 M 0 M 1 examle: NAND has M 0 = 1, M 1 = 3 don t test/characterize cases without outut transitions Worst-case delay is the slowest of all ossible cases worst-case high-to-low worst-case low-to-high often different inut transitions for each of these cases Lecture Notes 7.19

20 Series/Parallel Equivalent Circuits Scale both W and L no effective change in W/L increases gate caacitance inuts must be at same value/voltage Series Transistors increases effective L = µcox (W/L) effective ½ Parallel Transistors increases effective W effective 2 Lecture Notes 7.20

21 NAND: DC Analysis Multile Inuts Multile Transitions Multile VTCs VTC varies with transition transition from 0,0 to 1,1 ushed right of others why? V M varies with transition assume all tx have same L V M = V A = V B = Vout can merge transistors at this oint if W A =W B and W na =W nb series nmos, n ½n arallel MOS, 2 can now calculate the NAND V M Lecture Notes 7.21

22 Calculate VM for NAND 0,0 to 1,1 transition NAND Switching Point all tx change states (on, off) in other transitions, only 2 change V M = V A = V B = Vout set I Dn = I D, solve for V M V M = VDD V 1+ t V denominator reduced more VTC shifts right to balance this effect and set V M to V DD /2, can increase by 1 n VDD Vt + V increasing Wn tn N VM = but, since µ n >µ, V M V DD /2 1 n 1+ when Wn = W For NAND with N inuts N tn n 1 2 n series nmos means more resistance to outut falling, shifts VTC to right Lecture Notes 7.22

23 Similar Analysis to NAND Critical Transition 0,0 to 1,1 when all transistors change V M for NOR2 critical transition if W A =W B and W na =W nb arallel nmos, n 2n series MOS, ½ V M = VDD V t V n for NOR2 tn n NOR: DC Analysis series MOS resistance means slower rise VTC shifted to the left to set V M to V DD /2, increase W this will increase V M = VDD V t 1+ N + NV n tn for NOR-N n Lecture Notes 7.23

24 NAND RC Circuit NAND: Transient Analysis R: standard channel resistance C: Cout = C L + C Dn + 2C D Rise Time, t r Worst case charge circuit 1 MOS ON t r = 2.2 τ τ = R Cout best case charge circuit 2 MOS ON, R R/2 Fall Time, t f Discharge Circuit 2 series nmos, Rn 2Rn must account for internal ca, Cx t f = 2.2 τ n τ n = Cout (2 R n ) + Cx R n Cx = C Sn + C Dn Lecture Notes 7.24

25 NAND RC Circuit NOR: Transient Analysis R: standard channel resistance C: Cout = C L + 2C Dn + C D Fall Time, t f Worst case discharge circuit 1 nmos ON t f = 2.2 τ n τ n = R n Cout best case discharge circuit 2 nmos ON, Rn Rn/2 Rise Time, t r Charge Circuit 2 series MOS, R 2R must account for internal ca, Cy Cy = C S + C D t r = 2.2 τ τ = Cout (2 R ) + Cy R Lecture Notes 7.25

26 NAND/NOR Performance Inverter: symmetry (V M =V DD /2), n = (W/L) = µ n /µ (W/L) n Match INV erformance with NAND MOS, P =, same as inverter nmos, N = 2n, to balance for 2 series nmos Match INV erformance with NOR is adjusted by changing transistor size (width) MOS, P = 2, to balance for 2 series MOS nmos, N = n, same as inverter NAND and NOR will still be slower due to larger Cout This can be extended to 3, 4, N inut NAND/NOR gates Lecture Notes 7.26

27 NAND/NOR Transient Summary Critical Delay Path aths through series transistors will be slower more series transistors means worse delays Tx Sizing Considerations increase W in series transistors balance n / for each cell Worst Case Transition when all series transistor go from OFF to ON and all internal cas have to be charged (NOR) discharged (NAND) Lecture Notes 7.27

28 Performance Considerations Seed based on n, and arasitic cas DC erformance (V M, noise) based on n/ Design for seed not necessarily rovide good DC erformance Generally set tx size to otimize seed and then test DC characteristics to ensure adequate noise immunity Review Inverter: Our erformance reference oint for symmetry (V M =V DD /2), n = which requires (W/L) = µ n /µ (W/L) n Use inverter as reference oint for more comlex gates Aly slowest arriving inuts to series node closest to outut let faster signals begin to charge/discharge nodes closer to VDD and Ground slower signal faster signal outut ower suly Lecture Notes 7.28

29 Timing in Comlex Logic Gates Critical delay ath is due to series-connected transistors Examle: f = x (y+z) assume all tx are same size Fall time critical delay worst case, x ON, and y or z ON t f = 2.2 τ n τ n = Rn Cn + 2 Rn C out C out = 2C D + C Dn + C L Cn = 2C Dn + C Sn Rise time critical delay worst case, y and z ON, x OFF t r = 2.2 τ τ = R C + 2 R C out C out = 2C D + C Dn + C L C = C D + C S size vs. tx seed considerations Wnx Rn but Cout and Cn Wny Cn but Rn Wz R but Cout and C Wx no effect on critical ath! Lecture Notes 7.29

30 Sizing in Comlex Logic Gates Imroving seed within a single logic gate An Examle: f=(a b+c d) x nmos discharge through 3 series nmos set N = 3n MOS charge through 2 series MOS set P = 2 but, Mx is alone so P1 = but setting P1 = 2 might make layout easier These large transistors will increase caacitance and layout area and may only give a small increase in seed Advanced logic structures are best way to imrove seed Lecture Notes 7.30

31 Timing in Multi-Gate Circuits What is the worst-case delay in multi-gate circuits? A B C D F A B C D F C C D too many transitions to test manually Critical Path longest delay through a circuit block largest sum of delays, from inut to outut intuitive analysis: signal that asses through most gates not always true. can be slower ath through fewer gates B A B C D F ath through most gates critical ath if delay at D inut is very slow Lecture Notes 7.31

32 Power in Multi-Inut Logic Gates Inverter Power Consumtion P = P DC + P dyn = V DD I DDQ + C out V 2 DDf assumes gates switch outut state once er clock cycle, f Multi-Inut Gates same DC comonent as inverter, P DC = V DD I DDQ for dynamic ower, need to estimate activity of the gate, how often will the outut be switching P dyn = ac out V 2 DDf, a = activity coefficient estimate activity from truth table NOR NAND a = = rob. outut is at 0 1 = rob. of transition to 1 0=0.75 1=0.25 a=3/16 0=0.25 1=0.75 a=3/16 Lecture Notes 7.32

33 Timing Analysis of Transmission Gates TG = arallel nmos and MOS RC Model in general, only one tx active at same time nmos ulls outut low MOS ushes outut high R TG = max (Rn, R) Cin = C Sn + C D if outut at higher voltage than inut larger W will decrease R but increase Cin Note: no connections to VDD-Ground. Inut signal, Vin, must drive TG outut; TG just adds extra delay Lecture Notes 7.33

34 Pass Transistor Single nmos or MOS tx Often used in lace of TGs less area and wiring can t ull to both VDD and Ground tyically use nmos for better seed Φ=1 Rise and Fall Times τ n = Rn C out y I D time x=0 y=1 0 t f = 2.94 τ n t r = 18 τ n much slower than fall time y I D time x=1 Φ=1 y=0 1 nmos can t ull outut to VDD rise time suffers from threshold loss in nmos Lecture Notes 7.34