Lecture 8: Logic Effort and Combinational Circuit Design


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1 Lecture 8: Logic Effort and Combinational Circuit Design Slides courtesy of Deming Chen Slides based on the initial set from David Harris CMOS VLSI Design
2 Outline q Logical Effort q Delay in a Logic Gate q Multistage Logic Networks q ubble Pushing q Compound Gates q Logical Effort Example q More advanced topics q Readings: ; 4.5.; CMOS VLSI Design
3 Delay in a Logic Gate q q q q q q Express delays in processindependent unit d = Delay has two components: d = f + p τ = 3RC f: effort delay = gh (a.k.a. stage effort) gain has two components g: logical effort Measures relative ability of gate to deliver current g for inverter h: electrical effort = C out / C in Ratio of output to input capacitance Sometimes called fanout p: parasitic delay Represents delay of gate driving no load Set by internal parasitic capacitance d abs τ 3 ps in 65 nm process 60 ps in 0.6 µm process Logical Effort CMOS VLSI Design 3
4 Computing Logical Effort q DEF: Logical effort is the ratio of the input capacitance of a gate to the input capacitance of an inverter delivering the same output current. q Measure from delay vs. fanout plots q Or estimate by counting transistor widths 4 4 C in = 3 g = 3/3 C in = 4 g = 4/3 C in = 5 g = 5/3 Logical Effort CMOS VLSI Design 4
5 Delay Plots q d = f + p = gh + p What about NOR? Normalized Delay: d input NND Inverter g = 4/3 p = d = (4/3)h + g = p = d = h + Effort Delay: f 0 Parasitic Delay: p Electrical Effort: h = C out / C in Logical Effort CMOS VLSI Design 5
6 Catalog of Gates q Logical effort of common gates Gate type Number of inputs 3 4 n Inverter NND 4/3 5/3 6/3 (n+)/3 NOR 5/3 7/3 9/3 (n+)/3 Tristate / mux XOR, XNOR 4, 4 6,, 6 8, 6, 6, 8 Logical Effort CMOS VLSI Design 6
7 Catalog of Gates q Parasitic delay of common gates In multiples of p inv ( ) Gate type Inverter Number of inputs 3 4 n NND 3 4 n NOR 3 4 n Tristate / mux n XOR, XNOR Logical Effort CMOS VLSI Design 7
8 Example: Ring Oscillator q Estimate the frequency of an Nstage ring oscillator Logical Effort: g = Electrical Effort: h = Parasitic Delay: p = Stage Delay: d = Frequency: f osc = /(*N*d) = /4N 3 stage ring oscillator in 0.6 µm process has frequency of ~ 00 MHz Logical Effort CMOS VLSI Design 8
9 Example: FO4 Inverter q Estimate the delay of a fanoutof4 (FO4) inverter d Logical Effort: g = Electrical Effort: h = 4 Parasitic Delay: p = Stage Delay: d = 5 The FO4 delay is about 300 ps in 0.6 µm process 5 ps in a 65 nm process Logical Effort CMOS VLSI Design 9
10 Multistage Logic Networks q Logical effort generalizes to multistage networks q Path Logical Effort q Path Electrical Effort q Path Effort G= g i H = C C outpath inpath F = f = gh i i i 0 g = h = x/0 x g = 5/3 h = y/x y g 3 = 4/3 h 3 = z/y z g 4 = h 4 = 0/z 0 Logical Effort CMOS VLSI Design 0
11 Multistage Logic Networks q Logical effort generalizes to multistage networks q Path Logical Effort q Path Electrical Effort q Path Effort q Can we write F = GH? G= g i H = C out path C in path F = f = gh i i i Logical Effort CMOS VLSI Design
12 Paths that ranch q No! Consider paths that branch: G = H = 90 / 5 = GH = 8 h = (5 +5) / 5 = 6 h = 90 / 5 = F = g g h h = 36 = GH Logical Effort CMOS VLSI Design
13 ranching Effort q Introduce branching effort ccounts for branching between stages in path b = C on path = b i C C on path off path q Now we compute the path effort F = GH + Note: h i = H Logical Effort CMOS VLSI Design 3
14 Multistage Delays q Path Effort Delay D F = f i q Path Parasitic Delay q Path Delay P= p i = i = F + D d D P Logical Effort CMOS VLSI Design 4
15 Designing Fast Circuits = i = F + D d D P q Delay is smallest when each stage bears same effort fˆ = gh = F i i N q Thus minimum delay of N stage path is N D = NF + P q This is a key result of logical effort Find fastest possible delay Doesn t require calculating gate sizes Logical Effort CMOS VLSI Design 5
16 Gate Sizes q How wide should the gates be for least delay? fˆ = gh = g C = in i C C out in gc i fˆ out i q Working backward, apply capacitance transformation to find input capacitance of each gate given load it drives. q Check work by verifying input cap spec is met. Logical Effort CMOS VLSI Design 6
17 Example: 3stage path q Select gate sizes x and y for least delay from to x x y 45 8 x y 45 Logical Effort CMOS VLSI Design 7
18 0 5 x y 0 8
19 Example: 3stage path x y x 45 8 x y 45 Logical Effort G = (4/3)*(5/3)*(5/3) = 00/7 Electrical Effort H = 45/8 ranching Effort = 3 * = 6 Path Effort F = GH = 5 ˆ 3 = F = 5 est Stage Effort Parasitic Delay P = = 7 f Delay D = 3*5 + 7 = = 4.4 FO4 Logical Effort CMOS VLSI Design 9
20 Example: 3stage path q Work backward for sizes y = 45 * (5/3) / 5 = 5 x = (5*) * (5/3) / 5 = 0 x P: 8 4 N: 4 x P: x 4 N: 6 y P: y N: Logical Effort CMOS VLSI Design 0
21 Combinational Design  Example module mux(input s, d0, d, output y); assign y = s? d : d0; endmodule ) Sketch a design using ND, OR, and NOT gates. D0 S D S
22 Example ) Sketch a design using NND, NOR, and NOT gates. ssume ~S is available. D0 S D S
23 ubble Pushing q Start with network of ND / OR gates q Convert to NND / NOR + inverters q Push bubbles around to simplify logic Remember DeMorgan s Law (a) (b) (c) D (d) 3
24 Example 3 3) Sketch a design using one compound gate and one NOT gate. ssume ~S is available. D0 S D S 4
25 Compound Gates q Logical Effort of compound gates unit inverter OI OI = = i+ C = + C D C C D D E C Complex OI i i i( ) = + C + DiE C C 4 C 4 D 4 C D C D E E 6 D C g = 3/3 g = 6/3 g = 6/3 g = 5/3 p = 3/3 g = 6/3 g = 6/3 g = 8/3 g C = 5/3 g C = 6/3 g C = 8/3 p = 7/3 g D = 6/3 g D = 8/3 p = /3 g E = 8/3 p = 6/3 5
26 Example 4 q The multiplexer has a maximum input capacitance of 6 units on each input. It must drive a load of 60 units. Estimate the delay of the two designs. H = 60 / 6 = 0 = N = D0 S D S P = + = 4 G = (4 / 3) g(4 / 3) = 6 / 9 F = GH = 60 / 9 ˆ N f = F = 4. D = Nfˆ + P =.4τ D0 S D S P = 4+ = 5 G = (6/3) g() = F = GH = 0 ˆ N f = F = 4.5 D = Nfˆ + P = 4τ 6
27 Example 5 q nnotate your designs with transistor sizes that achieve this delay * (4/3) / 4. = * / 4.5 =
28 Input Order q Our parasitic delay model was too simple Calculate parasitic delay for falling If arrives latest? τ If arrives latest?.33τ x 6C C 8
29 Inner & Outer Inputs q Inner input is closest to output () q Outer input is closest to rail () q If input arrival time is known Connect latest input to inner terminal 9
30 symmetric Gates q symmetric gates favor one input over another q Ex: suppose input of a NND gate is most critical Use smaller transistor on (less capacitance) oost size of noncritical input So total resistance is same q g = 0/9 q g = reset q g total = g + g = 8/9 q symmetric gate approaches g = on critical input q ut total logical effort goes up reset 4/3 4 30
31 Symmetric Gates q Inputs can be made perfectly symmetric 3
32 Skewed Gates q Skewed gates favor one edge over another q Ex: suppose rising output of inverter is most critical Downsize noncritical nmos transistor HIskew inverter unskewed inverter (equal rise resistance) unskewed inverter (equal fall resistance) / / q Calculate logical effort by comparing to unskewed inverter with same effective resistance on that edge. g u =.5 / 3 = 5/6 g d =.5 /.5 = 5/3 3
33 HI and LOSkew q Def: Logical effort of a skewed gate for a particular transition is the ratio of the input capacitance of that gate to the input capacitance of an unskewed inverter delivering the same output current for the same transition. q Skewed gates reduce size of noncritical transistors HIskew gates favor rising output (small nmos) LOskew gates favor falling output (small pmos) q Logical effort is smaller for favored direction q ut larger for the other direction 33
34 Catalog of Skewed Gates Inverter NND NOR unskewed g u = g d = g avg avg = g u = 4/3 g d = 4/3 g avg avg = 4/3 4 4 g u = 5/3 g d = 5/3 g avg avg = 5/3 HIskew / g u = 5/6 g d = 5/3 g avg avg = 5/4 g u = g d = g avg avg = 3/ / 4 4 / g u = 3/ g d = 3 g avg avg = 9/4 LOskew g u = 4/3 g d = /3 g avg avg = g u = g d = g avg avg = 3/ g u = g d = g avg avg = 3/ 34
35 symmetric Skew q Combine asymmetric and skewed gates Downsize noncritical transistor on unimportant input Reduces parasitic delay for critical input reset reset 4/3 4 35
36 est P/N Ratio q We have selected P/N ratio for unit rise and fall resistance (µ = 3 for an inverter). q lternative: choose ratio for least average delay q Ex: inverter Delay driving identical inverter t pdf = (P+) t pdr = (P+)(µ/P) t pd = (P+)(+µ/P)/ = (P + + µ + µ/p)/ dt pd / dp = ( µ/p )/ = 0 Least delay for P = µ P 36
37 P/N Ratios q In general, best P/N ratio is sqrt of equal delay ratio. Only improves average delay slightly for inverters ut significantly decreases area and power Inverter NND NOR fastest.44 P/N ratio g u =.5 g d = 0.8 g avg = 0.98 g u = 4/3 g d = 4/3 g avg = 4/3 g u = g d = g avg = 3/ 37
38 Observations q For speed: NND vs. NOR Many simple stages vs. fewer high fanin stages Latestarriving input q For area and power: Many simple stages vs. fewer high fanin stages 38
39 Summary q Logic effort is an effective way for handson delay estimations for simple gates and paths In reality, people use timing analysis and logic synthesis for delay estimation and optimization q Combinational circuit design is the foundation for modern computer design Lead to sequential design in the next lecture q Next lecture Sequential circuit design Readings:
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