Lecture 8: Combinational Circuits


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1 Introduction to CMOS VLSI Design Lecture 8: Combinational Circuits David Harris Harvey Mudd College Spring 00
2 Outline ubble Pushing Compound Gates Logical Effort Example Input Ordering symmetric Gates Skewed Gates est P/N ratio Slide
3 Example module mux(input s, d0, d, output y); assign y s? d : d0; endmodule ) Sketch a design using ND, OR, and NOT gates. Slide 3 3
4 Example module mux(input s, d0, d, output y); assign y s? d : d0; endmodule ) Sketch a design using ND, OR, and NOT gates. D0 S D S Slide
5 Example ) Sketch a design using NND, NOR, and NOT gates. ssume ~S is available. Slide 5 5
6 Example ) Sketch a design using NND, NOR, and NOT gates. ssume ~S is available. D0 S D S Slide 6 6
7 ubble Pushing Start with network of ND / OR gates Convert to NND / NOR + inverters Push bubbles around to simplify logic Remember DeMorgan s Law (a) (b) (c) D (d) Slide 7 7
8 Example 3 3) Sketch a design using one compound gate and one NOT gate. ssume ~S is available. Slide 8 8
9 Example 3 3) Sketch a design using one compound gate and one NOT gate. ssume ~S is available. D0 S D S Slide 9 9
10 Compound Gates Logical Effort of compound gates unit inverter OI OI + C C D C C D D E C Complex OI + ( ) + C + D E 6 C C C D C D C D E E 6 D C g 3/3 g 6/3 g g p 3/3 g 6/3 g g g C 5/3 g C g C p 7/3 g D g D p g E p Slide 0 0
11 Compound Gates Logical Effort of compound gates unit inverter OI OI + C C D C C D D E C Complex OI + ( ) + C + D E 6 C C C D C D C D E E 6 D C g 3/3 g 6/3 g 6/3 g 5/3 p 3/3 g 6/3 g 6/3 g 8/3 g C 5/3 g C 6/3 g C 8/3 p 7/3 g D 6/3 g D 8/3 p /3 g E 8/3 p 6/3 Slide
12 Example The multiplexer has a maximum input capacitance of 6 units on each input. It must drive a load of 60 units. Estimate the delay of the NND and compound gate designs. Slide
13 Example The multiplexer has a maximum input capacitance of 6 units on each input. It must drive a load of 60 units. Estimate the delay of the NND and compound gate designs. D0 S D S D0 S D S H 60 / 6 0 N Slide 3 3
14 NND Solution D0 S D S Slide
15 NND Solution P + G (/3) (/3) 6/9 F GH 60 / 9 ˆ N f F. D Nfˆ + P.τ D0 S D S Slide 5 5
16 Compound Solution D0 S D S Slide 6 6
17 Compound Solution P + 5 G (6/3) () F GH 0 ˆ N f F.5 D Nfˆ + P τ D0 S D S Slide 7 7
18 Example 5 nnotate your designs with transistor sizes that achieve this delay. Slide 8 8
19 Example 5 nnotate your designs with transistor sizes that achieve this delay * (/3) / * / Slide 9 9
20 Input Order Our parasitic delay model was too simple Calculate parasitic delay for falling If arrives latest? If arrives latest? x 6C C Slide 0 0
21 Input Order Our parasitic delay model was too simple Calculate parasitic delay for falling If arrives latest? τ If arrives latest?.33τ x 6C C Slide
22 Inner & Outer Inputs Outer input is closest to rail () Inner input is closest to output () If input arrival time is known Connect latest input to inner terminal Slide
23 symmetric Gates symmetric gates favor one input over another Ex: suppose input of a NND gate is most critical Use smaller transistor on (less capacitance) oost size of noncritical input So total resistance is same reset g g g total g + g reset /3 symmetric gate approaches g on critical input ut total logical effort goes up Slide 3 3
24 symmetric Gates symmetric gates favor one input over another Ex: suppose input of a NND gate is most critical Use smaller transistor on (less capacitance) oost size of noncritical input reset So total resistance is same g 0/9 g /3 reset g total g + g 8/9 symmetric gate approaches g on critical input ut total logical effort goes up Slide
25 Symmetric Gates Inputs can be made perfectly symmetric Slide 5 5
26 Skewed Gates Skewed gates favor one edge over another Ex: suppose rising output of inverter is most critical Downsize noncritical nmos transistor HIskew inverter unskewed inverter (equal rise resistance) unskewed inverter (equal fall resistance) / / Calculate logical effort by comparing to unskewed inverter with same effective resistance on that edge. Slide 6 6
27 Skewed Gates Skewed gates favor one edge over another Ex: suppose rising output of inverter is most critical Downsize noncritical nmos transistor HIskew inverter unskewed inverter (equal rise resistance) unskewed inverter (equal fall resistance) / / Calculate logical effort by comparing to unskewed inverter with same effective resistance on that edge..5 / 3 5/6.5 /.5 5/3 Slide 7 7
28 HI and LOSkew Def: Logical effort of a skewed gate for a particular transition is the ratio of the input capacitance of that gate to the input capacitance of an unskewed inverter delivering the same output current for the same transition. Skewed gates reduce size of noncritical transistors HIskew gates favor rising output (small nmos) LOskew gates favor falling output (small pmos) Logical effort is smaller for favored direction ut larger for the other direction Slide 8 8
29 Catalog of Skewed Gates Inverter NND NOR unskewed /3 /3 /3 5/3 5/3 5/3 HIskew / 5/6 5/3 5/ LOskew /3 /3 Slide 9 9
30 Catalog of Skewed Gates Inverter NND NOR unskewed /3 /3 /3 5/3 5/3 5/3 HIskew / 5/6 5/3 5/ / / LOskew /3 /3 Slide 30 30
31 Catalog of Skewed Gates Inverter NND NOR unskewed /3 /3 /3 5/3 5/3 5/3 HIskew / 5/6 5/3 5/ 3/ / / 3/ 3 9/ LOskew /3 /3 3/ 3/ Slide 3 3
32 symmetric Skew Combine asymmetric and skewed gates Downsize noncritical transistor on unimportant input Reduces parasitic delay for critical input reset reset /3 Slide 3 3
33 est P/N Ratio We have selected P/N ratio for unit rise and fall resistance (μ 3 for an inverter). lternative: choose ratio for least average delay Ex: inverter Delay driving identical inverter P t pdf t pdr t pd Differentiate t pd w.r.t. P Least delay for P Slide 33 33
34 est P/N Ratio We have selected P/N ratio for unit rise and fall resistance (μ 3 for an inverter). lternative: choose ratio for least average delay Ex: inverter Delay driving identical inverter P t pdf (P+) t pdr (P+)(μ/P) t pd (P+)(+μ/P)/ (P + + μ + μ/p)/ Differentiate t pd w.r.t. P Least delay for P μ Slide 3 3
35 P/N Ratios In general, best P/N ratio is sqrt of equal delay ratio. Only improves average delay slightly for inverters ut significantly decreases area and power Inverter NND NOR fastest. P/N ratio Slide 35 35
36 P/N Ratios In general, best P/N ratio is sqrt of that giving equal delay. Only improves average delay slightly for inverters ut significantly decreases area and power Inverter NND NOR fastest. P/N ratio /3 /3 /3 3/ Slide 36 36
37 Observations For speed: NND vs. NOR Many simple stages vs. fewer high fanin stages Latestarriving input For area and power: Many simple stages vs. fewer high fanin stages Slide 37 37
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