Very Large Scale Integration (VLSI)


 Samantha Goodman
 4 years ago
 Views:
Transcription
1 Very Large Scale Integration (VLSI) Lecture 4 Dr. Ahmed H. Madian Dr. Ahmed H. MadianVLSI
2 Contents Delay estimation Simple RC model PenfieldRubenstein Model Logical effort Delay minimization techniques Transistor sizing Wiring sizing Distributed drivers Large driver Wiring techniques Dr. Ahmed H. MadianVLSI
3 Circuit characterization & performance Resistance estimation Capacitance estimation Inductance estimation Delay estimation Simple RC model PenfieldRubenstein Model Delay minimization techniques Transistor sizing Distributed drivers Driving large loads Wiring techniques Dr. Ahmed H. MadianVLSI 3
4 Delay Estimation How to estimate the delay for your layout?  use a simulator  Solve the differential equation to get the exact delay 3 model your circuit using one of the defined delay models like RC Dr. Ahmed H. MadianVLSI 4
5 Signal Delay Time Signal delay time is composed as follows Gate delay time Interconnection delay time due to minimization the delay times decreases the output impedance of buffers increases, thus the importance of interconnection delays increases So, signal delay time becomes less dependent on gate delay but more dependent on interconnection delay time Dr. Ahmed H. MadianVLSI 5
6 Elmore Delay ON transistors look like resistors Pullup or pulldown network modeled as RC ladder Elmore delay of RC ladder t R C pd itosource i nodes i R C R R C R R R C R R R 3 R N N N C C C 3 C N 4: DC and Transient Response 6
7 Routing Delay estimation (cont.) W W Elmore Delay: R total = n R U R u R u R u R u R u R u R u C u C u C u C u C u C u C u C total = n C U total = n R U C U Dr. Ahmed H. MadianVLSI 7
8 Delay Estimation For MOSFET transistor, transit Velocity = µ. L velocity Where µ = mobility and = electric filed = V DS /L transit For lower delay, L V L DS L V DD V DD may be increased but we have limit of break down S N+ N+ L may be decreased but there s a problem with technology and Resistance Dr. Ahmed H. MadianVLSI 8 G L D
9 Delay estimation (cont.) Equivalent circuit used for MOSFET Ideal Switch + Capacitance and ON Resistance Unit NMOS has resistance R, Capacitance C Unit PMOS has resistance R, Capacitance C Capacitance proportional to width Resistance is inversely proportional to width Define a model for delay based on the unit delay Treat every MOSFET as resistance. Lump intermediate node capacitance with load capacitance. u = R S * C Gate of min size transistor V in R G Cg Dr. Ahmed H. MadianVLSI 9
10 Simple RC model Assume all pull up /pulldown resistors are summed as R pu /R pd and all capacitance are summed in the output capacitance V DD V DD R P =.5R n V in u = R n C g R P R P inv = R P C g R n R n V in inv = 5 R n C g C g C g inv = R n C g Inverter pair delay = inv + inv = 7 R n C g Dr. Ahmed H. MadianVLSI 0
11 Elmore Delay Model V DD Calculate the delays in generalized RC trees. For a group of transistors in series (as in NAND gate), t R d Where R i is the summed resistance from point i to power or ground and C i is the capacitance at point i. Ex.: for 4 input NAND gate the fall time will be, i i C i a b c d R R xc R R R xc R R R R tdf ( RN xccd ) N N bc N N N3 ab N N N3 N 4 Dr. Ahmed H. MadianVLSI a b c d C ab C bc C cd xc C out out out
12 Delay Components Delay has two parts Parasitic delay 6 or 7 RC Independent of load Effort delay 4h RC Proportional to load capacitance Dr. Ahmed H. MadianVLSI
13 Logical Effort Chip designers face a bewildering array of choices What is the best circuit topology for a function? How many stages of logic give least delay? How wide should the transistors be? Logical effort is a method to make these decisions Uses a simple model of delay Allows backoftheenvelope calculations Helps make rapid comparisons between alternatives Emphasizes remarkable symmetries Dr. Ahmed H. MadianVLSI 3
14 Normalized Delay: d Delay Plots d = f + p = gh + p input NAND Inverter g = p = d = h + g = 4/3 p = d = (4/3)h + Effort Delay: f 0 Parasitic Delay: p Electrical Effort: h = C out / C in Dr. Ahmed H. MadianVLSI 4
15 Computing Logical Effort DEF: Logical effort is the ratio of the input capacitance of a gate to the input capacitance of an inverter delivering the same output current. Measure from delay vs. fanout plots Or estimate by counting transistor widths A Y A B Y A B 4 4 Y C in = 3 g = 3/3 C in = 4 g = 4/3 C in = 5 g = 5/3 Dr. Ahmed H. MadianVLSI 5
16 Example: Ring Oscillator Estimate the frequency of an Nstage ring oscillator Logical Effort: g = Electrical Effort: h = Parasitic Delay: p = Stage Delay: d = Frequency: f osc = Dr. Ahmed H. MadianVLSI 6
17 Example: Ring Oscillator Estimate the frequency of an Nstage ring oscillator Logical Effort: g = Electrical Effort: h = Parasitic Delay: p = Stage Delay: d = 3 stage ring oscillator in 0.6 m process has frequency of ~ 00 MHz Frequency: f osc = /(*N*d) = /4N Dr. Ahmed H. MadianVLSI 7
18 Example: FO4 Inverter Estimate the delay of a fanoutof4 (FO4) inverter d Logical Effort: g = Electrical Effort: h = Parasitic Delay: p = Stage Delay: d = Dr. Ahmed H. MadianVLSI 8
19 Example: FO4 Inverter Estimate the delay of a fanoutof4 (FO4) inverter d Logical Effort: g = Electrical Effort: h = 4 Parasitic Delay: p = Stage Delay: d = 5 The FO4 delay is about 00 ps in 0.6 m process 60 ps in a 80 nm process f/3 ns in an f m process Dr. Ahmed H. MadianVLSI 9
20 Multistage Logic Networks Logical effort generalizes to multistage networks Path Logical Effort Path Electrical Effort Path Effort G g i H C C outpath inpath F f g h i i i 0 g = h = x/0 x g = 5/3 h = y/x y g 3 = 4/3 h 3 = z/y z g 4 = h 4 = 0/z 0 Dr. Ahmed H. MadianVLSI 0
21 Multistage Logic Networks Logical effort generalizes to multistage networks Path Logical Effort Path Electrical Effort Path Effort Can we write F = GH? G g i H C out path C in path F f g h i i i Dr. Ahmed H. MadianVLSI
22 Paths that Branch No! Consider paths that branch: G = H = GH = h = h = F = GH? Dr. Ahmed H. MadianVLSI
23 Paths that Branch No! Consider paths that branch: G = H = 90 / 5 = 8 GH = 8 h = (5 +5) / 5 = 6 h = 90 / 5 = 6 F = g g h h = 36 = GH Dr. Ahmed H. MadianVLSI 3
24 Designing Fast Circuits i F D d D P Delay is smallest when each stage bears same effort fˆ g h F i i Thus minimum delay of N stage path is N D NF P This is a key result of logical effort Find fastest possible delay Doesn t require calculating gate sizes N Dr. Ahmed H. MadianVLSI 4
25 Gate Sizes How wide should the gates be for least delay? fˆ gh g C in i C C out in gc i fˆ Working backward, apply capacitance transformation to find input capacitance of each gate given load it drives. Check work by verifying input cap spec is met. out i Dr. Ahmed H. MadianVLSI 5
26 Example: 3stage path Select gate sizes x and y for least delay from A to B x x y 45 A 8 x y B 45 Dr. Ahmed H. MadianVLSI 6
27 Example: 3stage path x Logical Effort G = Electrical Effort H = Branching Effort B = Path Effort F = Best Stage Effort ˆf Parasitic Delay P = Delay D = A 8 x x y y 45 B 45 Dr. Ahmed H. MadianVLSI 7
28 Example: 3stage path Logical Effort G = (4/3)*(5/3)*(5/3) = 00/7 Electrical Effort H = 45/8 Branching Effort B = 3 * = 6 Path Effort F = GBH = 5 Best Stage Effort ˆ 3 F 5 x x A 8 x Parasitic Delay P = = 7 Delay D = 3*5 + 7 = = 4.4 FO4 f y y 45 B 45 Dr. Ahmed H. MadianVLSI 8
29 Example: 3stage path Work backward for sizes y = x = x x y 45 A 8 x y B 45 Dr. Ahmed H. MadianVLSI 9
30 Example: 3stage path Work backward for sizes y = 45 * (5/3) / 5 = 5 x = (5*) * (5/3) / 5 = 0 45 A P: 4 N: 4 P: 4 N: 6 P: N: 3 B 45 Dr. Ahmed H. MadianVLSI 30
31 Best Number of Stages How many stages should a path use? Minimizing number of stages is not always fastest Example: drive 64bit datapath with unit inverter Initial Driver D = Datapath Load N: f: D: 3 4 Dr. Ahmed H. MadianVLSI 3
32 Best Number of Stages How many stages should a path use? Minimizing number of stages is not always fastest Example: drive 64bit datapath with unit inverter Initial Driver D = NF /N + P = N(64) /N + N Datapath Load N: f: D: Fastest Dr. Ahmed H. MadianVLSI 3
33 Example: input NAND Estimate worstcase rising and falling delay of input NAND driving h identical gates. Y A B x h copies Dr. Ahmed H. MadianVLSI 33
34 Example: input NAND Estimate rising and falling propagation delays of a input NAND driving h identical gates. A B x 6C C Y 4hC h copies Dr. Ahmed H. MadianVLSI 34
35 Example: input NAND Estimate rising and falling propagation delays of a input NAND driving h identical gates. A B x 6C C Y 4hC h copies R Y (6+4h)C tpdr Dr. Ahmed H. MadianVLSI 35
36 Example: input NAND Estimate rising and falling propagation delays of a input NAND driving h identical gates. A B x 6C C Y 4hC h copies R Y (6+4h)C t pdr 64h RC Dr. Ahmed H. MadianVLSI 36
37 Example: input NAND Estimate rising and falling propagation delays of a input NAND driving h identical gates. A B x 6C C Y 4hC h copies Dr. Ahmed H. MadianVLSI 37
38 Example: input NAND Estimate rising and falling propagation delays of a input NAND driving h identical gates. A B x 6C C Y 4hC h copies R/ x R/ C Y (6+4h)C tpdf Dr. Ahmed H. MadianVLSI 38
39 Example: input NAND Estimate rising and falling propagation delays of a input NAND driving h identical gates. A B x 6C C Y 4hC h copies R/ x R/ C Y (6+4h)C pdf R R R h RC t C h C Dr. Ahmed H. MadianVLSI 39
40 Delay Estimation (cont.) 3 input NAND gate with it s gate and diffusion capacitances (assuming all nodes are contacted). Estimation at schematic levels will be different if you look at the layouts. Dr. Ahmed H. MadianVLSI 40
41 Layout models Good layout minimizes the diffusion area. 3 input NAND shown here, shares one diffusion contact, thus lowering the output capacitance by C. Contact diffusions are assumed. Dr. Ahmed H. MadianVLSI 4
42 Body effect & delay If A goes from 0 to while B, C and D are, then all the intermediate nodes in the pulldown chain have already been discharged and the top MOSFET sees only a small body effect. If D goes from 0 to while A, B and C are, then the intermediate nodes are all one V t below V dd and the upper MOSFETs see a larger body effect. Dr. Ahmed H. MadianVLSI 4
43 Circuit characterization & performance Delay estimation Simple RC model PenfieldRubenstein Model Delay minimization techniques Transistor sizing Wiring sizing Distributed drivers Driving large loads Wiring techniques Dr. Ahmed H. MadianVLSI 43
44 Delay minimization techniques V DD V DD Transistor sizing / a b c d out a C out V in V out b C ab Transistor sizing for minimum delay / c C bc Each Series transistors has C cd (W/L) = 3(W/L) basic inverter. each parallel transistors has (W/L) = (W/L) basic inverter Basic inverter d Dr. Ahmed H. MadianVLSI 44
45 Wire sizing Wire length is determined by layout architecture, but we can choose wire width to minimize delay. width can vary with distance from driver to adjust the resistance which drives downstream capacitance. Dr. Ahmed H. MadianVLSI 45
46 Optimal wire sizing Widening the wire reduces the resistance, but increases its capacitance. Wire with minimum delay has an exponential taper. Optimal tapering improves delay by about 8%. Can approximate optimal tapering with a few rectangular segments. Dr. Ahmed H. MadianVLSI 46
47 Tapering of wiring trees Different branches of tree can be set to different lengths to optimize delay. Dr. Ahmed H. MadianVLSI 47
48 Spanning tree A spanning tree has segments that go directly between sources and sinks. Dr. Ahmed H. MadianVLSI 48
49 Distributed driver Decrease output load capacitance Undistributed : C load = 8C g Distributed: C load = 6C g Dr. Ahmed H. MadianVLSI 49
50 Driving large loads If large loads have to be driven, the delay may increase drastically. Large loads are output capacitances, clock trees, etc. t d = t inv (C L /C G ) Where t inv =is the average delay of a minimumsized inverter driving another minimum sized inverter, C L = load capacitance& C G = gate capacitance C L = 000C G, then t d = 000.t inv A possibility to reduce the delay, is to use a sequence of n scaled inverters, but not the optimum delay: C Load t d = t inv (40/)+ t inv (00/40) + t inv (000/00)= 50t inv Dr. Ahmed H. MadianVLSI 50
51 Driving large loads (cont.) We may decrease the delay by using larger transistors to decrease the resistance. Scaling transistors by factor S results in: R W L sca led sca led R S S sca led W L normal t r =.R scaled (C in + C load ) But scaling the transistor also affects the input capacitance of the transistor: C in,scaled = S. C in Dr. Ahmed H. MadianVLSI 5
52 Driving large loads (cont.) reference... C in 3 N N (W/L) S(W/L) S (W/L) S N (W/L) S N (W/L) C Load The problem is if input signal is placed at inverter what s the number of stages N and the scaling factor S that will minimize the time needed for the signal to reach C load Dr. Ahmed H. MadianVLSI 5
53 Dr. Ahmed H. MadianVLSI 53 Driving large loads (cont.) t d = t +t +t 3 + +t N C Load... C in 3 N N (W/L) S(W/L) S (W/L) S N (W/L) S N (W/L) reference C = SC C 3 =S C C C 4 =S 3 C C N =s N C R R =R /S R 3 =R /S R N=R /S N R N=R /S N ) ( SR C N t C S S R C S S R C S S R C S S R C S S R R SC t d N N N N d t d = R C + R C 3 + R 3 C 4 + +R N C N +R N C load C load = S N C
54 Driving large loads (cont.) t t d C N d Load N( SR C S N C ln C ln S C ln C ln C S Load Load ) reference R R =R /S R 3 =R /S R N =R /S N R N=R /S N... C in 3 N N ( SR C (W/L) S(W/L) S (W/L) S N (W/L) S N (W/L) C C = SC 3 =S C C C 4 =S 3 C C N =s N C ) C Load For minimum delay, dt d /ds = 0; this yields, S = e =.7 Dr. Ahmed H. MadianVLSI 54
55 Example we want to drive a load capacitor of value C L = 0pF. The input stage is defined as C =0fF and has k =00µA/V. calculate the number of stages N to minimize the delay. solution N C Load ln 0x0 ln( ) C 5 0x0 ln(500) ln( S) ln( e) 6. We will select N = 6 to obtain noninverting chain Dr. Ahmed H. MadianVLSI 55
56 nd assignment Check the web site for Assignment 3. Due date next Saturday. Dr. Ahmed H. MadianVLSI 56
57 Refs. David Harris, Logical effort lecture notes, Hurvey mid college, 004. CMOS VLSI Design, 4 th edition Introduction to VLSI, nd edition Dr. Ahmed H. MadianVLSI 57
ECE429 Introduction to VLSI Design
ECE429 Introduction to VLSI Design Lecture 5: LOGICAL EFFORT Erdal Oruklu Illinois Institute of Technology Some of these slides have been adapted from the slides provided by David Harris, Harvey Mudd College
More informationEE 447 VLSI Design. Lecture 5: Logical Effort
EE 447 VLSI Design Lecture 5: Logical Effort Outline Introduction Delay in a Logic Gate Multistage Logic Networks Choosing the Best Number of Stages Example Summary EE 4475: VLSI Logical Design Effort
More informationVLSI Design, Fall Logical Effort. Jacob Abraham
6. Logical Effort 6. Logical Effort Jacob Abraham Department of Electrical and Computer Engineering The University of Texas at Austin VLSI Design Fall 207 September 20, 207 ECE Department, University of
More informationLecture 6: Logical Effort
Lecture 6: Logical Effort Outline Logical Effort Delay in a Logic Gate Multistage Logic Networks Choosing the Best Number of Stages Example Summary Introduction Chip designers face a bewildering array
More informationLecture 8: Combinational Circuit Design
Lecture 8: Combinational Circuit Design Mark McDermott Electrical and Computer Engineering The University of Texas at ustin 9/5/8 Verilog to Gates module mux(input s, d0, d, output y); assign y = s? d
More informationIntroduction to CMOS VLSI Design. Lecture 5: Logical Effort. David Harris. Harvey Mudd College Spring Outline
Introduction to CMOS VLSI Design Lecture 5: Logical Effort David Harris Harve Mudd College Spring 00 Outline Introduction Dela in a Logic Gate Multistage Logic Networks Choosing the Best Number of Stages
More informationLecture 8: Logic Effort and Combinational Circuit Design
Lecture 8: Logic Effort and Combinational Circuit Design Slides courtesy of Deming Chen Slides based on the initial set from David Harris CMOS VLSI Design Outline q Logical Effort q Delay in a Logic Gate
More informationLogical Effort: Designing for Speed on the Back of an Envelope David Harris Harvey Mudd College Claremont, CA
Logical Effort: Designing for Speed on the Back of an Envelope David Harris David_Harris@hmc.edu Harvey Mudd College Claremont, CA Outline o Introduction o Delay in a Logic Gate o Multistage Logic Networks
More informationLogical Effort. Sizing Transistors for Speed. Estimating Delays
Logical Effort Sizing Transistors for Speed Estimating Delays Would be nice to have a back of the envelope method for sizing gates for speed Logical Effort Book by Sutherland, Sproull, Harris Chapter 1
More informationLecture 4: DC & Transient Response
Introduction to CMOS VLSI Design Lecture 4: DC & Transient Response David Harris Harvey Mudd College Spring 004 Outline DC Response Logic Levels and Noise Margins Transient Response Delay Estimation Slide
More informationEE5780 Advanced VLSI CAD
EE5780 Advanced VLSI CAD Lecture 4 DC and Transient Responses, Circuit Delays Zhuo Feng 4.1 Outline Pass Transistors DC Response Logic Levels and Noise Margins Transient Response RC Delay Models Delay
More informationLecture 5: DC & Transient Response
Lecture 5: DC & Transient Response Outline q Pass Transistors q DC Response q Logic Levels and Noise Margins q Transient Response q RC Delay Models q Delay Estimation 2 Activity 1) If the width of a transistor
More informationLecture 6: DC & Transient Response
Lecture 6: DC & Transient Response Slides courtesy of Deming Chen Slides based on the initial set from David Harris CMOS VLSI Design Outline Pass Transistors DC Response Logic Levels and Noise Margins
More informationLecture 12 CMOS Delay & Transient Response
EE 471: Transport Phenomena in Solid State Devices Spring 2018 Lecture 12 CMOS Delay & Transient Response Bryan Ackland Department of Electrical and Computer Engineering Stevens Institute of Technology
More informationLecture 5: DC & Transient Response
Lecture 5: DC & Transient Response Outline Pass Transistors DC Response Logic Levels and Noise Margins Transient Response RC Delay Models Delay Estimation 2 Pass Transistors We have assumed source is grounded
More informationCPE/EE 427, CPE 527 VLSI Design I Delay Estimation. Department of Electrical and Computer Engineering University of Alabama in Huntsville
CPE/EE 47, CPE 57 VLSI Design I Delay Estimation Department of Electrical and Computer Engineering University of labama in Huntsville leksandar Milenkovic ( www.ece.uah.edu/~milenka ) Review: CMOS Circuit
More informationInterconnect (2) Buffering Techniques. Logical Effort
Interconnect (2) Buffering Techniques. Logical Effort Lecture 14 18322 Fall 2002 Textbook: [Sections 4.2.1, 8.2.3] A few announcements! M1 is almost over: The checkoff is due today (by 9:30PM) Students
More informationIntroduction to CMOS VLSI Design. Logical Effort B. Original Lecture by Jay Brockman. University of Notre Dame Fall 2008
Introduction to CMOS VLSI Design Logical Effort Part B Original Lecture b Ja Brockman Universit of Notre Dame Fall 2008 Modified b Peter Kogge Fall 2010,2011,2015, 2018 Based on lecture slides b David
More informationCARNEGIE MELLON UNIVERSITY DEPARTMENT OF ELECTRICAL AND COMPUTER ENGINEERING DIGITAL INTEGRATED CIRCUITS FALL 2002
CARNEGIE MELLON UNIVERSITY DEPARTMENT OF ELECTRICAL AND COMPUTER ENGINEERING 18322 DIGITAL INTEGRATED CIRCUITS FALL 2002 Final Examination, Monday Dec. 16, 2002 NAME: SECTION: Time: 180 minutes Closed
More informationDC and Transient. Courtesy of Dr. Daehyun Dr. Dr. Shmuel and Dr.
DC and Transient Courtesy of Dr. Daehyun Lim@WSU, Dr. Harris@HMC, Dr. Shmuel Wimer@BIU and Dr. Choi@PSU http://csce.uark.edu +1 (479) 575604 yrpeng@uark.edu Pass Transistors We have assumed source is
More information7. Combinational Circuits
7. Combinational Circuits Jacob Abraham Department of Electrical and Computer Engineering The University of Texas at Austin VLSI Design Fall 2017 September 25, 2017 ECE Department, University of Texas
More information5. CMOS Gate Characteristics CS755
5. CMOS Gate Characteristics Last module: CMOS Transistor theory This module: DC Response Logic Levels and Noise Margins Transient Response Delay Estimation Transistor ehavior 1) If the width of a transistor
More informationEE115C Digital Electronic Circuits Homework #5
EE115C Digital Electronic Circuits Homework #5 Due Thursday, May 13, 6pm @ 56147E EIV Problem 1 Elmore Delay Analysis Calculate the Elmore delay from node A to node B using the values for the resistors
More informationSpiral 2 7. Capacitance, Delay and Sizing. Mark Redekopp
27.1 Spiral 2 7 Capacitance, Delay and Sizing Mark Redekopp 27.2 Learning Outcomes I understand the sources of capacitance in CMOS circuits I understand how delay scales with resistance, capacitance
More informationVLSI GATE LEVEL DESIGN UNIT  III P.VIDYA SAGAR ( ASSOCIATE PROFESSOR) Department of Electronics and Communication Engineering, VBIT
VLSI UNIT  III GATE LEVEL DESIGN P.VIDYA SAGAR ( ASSOCIATE PROFESSOR) contents GATE LEVEL DESIGN : Logic Gates and Other complex gates, Switch logic, Alternate gate circuits, Time Delays, Driving large
More informationEE M216A.:. Fall Lecture 5. Logical Effort. Prof. Dejan Marković
EE M26A.:. Fall 200 Lecture 5 Logical Effort Prof. Dejan Marković ee26a@gmail.com Logical Effort Recap Normalized delay d = g h + p g is the logical effort of the gate g = C IN /C INV Inverter is sized
More informationHomework #2 10/6/2016. C int = C g, where 1 t p = t p0 (1 + C ext / C g ) = t p0 (1 + f/ ) f = C ext /C g is the effective fanout
0/6/06 Homework # Lecture 8, 9: Sizing and Layout of omplex MOS Gates Reading: hapter 4, sections 4.34.5 October 3 & 5, 06 hapter, section.5.5 Prof. R. Iris ahar Weste & Harris vailable on course webpage
More informationDigital Integrated Circuits A Design Perspective
Digital Integrated Circuits Design Perspective Jan M. Rabaey nantha Chandrakasan orivoje Nikolić Designing Combinational Logic Circuits November 2002. 1 Combinational vs. Sequential Logic In Combinational
More informationInterconnect (2) Buffering Techniques.Transmission Lines. Lecture Fall 2003
Interconnect (2) Buffering Techniques.Transmission Lines Lecture 12 18322 Fall 2003 A few announcements Partners Lab Due Times Midterm 1 is nearly here Date: 10/14/02, time: 3:004:20PM, place: in class
More informationLecture 7 Circuit Delay, Area and Power
Lecture 7 Circuit Delay, Area and Power lecture notes from S. Mitra Intro VLSI System course (EE271) Introduction to VLSI Systems 1 Circuits and Delay Introduction to VLSI Systems 2 Power, Delay and Area:
More informationChapter 9. Estimating circuit speed. 9.1 Counting gate delays
Chapter 9 Estimating circuit speed 9.1 Counting gate delays The simplest method for estimating the speed of a VLSI circuit is to count the number of VLSI logic gates that the input signals must propagate
More informationCPE/EE 427, CPE 527 VLSI Design I L13: Wires, Design for Speed. Course Administration
CPE/EE 427, CPE 527 VLSI Design I L3: Wires, Design for Speed Department of Electrical and Computer Engineering University of labama in Huntsville leksandar Milenkovic ( www.ece.uah.edu/~milenka ) www.ece.uah.edu/~milenka/cpe52705f
More informationCMPEN 411 VLSI Digital Circuits Spring 2012
CMPEN 411 VLSI Digital Circuits Spring 2012 Lecture 09: Resistance & Inverter Dynamic View [Adapted from Rabaey s Digital Integrated Circuits, Second Edition, 2003 J. Rabaey, A. Chandrakasan, B. Nikolic]
More informationDigital Integrated Circuits (83313) Lecture 5: Interconnect. Semester B, Lecturer: Adam Teman TAs: Itamar Levi, Robert Giterman 1
Digital Integrated Circuits (83313) Lecture 5: Interconnect Semester B, 201516 Lecturer: Adam Teman TAs: Itamar Levi, Robert Giterman 1 What will we learn today? 1 A First Glance at Interconnect 2 3
More informationDelay and Power Estimation
EEN454 Digital Integrated ircuit Design Delay and Power Estimation EEN 454 Delay Estimation We would like to be able to easily estimate delay Not as accurate as simulation But make it easier to ask What
More informationand V DS V GS V T (the saturation region) I DS = k 2 (V GS V T )2 (1+ V DS )
ECE 4420 Spring 2005 Page 1 FINAL EXAMINATION NAME SCORE /100 Problem 1O 2 3 4 5 6 7 Sum Points INSTRUCTIONS: This exam is closed book. You are permitted four sheets of notes (three of which are your sheets
More informationLecture 1: Gate Delay Models
High Speed CMOS VLSI Design Lecture 1: Gate Delay Models (c) 1997 David Harris 1.0 Designing for Speed on the Back of an Envelope Custom IC design is all about speed. For a small amount of money, one synthesize
More informationEE 466/586 VLSI Design. Partha Pande School of EECS Washington State University
EE 466/586 VLSI Design Partha Pande School of EECS Washington State University pande@eecs.wsu.edu Lecture 9 Propagation delay Power and delay Tradeoffs Follow board notes Propagation Delay Switching Time
More informationEE141. Administrative Stuff
Spring 2004 Digital Integrated ircuits Lecture 15 Logical Effort Pass Transistor Logic 1 dministrative Stuff First (short) project to be launched next Th. Overall span: 1 week Hardware lab this week Hw
More informationLecture 8: Combinational Circuits
Introduction to CMOS VLSI Design Lecture 8: Combinational Circuits David Harris Harvey Mudd College Spring 004 Outline ubble Pushing Compound Gates Logical Effort Example Input Ordering symmetric Gates
More informationEE M216A.:. Fall Lecture 4. Speed Optimization. Prof. Dejan Marković Speed Optimization via Gate Sizing
EE M216A.:. Fall 2010 Lecture 4 Speed Optimization Prof. Dejan Marković ee216a@gmail.com Speed Optimization via Gate Sizing Gate sizing basics P:N ratio Complex gates Velocity saturation ti Tapering Developing
More information! Dynamic Characteristics. " Delay
EE 57: Digital Integrated ircuits and LI Fundamentals Lecture Outline! Dynamic haracteristics " Delay Lec : February, 8 MO Inverter and Interconnect Delay 3 Review: Propogation Delay Definitions Dynamic
More information3. Design a stick diagram for the PMOS logic shown below [16] Y = (A + B).C. 4. Design a layout diagram for the CMOS logic shown below [16]
Code No: RR420203 Set No. 1 1. (a) Find g m and r ds for an nchannel transistor with V GS = 1.2V; V tn = 0.8V; W/L = 10; µncox = 92 µa/v 2 and V DS = Veff + 0.5V The out put impedance constant. λ = 95.3
More informationChapter 4. Digital Integrated Circuit Design I. ECE 425/525 Chapter 4. CMOS design can be realized meet requirements from
Digital Integrated Circuit Design I ECE 425/525 Professor R. Daasch Depar tment of Electrical and Computer Engineering Portland State University Portland, OR 972070751 (daasch@ece.pdx.edu) http://ece.pdx.edu/~ecex25
More informationEECS 151/251A Homework 5
EECS 151/251A Homework 5 Due Monday, March 5 th, 2018 Problem 1: Timing The datapath shown below is used in a simple processor. clk rd1 rd2 0 wr regfile 1 0 ALU REG 1 The elements used in the design have
More informationIntegrated Circuits & Systems
Federal University of Santa Catarina Center for Technology Computer Science & Electronics Engineering Integrated Circuits & Systems INE 5442 Lecture 16 CMOS Combinational Circuits  2 guntzel@inf.ufsc.br
More informationC.K. Ken Yang UCLA Courtesy of MAH EE 215B
Decoders: Logical Effort Applied C.K. Ken Yang UCLA yang@ee.ucla.edu Courtesy of MAH 1 Overview Reading Rabaey 6.2.2 (Ratioed logic) W&H 6.2.2 Overview We have now gone through the basics of decoders,
More informationCHAPTER 15 CMOS DIGITAL LOGIC CIRCUITS
CHAPTER 5 CMOS DIGITAL LOGIC CIRCUITS Chapter Outline 5. CMOS Logic Gate Circuits 5. Digital Logic Inverters 5.3 The CMOS Inverter 5.4 Dynamic Operation of the CMOS Inverter 5.5 Transistor Sizing 5.6 Power
More informationENEE 359a Digital VLSI Design
SLIDE 1 ENEE 359a Digital VLSI Design & Logical Effort Prof. blj@ece.umd.edu Credit where credit is due: Slides contain original artwork ( Jacob 2004) as well as material taken liberally from Irwin & Vijay
More informationDynamic operation 20
Dynamic operation 20 A simple model for the propagation delay Symmetric inverter (rise and fall delays are identical) otal capacitance is linear t p Minimum length devices R W C L t = 0.69R C = p W L 0.69
More informationName: Grade: Q1 Q2 Q3 Q4 Q5 Total. ESE370 Fall 2015
University of Pennsylvania Department of Electrical and System Engineering CircuitLevel Modeling, Design, and Optimization for Digital Systems ESE370, Fall 205 Midterm Wednesday, November 4 Point values
More informationLecture 5. Logical Effort Using LE on a Decoder
Lecture 5 Logical Effort Using LE on a Decoder Mark Horowitz Computer Systems Laboratory Stanford University horowitz@stanford.edu Copyright 00 by Mark Horowitz Overview Reading Harris, Logical Effort
More informationEE115C Digital Electronic Circuits Homework #6
Problem 1 Sizing of adder blocks Electrical Engineering Department Spring 2010 EE115C Digital Electronic Circuits Homework #6 Solution Figure 1: Mirror adder. Study the mirror adder cell (textbook, pages
More informationThe Wire. Digital Integrated Circuits A Design Perspective. Jan M. Rabaey Anantha Chandrakasan Borivoje Nikolic. July 30, 2002
Digital Integrated Circuits A Design Perspective Jan M. Rabaey Anantha Chandrakasan Borivoje Nikolic The Wire July 30, 2002 1 The Wire transmitters receivers schematics physical 2 Interconnect Impact on
More informationEE 560 CHIP INPUT AND OUTPUT (I/0) CIRCUITS. Kenneth R. Laker, University of Pennsylvania
1 EE 560 CHIP INPUT AND OUTPUT (I/0) CIRCUITS 2 > ESD PROTECTION CIRCUITS (INPUT PADS) > ONCHIP CLOCK GENERATION & DISTRIBUTION > OUTPUT PADS > ONCHIP NOISE DUE TO PARASITIC INDUCTANCE > SUPER BUFFER
More informationCOMP 103. Lecture 10. Inverter Dynamics: The Quest for Performance. Section 5.4.2, What is this lecture+ about? PERFORMANCE
COMP 103 Lecture 10 Inverter Dynamics: The Quest for Performance Section 5.4.2, 5.4.3 [All lecture notes are adapted from Mary Jane Irwin, Penn State, which were adapted from Rabaey s Digital Integrated
More informationLecture 9: Interconnect
Digital Integrated Circuits (83313) Lecture 9: Interconnect Semester B, 201617 Lecturer: Dr. Adam Teman TAs: Itamar Levi, Robert Giterman 23 May 2017 Disclaimer: This course was prepared, in its entirety,
More informationLecture 9: Combinational Circuit Design
Lecture 9: Combinational Circuit Design Outline Bubble Pushing Compound Gates Logical Effort Example Input Ordering symmetric Gates Skewed Gates Best P/N ratio 0: Combinational Circuits CMOS VLSI Design
More informationESE570 Spring University of Pennsylvania Department of Electrical and System Engineering Digital Integrated Cicruits AND VLSI Fundamentals
University of Pennsylvania Department of Electrical and System Engineering Digital Integrated Cicruits AND VLSI Fundamentals ESE570, Spring 2018 Final Monday, Apr 0 5 Problems with point weightings shown.
More informationLecture Outline. ESE 570: Digital Integrated Circuits and VLSI Fundamentals. Review: 1st Order RC Delay Models. Review: TwoInput NOR Gate (NOR2)
ESE 570: Digital Integrated Circuits and VLSI Fundamentals Lec 14: March 1, 2016 Combination Logic: Ratioed and Pass Logic Lecture Outline! CMOS Gates Review " CMOS Worst Case Analysis! Ratioed Logic Gates!
More informationCMOS logic gates. João Canas Ferreira. March University of Porto Faculty of Engineering
CMOS logic gates João Canas Ferreira University of Porto Faculty of Engineering March 2016 Topics 1 General structure 2 General properties 3 Cell layout João Canas Ferreira (FEUP) CMOS logic gates March
More informationIntegrated Circuits & Systems
Federal University of Santa Catarina Center for Technology Computer Science & Electronics Engineering Integrated Circuits & Systems INE 5442 Lecture 14 The CMOS Inverter: dynamic behavior (sizing, inverter
More information9/18/2008 GMU, ECE 680 Physical VLSI Design
ECE680: Physical VLSI Design Chapter III CMOS Device, Inverter, Combinational circuit Logic and Layout Part 3 Combinational Logic Gates (textbook chapter 6) 9/18/2008 GMU, ECE 680 Physical VLSI Design
More informationDigital Integrated Circuits. The Wire * Fuyuzhuo. *Thanks for Dr.Guoyong.SHI for his slides contributed for the talk. Digital IC.
Digital Integrated Circuits The Wire * Fuyuzhuo *Thanks for Dr.Guoyong.SHI for his slides contributed for the talk Introduction The Wire transmitters receivers schematics physical 2 Interconnect Impact
More informationLecture 8: Combinational Circuits
Introduction to CMOS VLSI Design Lecture 8: Combinational Circuits David Harris Harvey Mudd College Spring 00 Outline ubble Pushing Compound Gates Logical Effort Example Input Ordering symmetric Gates
More informationEE115C Digital Electronic Circuits Homework #4
EE115 Digital Electronic ircuits Homework #4 Problem 1 Power Dissipation Solution Vdd =1.0V onsider the source follower circuit used to drive a load L =20fF shown above. M1 and M2 are both NMOS transistors
More informationEE 330 Lecture 37. Digital Circuits. Other Logic Families. Propagation Delay basic characterization Device Sizing (Inverter and multipleinput gates)
EE 330 Lecture 37 Digital Circuits Other Logic Families Static Power Dissipation Propagation Delay basic characterization Device Sizing (Inverter and multipleinput gates) Review from Last Time Inverter
More informationESE 570: Digital Integrated Circuits and VLSI Fundamentals
ESE 570: Digital Integrated Circuits and VLSI Fundamentals Lec 15: March 3, 2016 Combination Logic: Ratioed & Pass Logic, and Performance Lecture Outline! CMOS NOR2 Worst Case Analysis! Pass Transistor
More informationStatic CMOS Circuits. Example 1
Static CMOS Circuits Conventional (ratioless) static CMOS Covered so far Ratioed logic (depletion load, pseudo nmos) Pass transistor logic ECE 261 Krish Chakrabarty 1 Example 1 module mux(input s, d0,
More informationCMOS Digital Integrated Circuits Lec 13 Semiconductor Memories
Lec 13 Semiconductor Memories 1 Semiconductor Memory Types Semiconductor Memories Read/Write (R/W) Memory or Random Access Memory (RAM) ReadOnly Memory (ROM) Dynamic RAM (DRAM) Static RAM (SRAM) 1. Mask
More informationESE570 Spring University of Pennsylvania Department of Electrical and System Engineering Digital Integrated Cicruits AND VLSI Fundamentals
University of Pennsylvania Department of Electrical and System Engineering Digital Integrated Cicruits AND VLSI Fundamentals ESE570, Spring 017 Final Wednesday, May 3 4 Problems with point weightings shown.
More informationEEC 116 Lecture #5: CMOS Logic. Rajeevan Amirtharajah Bevan Baas University of California, Davis Jeff Parkhurst Intel Corporation
EEC 116 Lecture #5: CMOS Logic Rajeevan mirtharajah Bevan Baas University of California, Davis Jeff Parkhurst Intel Corporation nnouncements Quiz 1 today! Lab 2 reports due this week Lab 3 this week HW
More informationName: Answers. Mean: 83, Standard Deviation: 12 Q1 Q2 Q3 Q4 Q5 Q6 Total. ESE370 Fall 2015
University of Pennsylvania Department of Electrical and System Engineering CircuitLevel Modeling, Design, and Optimization for Digital Systems ESE370, Fall 2015 Final Tuesday, December 15 Problem weightings
More informationLecture 9: Combinational Circuits
Introduction to CMOS VLSI Design Lecture 9: Combinational Circuits David Harris, Harvey Mudd College Kartik Mohanram and Steven Levitan University of Pittsburgh Outline q ubble Pushing q Compound Gates
More information5.0 CMOS Inverter. W.Kucewicz VLSICirciuit Design 1
5.0 CMOS Inverter W.Kucewicz VLSICirciuit Design 1 Properties Switching Threshold Dynamic Behaviour Capacitance Propagation Delay nmos/pmos Ratio Power Consumption Contents W.Kucewicz VLSICirciuit Design
More informationESE 570: Digital Integrated Circuits and VLSI Fundamentals
ESE 570: Digital Integrated Circuits and VLSI Fundamentals Lec 24: April 19, 2018 Crosstalk and Wiring, Transmission Lines Lecture Outline! Crosstalk! Repeaters in Wiring! Transmission Lines " Where transmission
More informationEEE 421 VLSI Circuits
EEE 421 CMOS Properties Full railtorail swing high noise margins» Logic levels not dependent upon the relative device sizes transistors can be minimum size ratioless Always a path to V dd or GND in steady
More informationAnswers. Name: Grade: Q1 Q2 Q3 Q4 Total mean: 83, stdev: 14. ESE370 Fall 2017
University of Pennsylvania Department of Electrical and System Engineering CircuitLevel Modeling, Design, and Optimization for Digital Systems ESE370, Fall 2017 Midterm 2 Monday, November 6 Point values
More informationLecture 6: Circuit design part 1
Lecture 6: Circuit design part 6. Combinational circuit design 6. Sequential circuit design 6.3 Circuit simulation 6.4. Hardware description language Combinational Circuit Design. Combinational circuit
More informationUniversity of Toronto. Final Exam
University of Toronto Final Exam Date  Apr 18, 011 Duration:.5 hrs ECE334 Digital Electronics Lecturer  D. Johns ANSWER QUESTIONS ON THESE SHEETS USING BACKS IF NECESSARY 1. Equation sheet is on last
More information! Crosstalk. ! Repeaters in Wiring. ! Transmission Lines. " Where transmission lines arise? " Lossless Transmission Line.
ESE 570: Digital Integrated Circuits and VLSI Fundamentals Lec 24: April 19, 2018 Crosstalk and Wiring, Transmission Lines Lecture Outline! Crosstalk! Repeaters in Wiring! Transmission Lines " Where transmission
More informationECE 425 Midterm Overview. Fall 2017
ECE 425 Midterm Overview Fall 2017 Overview q Midterm (20% of total grade) Oct 24 th 3:305:00pm in class q Materials Lecture 1 through 11 MP0, MP1 HW1, HW2 Practice exam q Rules 1 page of cheat sheet,
More informationInterconnects. Wire Resistance Wire Capacitance Wire RC Delay Crosstalk Wire Engineering Repeaters. ECE 261 James Morizio 1
Interconnects Wire Resistance Wire Capacitance Wire RC Delay Crosstalk Wire Engineering Repeaters ECE 261 James Morizio 1 Introduction Chips are mostly made of wires called interconnect In stick diagram,
More informationTopic 4. The CMOS Inverter
Topic 4 The CMOS Inverter Peter Cheung Department of Electrical & Electronic Engineering Imperial College London URL: www.ee.ic.ac.uk/pcheung/ Email: p.cheung@ic.ac.uk Topic 41 Noise in Digital Integrated
More informationUNIVERSITY OF CALIFORNIA, BERKELEY College of Engineering Department of Electrical Engineering and Computer Sciences
UNIVERSITY OF CALIFORNIA, BERKELEY College of Engineering Department of Electrical Engineering and Computer Sciences Elad Alon Homework #9 EECS141 PROBLEM 1: TIMING Consider the simple state machine shown
More informationEECS 141: FALL 05 MIDTERM 1
University of California College of Engineering Department of Electrical Engineering and Computer Sciences D. Markovic TuTh 111:3 Thursday, October 6, 6:38:pm EECS 141: FALL 5 MIDTERM 1 NAME Last SOLUTION
More informationEE213, Spr 2017 HW#3 Due: May 17 th, in class. Figure 1
RULES: Please try to work on your own. Discussion is permissible, but identical submissions are unacceptable! Please show all intermediate steps: a correct solution without an explanation will get zero
More informationECE 546 Lecture 10 MOS Transistors
ECE 546 Lecture 10 MOS Transistors Spring 2018 Jose E. SchuttAine Electrical & Computer Engineering University of Illinois jesa@illinois.edu NMOS Transistor NMOS Transistor NChannel MOSFET Built on ptype
More informationPhysical Design of Digital Integrated Circuits (EN0291 S40) Sherief Reda Division of Engineering, Brown University Fall 2006
Physical Design of Digital Integrated Circuits (EN0291 S40) Sherief Reda Division of Engineering, Brown University Fall 2006 1 Lecture 04: Timing Analysis Static timing analysis STA for sequential circuits
More informationHightoLow Propagation Delay t PHL
HightoLow Propagation Delay t PHL V IN switches instantly from low to high. Driver transistor (nchannel) immediately switches from cutoff to saturation; the pchannel pullup switches from triode to
More informationLogic Gate Sizing. The method of logical effort. João Canas Ferreira. March University of Porto Faculty of Engineering
Logic Gate Sizing The method of logical effort João Canas Ferreira University of Porto Faculty of Engineering March 016 Topics 1 Modeling CMOS Gates Chain of logic gates João Canas Ferreira (FEUP) Logic
More informationVLSI Design and Simulation
VLSI Design and Simulation Performance Characterization Topics Performance Characterization Resistance Estimation Capacitance Estimation Inductance Estimation Performance Characterization Inverter Voltage
More informationEE 330 Lecture 39. Digital Circuits. Propagation Delay basic characterization Device Sizing (Inverter and multipleinput gates)
EE 330 Lecture 39 Digital ircuits Propagation Delay basic characterization Device Sizing (Inverter and multipleinput gates) Review from last lecture Other MOS Logic Families Enhancement Load NMOS Enhancement
More informationLecture 4: CMOS Transistor Theory
Introduction to CMOS VLSI Design Lecture 4: CMOS Transistor Theory David Harris, Harvey Mudd College Kartik Mohanram and Steven Levitan University of Pittsburgh Outline q Introduction q MOS Capacitor q
More informationTopics to be Covered. capacitance inductance transmission lines
Topics to be Covered Circuit Elements Switching Characteristics Power Dissipation Conductor Sizes Charge Sharing Design Margins Yield resistance capacitance inductance transmission lines Resistance of
More informationEE141Fall 2011 Digital Integrated Circuits
EE4Fall 20 Digital Integrated Circuits Lecture 5 Memory decoders Administrative Stuff Homework #6 due today Project posted Phase due next Friday Project done in pairs 2 Last Lecture Last lecture Logical
More informationECE 342 Solid State Devices & Circuits 4. CMOS
ECE 34 Solid State Devices & Circuits 4. CMOS Jose E. SchuttAine Electrical & Computer Engineering University of Illinois jschutt@emlab.uiuc.edu ECE 34 Jose Schutt Aine 1 Digital Circuits V IH : Input
More informationIntegrated Circuits & Systems
Federal University of Santa Catarina Center for Technology Computer Science & Electronics Engineering Integrated Circuits & Systems INE 5442 Lecture 13 The CMOS Inverter: dynamic behavior (delay) guntzel@inf.ufsc.br
More informationDigital Integrated Circuits 2nd Inverter
Digital Integrated Circuits The Inverter The CMOS Inverter V DD Analysis Inverter complex gate Cost V in V out complexity & Area Integrity and robustness C L Static behavior Performance Dynamic response
More informationLecture 14: Circuit Families
Introduction to CMOS VLSI Design Lecture 4: Circuit Families David Harris, Harvey Mudd College Kartik Mohanram and Steven Levitan University of Pittsburgh Outline q PseudonMOS Logic q Dynamic Logic q
More information