Lecture 8: Combinational Circuit Design


 Caroline Kennedy
 2 years ago
 Views:
Transcription
1 Lecture 8: Combinational Circuit Design Mark McDermott Electrical and Computer Engineering The University of Texas at ustin 9/5/8
2 Verilog to Gates module mux(input s, d0, d, output y); assign y = s? d : d0; endmodule Sketch a design using ND, OR, and NOT gates. D0 S D S 9/5/8 Page
3 Example ) Sketch the design using NND, NOR, and NOT gates. ssume ~S is available. D0 S D S 9/5/8 Page 3
4 Example 3 3) Sketch a design using one compound gate and one NOT gate. ssume ~S is available. D0 S D S 9/5/8 Page 4
5 Sizing Compound Gates Inverter equivalence unit inverter OI OI = =! + C = + CD C C D D E C Complex OI!! ( ) =! + C + DE! C C 4 C 4 D 4 C D C D E E 6 D C g = 3/3 g = 6/3 g = 6/3 g = 5/3 p = 3/3 g = 6/3 g = 6/3 g = 8/3 g C = 5/3 g C = 6/3 g C = 8/3 p = 7/3 g D = 6/3 g D = 8/3 p = /3 g E = 8/3 p = 6/3 9/5/8 Page 5
6 Input Order Matters Our parasitic delay model was too simple Calculate parasitic delay for falling If arrives latest? t If arrives latest?.33t x 6C C 9/5/8 Page 6
7 Inner & Outer Inputs Outer input is closest to rail () Inner input is closest to output () If input arrival time is known Connect latest input to inner terminal 9/5/8 Page 7
8 symmetric Gates symmetric gates favor one input over another Example: Suppose input of a NND gate is most critical Use smaller transistor on (less capacitance) oost size of noncritical input So total resistance is same reset reset 4/3 4 9/5/8 Page 8
9 Symmetric Gates Inputs can be made perfectly symmetric 9/5/8 Page 9
10 Skewed Gates Skewed gates favor one edge over another Ex: suppose rising output of inverter is most critical Downsize noncritical NMOS transistor HIskew inverter unskewed inverter (equal rise resistance) unskewed inverter (equal fall resistance) / / 9/5/8 Page 0
11 HI and LOSkew Logical effort of a skewed gate for a particular transition is the ratio of the input capacitance of that gate to the input capacitance of an unskewed inverter delivering the same output current for the same transition Skewed gates reduce size of noncritical transistors HIskew gates favor rising output (small nmos) LOskew gates favor falling output (small pmos) Logical effort is smaller for favored direction ut larger for the other direction 9/5/8 Page
12 Catalog of Skewed Gates Inverter NND NOR unskewed g u = g d = g avg = g u = 4/3 g d = 4/3 g avg = 4/3 4 4 g u = 5/3 g d = 5/3 g avg = 5/3 HIskew / g u = 5/6 g d = 5/3 g avg = 5/4 g u = g d = g avg = 3/ / 4 4 / g u = 3/ g d = 3 g avg = 9/4 LOskew g u = 4/3 g d = /3 g avg = g u = g d = g avg = 3/ g u = g d = g avg = 3/ 9/5/8 Page
13 symmetric Skew Combine asymmetric and skewed gates Downsize noncritical transistor on unimportant input Reduces parasitic delay for critical input reset reset 4/3 4 9/5/8 Page 3
14 est P/N Ratio We have selected P/N ratio for equivalent rise and fall resistance (µ = 3 for an inverter). lternative: choose ratio for least average delay Ex: inverter Delay driving identical inverter t pdf = (P+) t pdr = (P+)(µ/P) t pd = (P+)(+µ/P)/ = (P + + µ + µ/p)/ Differentiate t pd w.r.t. P Least delay for P = µ P 9/5/8 Page 4
15 P/N Ratios In general, best P/N ratio is square root of that giving equal delay Only improves average delay slightly for inverters ut significantly decreases area and power Inverter NND NOR fastest.44 P/N ratio g u =.5 g d = 0.8 g avg = 0.98 g u = 4/3 g d = 4/3 g avg = 4/3 g u = g d = g avg = 3/ 9/5/8 Page 5
16 Device Sizing Device sizing is one of the key techniques for circuit optimization For standard cell type of designs, gate sizing For example of inverters, INV, INV, INVC,, INVN,, each having a different driving capabilities. For microprocessor or custom designs, more finegrained control, transistor sizing For each transistor 9/5/8 Page 6
17 Driver Sizing Given: chain of cascaded drivers driving a load Ignore the interconnect between drivers (i.e. assume driver and load CL is closer enough) Obtain: Optimize the driver sizes to minimize delay, or minimize total area while meeting target delay Delay and area/power tradeoff d d d k C L C g C g Cgk 9/5/8 Page 7
18 Driver Sizing using stage ratios d d d k C L C g C g C gk Constant stage ratio: where!"#$!"!"#$!". (i.e..78) = ( '( ') )$/, We will use 34 in this class 9/5/8 Page 8
19 Stage ratio example 0 60 Inverter equivalent stage ratio = 3 beta ratio = 40 0 Sized NND beta ratio = /5/8 Page 9
20 Sizing example Size these three circuits. Load on node : 40/0 inverter Use stage ratio of 4 Use beta ratio of
21 Stage ratio example HW #3 Use stage ratio of 3 Use beta ratio of F G 0 60 C 80 D 90 E 9/5/8 Page
22 ackup: Logical Effort 9/5/8
23 Introduction Chip designers face a plethora of choices What is the best circuit topology for a function? How many stages of logic give least delay? How wide should the transistors be? Logical effort is one method to make these decisions Uses a simple model of delay llows backoftheenvelope calculations Helps make rapid comparisons between alternatives Emphasizes remarkable symmetries 9/5/8 Page 4
24 Example Design the decoder for a register file. Decoder specifications: 6 word register file Each word is 3 bits wide Each bit presents load of 3 unitsized transistors True and complementary address inputs [3:0] Each input may drive 0 unitsized transistors Need to decide: How many stages to use? How large should each gate be? How fast can decoder operate? [3:0] [3:0] 4:6 Decoder 6 3 bits Register File 6 words 9/5/8 Page 5
25 Delay in a Logic Gate Express delays in processindependent unit d = d abs t Delay has two components: d = f + p Effort delay f = gh (a.k.a. stage effort) τ = 3RC» ps in 80 nm process 3 ps in 65nm µm process g: logical effort Measures relative ability of gate to deliver current g = for inverter h: electrical effort = Cout / Cin Ratio of output to input caps. Sometimes called fanout effort Parasitic delay p Represents intrinsic delay of gate driving no load Set by internal parasitic capacitance 9/5/8 Page 6
26 Delay Plots d = f + p d = gh + p Normalized Delay: d input NND Inverter g = 4/3 p = d = (4/3)h + g = p = d = h + Effort Delay: f 0 Parasitic Delay: p Electrical Effort: h = C out / C in What about a NOR? 9/5/8 Page 7
27 Computing Logical Effort Logical effort is the ratio of the input capacitance of a gate to the input capacitance of an inverter delivering the same output current Measure from delay vs. fanout plots Or estimate by counting transistor widths 4 4 C in = 3 g = 3/3 C in = 4 g = 4/3 C in = 5 g = 5/3 9/5/8 Page 8
28 Computing Logical Effort for a NND Gate Recall that delay = t pd /τ and τ 3RC For the NND gate below x 6C C 4hC R (6+4h)C The rising propagation delay is: t pdr = 6+ 4h RC ( ) Therefore d = t pd /τ = (6 + 4h)RC/3RC = 4/3h + Recall d = gh + p therefore g=4/3 9/5/8 Page 9
29 Computing Logical Effort for a NND Gate (cont) The logical effort for the falling signal is the same, however the intrinsic delay is not. x 6C C 4hC R/ x R/ C (6+4h)C tpdf = C + ë + h Cû + = 7+ 4h RC ( )( R ) ( 6 4 ) ( R R é ù ) ( ) Where d = t pd /τ = (7 + 4h)RC/3RC = 4/3h +7/3 9/5/8 Page 30
30 Catalog of Gates Logical effort of common gates Gate type Number of inputs 3 4 n Inverter NND 4/3 5/3 6/3 (n+)/3 NOR 5/3 7/3 9/3 (n+)/3 Tristate / mux XOR, XNOR 4, 4 6,, 6 8, 6, 6, 8 9/5/8 Page 3
31 Catalog of Gates Parasitic (intrinsic) delay of common gates In multiples of p inv (») Gate type Number of inputs 3 4 n Inverter NND 3 4 n NOR 3 4 n Tristate / mux n XOR, XNOR /5/8 Page 3
32 Example: Ring Oscillator Estimate the frequency of an Nstage ring oscillator 3 stage ring oscillator in Logical Effort: g = 0.6 µm process has Electrical Effort: h = frequency of ~ 00 MHz Parasitic Delay: p = Stage Delay: d = Frequency: f osc = /(*N*d) = /4N Recall that the signal has to propagate through the inverter chain twice to make a complete waveform Page 33 9/5/8
33 Example: FO4 Inverter Estimate the delay of a fanoutof4 (FO4) inverter d Logical Effort: g = Electrical Effort: h = 4 Parasitic Delay: p = Stage Delay: d = 5 The FO4 delay is about 00 ps in 0.6 µm process 60 ps in a 80 nm process f/3 ns in an f µm process (f/3 ps in an f nm process) Page 34 9/5/8
34 Multistage Logic Networks Logical effort generalizes to multistage networks Path Logical Effort à Path Electrical Effort à G = Õ g i H = C C outpath inpath Path Effort à F= Õ fi = Õgh i i 0 g = h = x/0 x g = 5/3 h = y/x y g 3 = 4/3 h 3 = z/y z g 4 = h 4 = 0/z 0 Can we write F = GH in general? Page 35 9/5/8
35 Paths that ranch No! Consider paths that branch: G = H = 90 / 5 = 8 GH = 8 h = (5 +5) / 5 = 6 h = 90 / 5 = 6 F = g g h h = 36 = GH Page 36 9/5/8
36 ranching Effort Introduce branching effort ccounts for branching between stages in path b = C on path C + C on path off path = Õb i hi Õ Note: = H We compute the path effort F = GH Page 37 9/5/8
37 Multistage Delays Path Effort Delay D F = å f i Path Parasitic Delay P= å p i Path Delay = å = + i F D d D P Page 38 9/5/8
38 Designing Fast Circuits = å i = F + D d D P Delay is smallest when each stage bears same effort ˆ N f = gh i i = F Thus minimum delay of N stage path is N D = NF + P This is a key result of logical effort Find fastest possible delay Doesn t require calculating gate sizes Page 39 9/5/8
39 Gate Sizes How wide should the gates be for least delay? fˆ = gh = g Þ C = in i Working backward, apply capacitance transformation to find input capacitance of each gate given load it drives C C out i in gc fˆ out i Check work by verifying input cap spec is met 9/5/8 Page 40
40 Example: 3stage path Select gate sizes x and y for least delay from to x x y 45 8 x y 45 9/5/8 Page 4
41 Example: 3stage path x x y 45 8 x y 45 Logical Effort G = (4/3)*(5/3)*(5/3) = 00/7 Electrical Effort H = 45/8 ranching Effort = 3 * = 6 Path Effort F = GH = 5 est Stage Effort 3 f ˆ = F = 5 Parasitic Delay P = = 7 Delay D = 3*5 + 7 = = 4.4 FO4 Page 4 9/5/8
42 Example: 3stage path Work backward for sizes y = 45 * (5/3) / 5 = 5 x = (5*) * (5/3) / 5 = 0 45 P: 4 N: 4 P: 4 N: 6 P: N: /5/8 Page 43
43 est Number of Stages How many stages should a path use? Minimizing number of stages is not always fastest Example: drive 64bit datapath with unit inverter Initial Driver D = NF /N + P = N(64) /N + N Datapath Load N: f: D: Fastest Page 44 9/5/8
44 Derivation Consider adding inverters to end of path How many give least delay? = n N + å i +  i= D NF p N n p ( ) inv Logic lock: n Stages Path Effort F N  n Extra Inverters Define best stage effort r = F N D N N N N =  F ln F + F + p = 0 inv p + r  ln r = 0 inv ( ) Page 45 9/5/8
45 est Stage Effort p + r  ln r = 0 ( ) has no closedform solution inv Neglecting parasitics (p inv = 0), we find r =.78 (e) For p inv =, solve numerically for r = 3.59 Page 46 9/5/8
46 Sensitivity nalysis How sensitive is delay to using exactly the best number of stages? D(N) /D(N) (r=6) (r =.4) < r < 6 gives delay within 5% of optimal We can be sloppy! For example, use r = 4 N / N Page 47 9/5/8
47 Let s revisit the decoder specifications Design the decoder for a register file. Decoder specifications: 6 word register file Each word is 3 bits wide Each bit presents load of 3 unitsized transistors True and complementary address inputs [3:0] Each input may drive 0 unitsized transistors Need to decide: How many stages to use? How large should each gate be? How fast can decoder operate? [3:0] [3:0] 4:6 Decoder 6 3 bits Register File 6 words 9/5/8 Page 48
48 Decoder Ex: Number of Stages Decoder effort is mainly electrical and branching Electrical Effort: H = (3*3) / 0 = 9.6 ranching Effort: = 8 If we neglect logical effort (assume G = ) Path Effort: F = GH = 76.8 Number of Stages: N = log 4 F = 3. Try a 3stage design based on rough estimation Page 49 9/5/8
49 Decoder: Gate Sizes & Delay Logical Effort: G = * 6/3 * = (not an estimation) Path Effort: F = GH = 54 Stage Effort: Path Delay: /3 f ˆ = F = 5.36 D= 3 fˆ =. Gate sizes: z = 96*/5.36 = 8; y = 8*/5.36 = 6.7 [3] [3] [] [] [] [] [0] [0] y z word[0] 96 units of wordline capacitance y z word[5] Page 50 9/5/8
50 Decoder: Comparison Compare many alternatives with a spreadsheet Design N G P D NND4INV NNDNOR 0/ INVNND4INV 3 6. NND4INVINVINV 4 7. NNDNORINVINV 4 0/ NNDINVNNDINV 4 6/ INVNNDINVNNDINV 5 6/ NNDINVNNDINVINVINV 6 6/ /5/8 Page 5
51 Review of Definitions Term Stage Path number of stages logical effort electrical effort branching effort effort effort delay parasitic delay delay g h = b = f f p = C C C out in onpath gh + C C onpath d = f + p offpath N G = Õ g i H = C C outpath inpath = Õb i F D = GH F = å P = å p i å f i i D = d = D + P F Page 5 9/5/8
52 Logical Effort Methodology Summary Compute path effort Estimate best number of stages Sketch path with N stages Estimate least delay Determine best stage effort F = GH N = log 4 N D = NF + P ˆ f = F N F Find gate sizes C in i = gc i fˆ out i 9/5/8 Page 53
53 Limits of Logical Effort Chicken and egg problem Need path to compute G ut don t know number of stages without G Simplistic delay model Neglects input rise time effects Interconnect Iteration required in designs with wire Maximum speed only Not minimum area/power for constrained delay 9/5/8 Page 54
54 Summary Logical effort is useful for thinking of delay in circuits Numeric logical effort characterizes gates NNDs are faster than NORs in CMOS Paths are fastest when effort delays are ~4 Path delay is weakly sensitive to stages, sizes ut using fewer stages doesn t mean faster paths Delay of path is about log 4 F FO4 inverter delays Inverters and NND best for driving large caps Provides language for discussing fast circuits ut requires practice to master 9/5/8 Page 55
55 9/5/8 Page 56
56 9/5/8 Page 5757
57 9/5/8 Page 5858
Lecture 8: Logic Effort and Combinational Circuit Design
Lecture 8: Logic Effort and Combinational Circuit Design Slides courtesy of Deming Chen Slides based on the initial set from David Harris CMOS VLSI Design Outline q Logical Effort q Delay in a Logic Gate
More informationLecture 6: Logical Effort
Lecture 6: Logical Effort Outline Logical Effort Delay in a Logic Gate Multistage Logic Networks Choosing the Best Number of Stages Example Summary Introduction Chip designers face a bewildering array
More informationEE 447 VLSI Design. Lecture 5: Logical Effort
EE 447 VLSI Design Lecture 5: Logical Effort Outline Introduction Delay in a Logic Gate Multistage Logic Networks Choosing the Best Number of Stages Example Summary EE 4475: VLSI Logical Design Effort
More informationECE429 Introduction to VLSI Design
ECE429 Introduction to VLSI Design Lecture 5: LOGICAL EFFORT Erdal Oruklu Illinois Institute of Technology Some of these slides have been adapted from the slides provided by David Harris, Harvey Mudd College
More informationVLSI Design, Fall Logical Effort. Jacob Abraham
6. Logical Effort 6. Logical Effort Jacob Abraham Department of Electrical and Computer Engineering The University of Texas at Austin VLSI Design Fall 207 September 20, 207 ECE Department, University of
More informationIntroduction to CMOS VLSI Design. Lecture 5: Logical Effort. David Harris. Harvey Mudd College Spring Outline
Introduction to CMOS VLSI Design Lecture 5: Logical Effort David Harris Harve Mudd College Spring 00 Outline Introduction Dela in a Logic Gate Multistage Logic Networks Choosing the Best Number of Stages
More informationLecture 8: Combinational Circuits
Introduction to CMOS VLSI Design Lecture 8: Combinational Circuits David Harris Harvey Mudd College Spring 00 Outline ubble Pushing Compound Gates Logical Effort Example Input Ordering symmetric Gates
More informationLecture 8: Combinational Circuits
Introduction to CMOS VLSI Design Lecture 8: Combinational Circuits David Harris Harvey Mudd College Spring 004 Outline ubble Pushing Compound Gates Logical Effort Example Input Ordering symmetric Gates
More informationLecture 9: Combinational Circuits
Introduction to CMOS VLSI Design Lecture 9: Combinational Circuits David Harris, Harvey Mudd College Kartik Mohanram and Steven Levitan University of Pittsburgh Outline q ubble Pushing q Compound Gates
More informationLecture 9: Combinational Circuit Design
Lecture 9: Combinational Circuit Design Outline Bubble Pushing Compound Gates Logical Effort Example Input Ordering symmetric Gates Skewed Gates Best P/N ratio 0: Combinational Circuits CMOS VLSI Design
More informationLogical Effort: Designing for Speed on the Back of an Envelope David Harris Harvey Mudd College Claremont, CA
Logical Effort: Designing for Speed on the Back of an Envelope David Harris David_Harris@hmc.edu Harvey Mudd College Claremont, CA Outline o Introduction o Delay in a Logic Gate o Multistage Logic Networks
More information7. Combinational Circuits
7. Combinational Circuits Jacob Abraham Department of Electrical and Computer Engineering The University of Texas at Austin VLSI Design Fall 2017 September 25, 2017 ECE Department, University of Texas
More informationLogical Effort. Sizing Transistors for Speed. Estimating Delays
Logical Effort Sizing Transistors for Speed Estimating Delays Would be nice to have a back of the envelope method for sizing gates for speed Logical Effort Book by Sutherland, Sproull, Harris Chapter 1
More informationLecture 6: Circuit design part 1
Lecture 6: Circuit design part 6. Combinational circuit design 6. Sequential circuit design 6.3 Circuit simulation 6.4. Hardware description language Combinational Circuit Design. Combinational circuit
More informationVery Large Scale Integration (VLSI)
Very Large Scale Integration (VLSI) Lecture 4 Dr. Ahmed H. Madian Ah_madian@hotmail.com Dr. Ahmed H. MadianVLSI Contents Delay estimation Simple RC model PenfieldRubenstein Model Logical effort Delay
More informationIntroduction to CMOS VLSI Design. Logical Effort B. Original Lecture by Jay Brockman. University of Notre Dame Fall 2008
Introduction to CMOS VLSI Design Logical Effort Part B Original Lecture b Ja Brockman Universit of Notre Dame Fall 2008 Modified b Peter Kogge Fall 2010,2011,2015, 2018 Based on lecture slides b David
More informationStatic CMOS Circuits. Example 1
Static CMOS Circuits Conventional (ratioless) static CMOS Covered so far Ratioed logic (depletion load, pseudo nmos) Pass transistor logic ECE 261 Krish Chakrabarty 1 Example 1 module mux(input s, d0,
More informationEE M216A.:. Fall Lecture 5. Logical Effort. Prof. Dejan Marković
EE M26A.:. Fall 200 Lecture 5 Logical Effort Prof. Dejan Marković ee26a@gmail.com Logical Effort Recap Normalized delay d = g h + p g is the logical effort of the gate g = C IN /C INV Inverter is sized
More informationDigital Integrated Circuits A Design Perspective
Digital Integrated Circuits Design Perspective Jan M. Rabaey nantha Chandrakasan orivoje Nikolić Designing Combinational Logic Circuits November 2002. 1 Combinational vs. Sequential Logic In Combinational
More informationC.K. Ken Yang UCLA Courtesy of MAH EE 215B
Decoders: Logical Effort Applied C.K. Ken Yang UCLA yang@ee.ucla.edu Courtesy of MAH 1 Overview Reading Rabaey 6.2.2 (Ratioed logic) W&H 6.2.2 Overview We have now gone through the basics of decoders,
More informationEE141. Administrative Stuff
Spring 2004 Digital Integrated ircuits Lecture 15 Logical Effort Pass Transistor Logic 1 dministrative Stuff First (short) project to be launched next Th. Overall span: 1 week Hardware lab this week Hw
More informationLecture 5. Logical Effort Using LE on a Decoder
Lecture 5 Logical Effort Using LE on a Decoder Mark Horowitz Computer Systems Laboratory Stanford University horowitz@stanford.edu Copyright 00 by Mark Horowitz Overview Reading Harris, Logical Effort
More informationEECS 151/251A Homework 5
EECS 151/251A Homework 5 Due Monday, March 5 th, 2018 Problem 1: Timing The datapath shown below is used in a simple processor. clk rd1 rd2 0 wr regfile 1 0 ALU REG 1 The elements used in the design have
More informationInterconnect (2) Buffering Techniques. Logical Effort
Interconnect (2) Buffering Techniques. Logical Effort Lecture 14 18322 Fall 2002 Textbook: [Sections 4.2.1, 8.2.3] A few announcements! M1 is almost over: The checkoff is due today (by 9:30PM) Students
More informationCPE/EE 427, CPE 527 VLSI Design I L13: Wires, Design for Speed. Course Administration
CPE/EE 427, CPE 527 VLSI Design I L3: Wires, Design for Speed Department of Electrical and Computer Engineering University of labama in Huntsville leksandar Milenkovic ( www.ece.uah.edu/~milenka ) www.ece.uah.edu/~milenka/cpe52705f
More informationEE5780 Advanced VLSI CAD
EE5780 Advanced VLSI CAD Lecture 4 DC and Transient Responses, Circuit Delays Zhuo Feng 4.1 Outline Pass Transistors DC Response Logic Levels and Noise Margins Transient Response RC Delay Models Delay
More informationEEC 118 Lecture #6: CMOS Logic. Rajeevan Amirtharajah University of California, Davis Jeff Parkhurst Intel Corporation
EEC 118 Lecture #6: CMOS Logic Rajeevan mirtharajah University of California, Davis Jeff Parkhurst Intel Corporation nnouncements Quiz 1 today! Lab 2 reports due this week Lab 3 this week HW 3 due this
More informationEECS 427 Lecture 8: Adders Readings: EECS 427 F09 Lecture 8 1. Reminders. HW3 project initial proposal: due Wednesday 10/7
EECS 427 Lecture 8: dders Readings: 11.111.3.3 3 EECS 427 F09 Lecture 8 1 Reminders HW3 project initial proposal: due Wednesday 10/7 You can schedule a halfhour hour appointment with me to discuss your
More informationEE M216A.:. Fall Lecture 4. Speed Optimization. Prof. Dejan Marković Speed Optimization via Gate Sizing
EE M216A.:. Fall 2010 Lecture 4 Speed Optimization Prof. Dejan Marković ee216a@gmail.com Speed Optimization via Gate Sizing Gate sizing basics P:N ratio Complex gates Velocity saturation ti Tapering Developing
More informationLecture 4: DC & Transient Response
Introduction to CMOS VLSI Design Lecture 4: DC & Transient Response David Harris Harvey Mudd College Spring 004 Outline DC Response Logic Levels and Noise Margins Transient Response Delay Estimation Slide
More informationLecture 5: DC & Transient Response
Lecture 5: DC & Transient Response Outline q Pass Transistors q DC Response q Logic Levels and Noise Margins q Transient Response q RC Delay Models q Delay Estimation 2 Activity 1) If the width of a transistor
More informationLecture 7: Multistage Logic Networks. Best Number of Stages
Lecture 7: Multstage Logc Networks Multstage Logc Networks (cont. from Lec 06) Examples Readng: Ch. Best Number of Stages How many stages should a path use? Mnmzng number of stages s not always fastest
More information5. CMOS Gate Characteristics CS755
5. CMOS Gate Characteristics Last module: CMOS Transistor theory This module: DC Response Logic Levels and Noise Margins Transient Response Delay Estimation Transistor ehavior 1) If the width of a transistor
More informationCPE/EE 427, CPE 527 VLSI Design I Delay Estimation. Department of Electrical and Computer Engineering University of Alabama in Huntsville
CPE/EE 47, CPE 57 VLSI Design I Delay Estimation Department of Electrical and Computer Engineering University of labama in Huntsville leksandar Milenkovic ( www.ece.uah.edu/~milenka ) Review: CMOS Circuit
More informationCPE/EE 427, CPE 527 VLSI Design I L18: Circuit Families. Outline
CPE/EE 47, CPE 57 VLI Design I L8: Circuit Families Department of Electrical and Computer Engineering University of labama in Huntsville leksandar Milenkovic ( www.ece.uah.edu/~milenka ) www.ece.uah.edu/~milenka/cpe5705f
More informationChapter 4. Digital Integrated Circuit Design I. ECE 425/525 Chapter 4. CMOS design can be realized meet requirements from
Digital Integrated Circuit Design I ECE 425/525 Professor R. Daasch Depar tment of Electrical and Computer Engineering Portland State University Portland, OR 972070751 (daasch@ece.pdx.edu) http://ece.pdx.edu/~ecex25
More informationLecture 5: DC & Transient Response
Lecture 5: DC & Transient Response Outline Pass Transistors DC Response Logic Levels and Noise Margins Transient Response RC Delay Models Delay Estimation 2 Pass Transistors We have assumed source is grounded
More informationEEC 116 Lecture #5: CMOS Logic. Rajeevan Amirtharajah Bevan Baas University of California, Davis Jeff Parkhurst Intel Corporation
EEC 116 Lecture #5: CMOS Logic Rajeevan mirtharajah Bevan Baas University of California, Davis Jeff Parkhurst Intel Corporation nnouncements Quiz 1 today! Lab 2 reports due this week Lab 3 this week HW
More informationPhysical Design of Digital Integrated Circuits (EN0291 S40) Sherief Reda Division of Engineering, Brown University Fall 2006
Physical Design of Digital Integrated Circuits (EN0291 S40) Sherief Reda Division of Engineering, Brown University Fall 2006 1 Lecture 04: Timing Analysis Static timing analysis STA for sequential circuits
More informationLecture 6: DC & Transient Response
Lecture 6: DC & Transient Response Slides courtesy of Deming Chen Slides based on the initial set from David Harris CMOS VLSI Design Outline Pass Transistors DC Response Logic Levels and Noise Margins
More informationLecture 12 CMOS Delay & Transient Response
EE 471: Transport Phenomena in Solid State Devices Spring 2018 Lecture 12 CMOS Delay & Transient Response Bryan Ackland Department of Electrical and Computer Engineering Stevens Institute of Technology
More informationSpiral 2 7. Capacitance, Delay and Sizing. Mark Redekopp
27.1 Spiral 2 7 Capacitance, Delay and Sizing Mark Redekopp 27.2 Learning Outcomes I understand the sources of capacitance in CMOS circuits I understand how delay scales with resistance, capacitance
More informationEstimating Delays. Gate Delay Model. Gate Delay. Effort Delay. Computing Logical Effort. Logical Effort
Estmatng Delas Would be nce to have a back of the envelope method for szng gates for speed Logcal Effort ook b Sutherland, Sproull, Harrs Chapter s on our web page Gate Dela Model Frst, normalze a model
More informationLogic Gate Sizing. The method of logical effort. João Canas Ferreira. March University of Porto Faculty of Engineering
Logic Gate Sizing The method of logical effort João Canas Ferreira University of Porto Faculty of Engineering March 016 Topics 1 Modeling CMOS Gates Chain of logic gates João Canas Ferreira (FEUP) Logic
More informationAnnouncements. EE141Spring 2007 Digital Integrated Circuits. CMOS SRAM Analysis (Read/Write) Class Material. Layout. Read Static Noise Margin
Vo l ta ge ri s e [ V] EESpring 7 Digital Integrated ircuits Lecture SRM Project Launch nnouncements No new labs next week and week after Use labs to work on project Homework #6 due Fr. pm Project updated
More informationCSE370 HW3 Solutions (Winter 2010)
CSE370 HW3 Solutions (Winter 2010) 1. CL2e, 4.9 We are asked to implement the function f(a,,c,,e) = A + C + + + CE using the smallest possible multiplexer. We can t use any extra gates or the complement
More informationEE115C Digital Electronic Circuits Homework #6
Problem 1 Sizing of adder blocks Electrical Engineering Department Spring 2010 EE115C Digital Electronic Circuits Homework #6 Solution Figure 1: Mirror adder. Study the mirror adder cell (textbook, pages
More informationEEE 421 VLSI Circuits
EEE 421 CMOS Properties Full railtorail swing high noise margins» Logic levels not dependent upon the relative device sizes transistors can be minimum size ratioless Always a path to V dd or GND in steady
More informationCARNEGIE MELLON UNIVERSITY DEPARTMENT OF ELECTRICAL AND COMPUTER ENGINEERING DIGITAL INTEGRATED CIRCUITS FALL 2002
CARNEGIE MELLON UNIVERSITY DEPARTMENT OF ELECTRICAL AND COMPUTER ENGINEERING 18322 DIGITAL INTEGRATED CIRCUITS FALL 2002 Final Examination, Monday Dec. 16, 2002 NAME: SECTION: Time: 180 minutes Closed
More informationLecture 4: Implementing Logic in CMOS
Lecture 4: Implementing Logic in CMOS Mark Mcermott Electrical and Computer Engineering The University of Texas at ustin Review of emorgan s Theorem Recall that: () = + and = ( + ) (+) = and + = ( ) ()
More informationLecture 14: Circuit Families
Introduction to CMOS VLSI Design Lecture 4: Circuit Families David Harris, Harvey Mudd College Kartik Mohanram and Steven Levitan University of Pittsburgh Outline q PseudonMOS Logic q Dynamic Logic q
More informationSequential Logic Worksheet
Sequential Logic Worksheet Concept Inventory: Notes: Dlatch & the Dynamic Discipline Dregister Timing constraints for sequential circuits Setup and hold times for sequential circuits 6.004 Worksheet
More informationCOSC3330 Computer Architecture Lecture 2. Combinational Logic
COSC333 Computer rchitecture Lecture 2. Combinational Logic Instructor: Weidong Shi (Larry), PhD Computer Science Department University of Houston Today Combinational Logic oolean lgebra Mux, DeMux, Decoder
More informationIntegrated Circuits & Systems
Federal University of Santa Catarina Center for Technology Computer Science & Electronics Engineering Integrated Circuits & Systems INE 5442 Lecture 16 CMOS Combinational Circuits  2 guntzel@inf.ufsc.br
More informationLecture 1: Gate Delay Models
High Speed CMOS VLSI Design Lecture 1: Gate Delay Models (c) 1997 David Harris 1.0 Designing for Speed on the Back of an Envelope Custom IC design is all about speed. For a small amount of money, one synthesize
More informationUNIVERSITY OF CALIFORNIA College of Engineering Department of Electrical Engineering and Computer Sciences. Professor Oldham Fall 1999
UNIVERSITY OF CLIFORNI College of Engineering Department of Electrical Engineering and Computer Sciences Professor Oldham Fall 1999 EECS 40 FINL EXM 13 December 1999 Name: Last, First Student ID: T: Kusuma
More informationDelay and Power Estimation
EEN454 Digital Integrated ircuit Design Delay and Power Estimation EEN 454 Delay Estimation We would like to be able to easily estimate delay Not as accurate as simulation But make it easier to ask What
More informationDigital EE141 Integrated Circuits 2nd Combinational Circuits
Digital Integrated Circuits Designing i Combinational Logic Circuits 1 Combinational vs. Sequential Logic 2 Static CMOS Circuit t every point in time (except during the switching transients) each gate
More informationEE115C Digital Electronic Circuits Homework #5
EE115C Digital Electronic Circuits Homework #5 Due Thursday, May 13, 6pm @ 56147E EIV Problem 1 Elmore Delay Analysis Calculate the Elmore delay from node A to node B using the values for the resistors
More informationMASSACHUSETTS INSTITUTE OF TECHNOLOGY Department of Electrical Engineering and Computer Sciences
MSSCHUSETTS INSTITUTE OF TECHNOLOGY Department of Electrical Engineering and Computer Sciences nalysis and Design of Digital Integrated Circuits (6.374)  Fall 2003 Quiz #1 Prof. nantha Chandrakasan Student
More informationArithmetic Building Blocks
rithmetic uilding locks Datapath elements dder design Static adder Dynamic adder Multiplier design rray multipliers Shifters, Parity circuits ECE 261 Krish Chakrabarty 1 Generic Digital Processor InputOutput
More informationClock signal in digital circuit is responsible for synchronizing the transfer to the data between processing elements.
1 2 Introduction Clock signal in digital circuit is responsible for synchronizing the transfer to the data between processing elements. Defines the precise instants when the circuit is allowed to change
More information9/18/2008 GMU, ECE 680 Physical VLSI Design
ECE680: Physical VLSI Design Chapter III CMOS Device, Inverter, Combinational circuit Logic and Layout Part 3 Combinational Logic Gates (textbook chapter 6) 9/18/2008 GMU, ECE 680 Physical VLSI Design
More informationCMOS Digital Integrated Circuits Lec 10 Combinational CMOS Logic Circuits
Lec 10 Combinational CMOS Logic Circuits 1 Combinational vs. Sequential Logic In Combinational Logic circuit Out In Combinational Logic circuit Out State Combinational The output is determined only by
More informationBitSliced Design. EECS 141 F01 Arithmetic Circuits. A Generic Digital Processor. FullAdder. The Binary Adder
itliced Design Control EEC 141 F01 rithmetic Circuits DataIn Register dder hifter it 3 it 2 it 1 it 0 DataOut Tile identical processing elements Generic Digital Processor Fulldder MEMORY Cin Full adder
More informationVLSI GATE LEVEL DESIGN UNIT  III P.VIDYA SAGAR ( ASSOCIATE PROFESSOR) Department of Electronics and Communication Engineering, VBIT
VLSI UNIT  III GATE LEVEL DESIGN P.VIDYA SAGAR ( ASSOCIATE PROFESSOR) contents GATE LEVEL DESIGN : Logic Gates and Other complex gates, Switch logic, Alternate gate circuits, Time Delays, Driving large
More informationDynamic operation 20
Dynamic operation 20 A simple model for the propagation delay Symmetric inverter (rise and fall delays are identical) otal capacitance is linear t p Minimum length devices R W C L t = 0.69R C = p W L 0.69
More informationDC and Transient. Courtesy of Dr. Daehyun Dr. Dr. Shmuel and Dr.
DC and Transient Courtesy of Dr. Daehyun Lim@WSU, Dr. Harris@HMC, Dr. Shmuel Wimer@BIU and Dr. Choi@PSU http://csce.uark.edu +1 (479) 575604 yrpeng@uark.edu Pass Transistors We have assumed source is
More informationProperties of CMOS Gates Snapshot
MOS logic 1 Properties of MOS Gates Snapshot High noise margins: V OH and V OL are at V DD and GND, respectively. No static power consumption: There never exists a direct path between V DD and V SS (GND)
More informationDigital Microelectronic Circuits ( ) Logical Effort. Lecture 7: Presented by: Adam Teman
Digital Microelectronic ircuits (36113021 ) Presented by: Adam Teman Lecture 7: Logical Effort Digital Microelectronic ircuits The VLSI Systems enter  BGU Lecture 7: Logical Effort 1 Last Lectures The
More informationECE 425 Midterm Overview. Fall 2017
ECE 425 Midterm Overview Fall 2017 Overview q Midterm (20% of total grade) Oct 24 th 3:305:00pm in class q Materials Lecture 1 through 11 MP0, MP1 HW1, HW2 Practice exam q Rules 1 page of cheat sheet,
More informationUNIVERSITY OF CALIFORNIA, BERKELEY College of Engineering Department of Electrical Engineering and Computer Sciences
UNIVERSITY OF CALIFORNIA, BERKELEY College of Engineering Department of Electrical Engineering and Computer Sciences Elad Alon Homework #9 EECS141 PROBLEM 1: TIMING Consider the simple state machine shown
More informationDigital Microelectronic Circuits ( )
Digital Microelectronic ircuits (36113021 ) Presented by: Dr. Alex Fish Lecture 5: Parasitic apacitance and Driving a Load 1 Motivation Thus far, we have learned how to model our essential building block,
More informationUniversity of Toronto. Final Exam
University of Toronto Final Exam Date  Apr 18, 011 Duration:.5 hrs ECE334 Digital Electronics Lecturer  D. Johns ANSWER QUESTIONS ON THESE SHEETS USING BACKS IF NECESSARY 1. Equation sheet is on last
More informationEE 560 CHIP INPUT AND OUTPUT (I/0) CIRCUITS. Kenneth R. Laker, University of Pennsylvania
1 EE 560 CHIP INPUT AND OUTPUT (I/0) CIRCUITS 2 > ESD PROTECTION CIRCUITS (INPUT PADS) > ONCHIP CLOCK GENERATION & DISTRIBUTION > OUTPUT PADS > ONCHIP NOISE DUE TO PARASITIC INDUCTANCE > SUPER BUFFER
More informationDigital Integrated Circuits A Design Perspective
igital Integrated Circuits esign Perspective esigning Combinational Logic Circuits 1 Combinational vs. Sequential Logic In Combinational Logic Circuit Out In Combinational Logic Circuit Out State Combinational
More informationEE141Microelettronica. CMOS Logic
Microelettronica CMOS Logic CMOS logic Power consumption in CMOS logic gates Where Does Power Go in CMOS? Dynamic Power Consumption Charging and Discharging Capacitors Short Circuit Currents Short Circuit
More informationMiscellaneous Lecture topics. Mary Jane Irwin [Adapted from Rabaey s Digital Integrated Circuits, 2002, J. Rabaey et al.]
Miscellaneous Lecture topics Mary Jane Irwin [dapted from Rabaey s Digital Integrated Circuits, 2002, J. Rabaey et al.] MOS Switches MOS transistors can be viewed as simple switches. In an NSwitch, the
More informationLogical Effort EE141
Logical Effort 1 Question #1 How to best combine logic and drive for a big capacitive load? C L C L 2 Question #2 All of these are decoders Which one is best? 3 Method to answer both of these questions
More informationLogic effort and gate sizing
EEN454 Dgtal Integrated rcut Desgn Logc effort and gate szng EEN 454 Introducton hp desgners face a bewlderng arra of choces What s the best crcut topolog for a functon? How man stages of logc gve least
More informationEECS 270 Midterm 2 Exam Answer Key Winter 2017
EES 270 Midterm 2 Exam nswer Key Winter 2017 Name: unique name: Sign the honor code: I have neither given nor received aid on this exam nor observed anyone else doing so. NOTES: 1. This part of the exam
More informationDesigning Information Devices and Systems II Fall 2017 Miki Lustig and Michel Maharbiz Homework 1. This homework is due September 5, 2017, at 11:59AM.
EECS 16 Designing Information Devices and Systems II Fall 017 Miki Lustig and Michel Maharbiz Homework 1 This homework is due September 5, 017, at 11:59M. 1. Fundamental Theorem of Solutions to Differential
More informationEE 466/586 VLSI Design. Partha Pande School of EECS Washington State University
EE 466/586 VLSI Design Partha Pande School of EECS Washington State University pande@eecs.wsu.edu Lecture 9 Propagation delay Power and delay Tradeoffs Follow board notes Propagation Delay Switching Time
More informationDC & Transient Responses
ECEN454 Digital Integrated Circuit Design DC & Transient Responses ECEN 454 DC Response DC Response: vs. for a gate Ex: Inverter When = > = When = > = In between, depends on transistor size and current
More informationEE115C Digital Electronic Circuits Homework #4
EE115 Digital Electronic ircuits Homework #4 Problem 1 Power Dissipation Solution Vdd =1.0V onsider the source follower circuit used to drive a load L =20fF shown above. M1 and M2 are both NMOS transistors
More informationCMPEN 411 VLSI Digital Circuits Spring 2012 Lecture 17: Dynamic Sequential Circuits And Timing Issues
CMPEN 411 VLSI Digital Circuits Spring 2012 Lecture 17: Dynamic Sequential Circuits And Timing Issues [Adapted from Rabaey s Digital Integrated Circuits, Second Edition, 2003 J. Rabaey, A. Chandrakasan,
More informationand V DS V GS V T (the saturation region) I DS = k 2 (V GS V T )2 (1+ V DS )
ECE 4420 Spring 2005 Page 1 FINAL EXAMINATION NAME SCORE /100 Problem 1O 2 3 4 5 6 7 Sum Points INSTRUCTIONS: This exam is closed book. You are permitted four sheets of notes (three of which are your sheets
More informationFor smaller NRE cost For faster time to market For smaller highvolume manufacturing cost For higher performance
University of California at Berkeley College of Engineering Department of Electrical Engineering and Computer Sciences EECS5 J. Wawrzynek Spring 22 2/22/2. [2 pts] Short Answers. Midterm Exam I a) [2 pts]
More informationCOMBINATIONAL LOGIC. Combinational Logic
COMINTIONL LOGIC Overview Static CMOS Conventional Static CMOS Logic Ratioed Logic Pass Transistor/Transmission Gate Logic Dynamic CMOS Logic Domino npcmos Combinational vs. Sequential Logic In Logic
More informationEE371  Advanced VLSI Circuit Design
EE371  Advanced VLSI Circuit Design Midterm Examination May 1999 Name: No. Points Score 1. 20 2. 24 3. 26 4. 20 TOTAL / 90 In recognition of and in the spirit of the Stanford University Honor Code, I
More informationCOMP 103. Lecture 16. Dynamic Logic
COMP 03 Lecture 6 Dynamic Logic Reading: 6.3, 6.4 [ll lecture notes are adapted from Mary Jane Irwin, Penn State, which were adapted from Rabaey s Digital Integrated Circuits, 2002, J. Rabaey et al.] COMP03
More informationTHE INVERTER. Inverter
THE INVERTER DIGITAL GATES Fundamental Parameters Functionality Reliability, Robustness Area Performance» Speed (delay)» Power Consumption» Energy Noise in Digital Integrated Circuits v(t) V DD i(t) (a)
More information! Dynamic Characteristics. " Delay
EE 57: Digital Integrated ircuits and LI Fundamentals Lecture Outline! Dynamic haracteristics " Delay Lec : February, 8 MO Inverter and Interconnect Delay 3 Review: Propogation Delay Definitions Dynamic
More informationCMOS logic gates. João Canas Ferreira. March University of Porto Faculty of Engineering
CMOS logic gates João Canas Ferreira University of Porto Faculty of Engineering March 2016 Topics 1 General structure 2 General properties 3 Cell layout João Canas Ferreira (FEUP) CMOS logic gates March
More informationEE115C Winter 2017 Digital Electronic Circuits. Lecture 19: Timing Analysis
EE115C Winter 2017 Digital Electronic Circuits Lecture 19: Timing Analysis Outline Timing parameters Clock nonidealities (skew and jitter) Impact of Clk skew on timing Impact of Clk jitter on timing Flipflop
More informationEECS 312: Digital Integrated Circuits Final Exam Solutions 23 April 2009
Signature: EECS 312: Digital Integrated Circuits Final Exam Solutions 23 April 2009 Robert Dick Show your work. Derivations are required for credit; end results are insufficient. Closed book. You may use
More informationMOS Transistor Theory
CHAPTER 3 MOS Transistor Theory Outline 2 1. Introduction 2. Ideal IV Characteristics 3. Nonideal IV Effects 4. CV Characteristics 5. DC Transfer Characteristics 6. Switchlevel RC Delay Models MOS
More informationHomework Assignment #1 Solutions EE 477 Spring 2017 Professor Parker
Homework Assignment #1 Solutions EE 477 Spring 2017 Professor Parker Note: + implies OR,. implies AND, ~ implies NOT Question 1: a) (4%) Use transmission gates to design a 3input OR gate Note: There are
More informationEE241  Spring 2000 Advanced Digital Integrated Circuits. Announcements
EE241  Spring 2000 Advanced Digital Integrated Circuits Lecture 3 Circuit Optimization for Speed Announcements Tu 2/8/00 class will be pretaped on Friday, 2/4, 45:30 203 McLaughlin Class notes are available
More informationWARM SRAM: A Novel Scheme to Reduce Static Leakage Energy in SRAM Arrays
WARM SRAM: A Novel Scheme to Reduce Static Leakage Energy in SRAM Arrays Mahadevan Gomathisankaran Iowa State University gmdev@iastate.edu Akhilesh Tyagi Iowa State University tyagi@iastate.edu ➀ Introduction
More information