Digital Microelectronic Circuits ( ) Logical Effort. Lecture 7: Presented by: Adam Teman

Transcription

1 Digital Microelectronic ircuits ( ) Presented by: Adam Teman Lecture 7: Logical Effort Digital Microelectronic ircuits The VLSI Systems enter - BGU Lecture 7: Logical Effort 1

2 Last Lectures The MOS Inverter» Delay alculation» Driving a Load MOS Digital Logic» Dealing with High Fan-In Digital Microelectronic ircuits The VLSI Systems enter - BGU Lecture 7: Logical Effort 2

3 This Lecture So we learned how to drive a large load with a chain of erters. But what if there is logic to be calculated along the way? How should we distribute the logic in order to optimally drive the load? an we develop a methodology for designing a logical network? Digital Microelectronic ircuits The VLSI Systems enter - BGU Lecture 7: Logical Effort 3

4 Design Technique Question We need to implement an 8-input decoder: F = ABDEFGH Which implementation is best? Digital Microelectronic ircuits The VLSI Systems enter - BGU Lecture 7: Logical Effort 4

5 Design Technique Question 2 Is it better to drive a big capacitive load directly with the NAND gate or after some buffering? L L Method to answer both of these questions:»logical Effort This is an extension of the buffer sizing problem 5 Digital Microelectronic ircuits The VLSI Systems enter - BGU Lecture 7: Logical Effort

6 Reminder: Inverter with Load We saw that the delay increases with ratio of load to erter size: t t p p0 1 f t p0 is the intrinsic delay of an unloaded erter. γ is a technology dependent ratio. f is the Effective Fanout ratio of load to erter size Digital Microelectronic ircuits The VLSI Systems enter - BGU Lecture 7: Logical Effort 6

7 Reminder: Inverter with Load For easier equations, we will rewrite this a bit t p tp0 0.69Rout in t p t p f For a chain of erters, we get: Digital Microelectronic ircuits The VLSI Systems enter - BGU Lecture 7: Logical Effort 7

8 An Optimal (reference) Inverter Digital Microelectronic ircuits The VLSI Systems enter - BGU Lecture 7: Logical Effort 8

9 Now, lets look at a NAND Gate We will take a NAND gate sized for equal resistance to an optimal erter. We notice that: g, A g, B g,min g, 6 3 out, NAND d,min out, d,min Let us write the delay of the NAND: t 0.69R 0.69R p, NAND NAND out out, NAND Load Digital Microelectronic ircuits The VLSI Systems enter - BGU Lecture 7: Logical Effort 9

10 Now, lets look at a NAND Gate out, NAND d,min 6 3 out, d,min g, g, NAND t 0.69 R, t t 0.69R p, NAND out, NAND L p0 out, p, t 6 3 p0 d,min L 0.69R d,min g, t p, 2 t p0 d,min out, g, g,min t 4 3 out, out, NAND L p, f 2 out, out, 3 4 L g, NAND Digital Microelectronic ircuits The VLSI Systems enter - BGU Lecture 7: Logical Effort 10

11 Now, lets look at a NAND Gate We arrived at: 4 t p, NAND t p, 2 f 3 Two onclusions:» The intrinsic (unloaded) delay is twice that of an erter.» The fanout increases the delay at a faster pace than an erter. It is better to drive a load with an erter than a NAND! Digital Microelectronic ircuits The VLSI Systems enter - BGU Lecture 7: Logical Effort 11

12 How about a NOR Gate? We take an optimal NOR: 4 11 out, NOR d,min 3 out, d,min 2 g, NOR g, 5 3 Using the same steps, we arrive at: out, NOR g, NOR t p, NOR t p, f out, g, t p, f A NOR gate is less efficient than a NAND at driving a load! Digital Microelectronic ircuits The VLSI Systems enter - BGU Lecture 7: Logical Effort 12

13 Logical Effort We can generalize the delay to be: t t p LE f p p,» p intrinsic delay (~proportional to Fan In)» LE Logical Effort» f Electrical Effort» EF=LExf Effective Fanout» LE()=1 p()=1 Digital Microelectronic ircuits The VLSI Systems enter - BGU Lecture 7: Logical Effort 13

14 To summarize: Logical Effort» The logical effort of a gate describes how much effort we need to perform a logic calculation.» An Inverter has the smallest logical effort and intrinsic delay of all static MOS gates.» Logical Effort increases with gate complexity. Digital Microelectronic ircuits The VLSI Systems enter - BGU Lecture 7: Logical Effort 14

15 t 0.69R pd gate d, gate Load t p, 0.69R d, Generalization of LE R 0.69R d, gate d, gate Load R d, t R R gate gate p, d, gate Load R d, R d, p R, R gate d, gate d, d, g, R 1 gate g, gate t p, p Load R g, g, gate LE R, f R gate g, gate Load g, g, gate p, t p LE f Digital Microelectronic ircuits The VLSI Systems enter - BGU Lecture 7: Logical Effort 15

16 Generalization of LE t t p LE f pd p, p R R LE R R gate d, gate gate g, gate d, g, Digital Microelectronic ircuits The VLSI Systems enter - BGU Lecture 7: Logical Effort 16

17 pd p, Logical Effort Methodology t t p LE f,, We don t like the resistance factor in the expressions for p and LE. R R LE R R gate d gate gate g gate d, g, Therefore, first size the gate so the resistance is equivalent to an optimal erter. Now just find the ratio of capacitances to an optimal erter! p Digital Microelectronic ircuits The VLSI Systems enter - BGU Lecture 7: Logical Effort 17

18 LE of a NAND Gate p R R LE R R gate d, gate gate g, gate d, g, Digital Microelectronic ircuits The VLSI Systems enter - BGU Lecture 7: Logical Effort 18

19 LE of a NOR Gate p R R LE R R gate d, gate gate g, gate d, g, Digital Microelectronic ircuits The VLSI Systems enter - BGU Lecture 7: Logical Effort 19

20 Logical Effort of Gates t t p LE f p p, p R R LE R R gate d, gate gate g, gate d, g, Digital Microelectronic ircuits The VLSI Systems enter - BGU Lecture 7: Logical Effort 20

21 What happens with higher Fan-In? A three-input NAND gate: LE NAND n 3 2 A three-input NOR gate: LE NOR 2n 1 3 Digital Microelectronic ircuits The VLSI Systems enter - BGU Lecture 7: Logical Effort 21

22 Last Lecture The method of Logical Effort: t t p LE f p p, p R R gate d, gate d, LE R R gate g, gate g, Digital Microelectronic ircuits The VLSI Systems enter - BGU Lecture 7: Logical Effort 22

23 Add Branching Effort What happens if a node branches off? b L,on-path L,on-path L,off-path L, total L,on-path Digital Microelectronic ircuits The VLSI Systems enter - BGU Lecture 7: Logical Effort 23

24 ascading gates into a Path N, t t p LE f b p p i i i i i1 Let s give a few things names» Stage Electrical Effort» Path Electrical Fanout» Path Logical Effort» Path Branching Effort» Path Effort EFi LEi fi bi LEi out F in LE LE LE LE N B b... 1b2 bn PE F LE B out, i in, i b i Digital Microelectronic ircuits The VLSI Systems enter - BGU Lecture 7: Logical Effort 24

25 ascading gates into a Path N, t t p LE f b p p i i i i i1 Using the same approach as before, we can find the minimal delay. The solution, again, is that the electrical effort should be equal between stages, so we get: i N N EF PE F LE B Digital Microelectronic ircuits The VLSI Systems enter - BGU Lecture 7: Logical Effort 25

26 Optimal Number of Stages We now have a delay equation: N t p N PE pi We can find the optimal number of stages. Again we get EF opt =4 (3.6 with γ=1) Digital Microelectronic ircuits The VLSI Systems enter - BGU Lecture 7: Logical Effort 26

27 Summary Method of Logical Effort ompute the Path Effort: PE F LE B Find the optimal number of stages: N log 3.6 PE ompute the Effective Fanout: (identical for all stages) EF N PE Find sizes of each stage: EFi LEi fi LEi out, i in, i b i in, i LE i out, i EF b i Digital Microelectronic ircuits The VLSI Systems enter - BGU Lecture 7: Logical Effort 27

28 Example Given the following network with» in,1 =» Size of Y and Z equal for all gates at the same stage. Size the gates optimally for the red path. F 9 9, LE b 2, 3, 1 b 6 1 Y b 1 Z B 1 PE EF LbZ Z LEZ 2.38 EF Z by Y LEY 1.89 EF Y b LE EF Digital Microelectronic ircuits The VLSI Systems enter - BGU Lecture 7: Logical Effort SANITY HEK!!! in, i LE i out, i bi EF 28