EE241 - Spring 2000 Advanced Digital Integrated Circuits. Announcements
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1 EE241 - Spring 2000 Advanced Digital Integrated Circuits Lecture 3 Circuit Optimization for Speed Announcements Tu 2/8/00 class will be pre-taped on Friday, 2/4, 4-5: McLaughlin Class notes are available in the morning before the class on the Web ISSCC preview seminars:» Fri 1/28, 2-5pm, 531 Cory (Hogan Rm) - 5 speakers from Stanford» Tue 2/1 3:30-5:30pm, 531 Cory 4 speakers from Philips» Thu 2/ Cory 2 speakers from UC Davis 1
2 Static CMOS Delay Intrinsic logic delay» From internal R, C = constant RC delay of the load» Fan-out» Wire RC For a given gate, delay is a function of:» Load» Input rise time(s)» Intrinsic delay Delay model application: intrinsic delay 2C D +C G Close to Shoji 2
3 Delay dependence on inputs V DD R P R P 3.0 A = B = 1 0 A R N B B F C L A = 1, B = 1 0 A = 1 0, B =1 R N A C int time, ps Optimizing the intrinsic RC delay 3
4 Progressive Sizing Uniform versus progressive sizing Uniform k n-1 Non-uniform 1 N k n-1 k k 2 k n-1 4
5 Sizing models Case study 5
6 Example: Progressive Scaling of NMOS Devices in DOMINO CMOS What if External Capacitance is Dominant? Divide and Conquer! 6
7 Divide and Conquer In 1 u u 2 u N-1 Out Ci C1 C2 C L u opt = e t p as a function of u and x 60.0 u/ln(u) 40.0 x=10,000 x= x=100 x= u 7
8 Adding Intrinsic Load Optimum Tapering Factor for Realistic Load 5 4 u opt α = gγ 8
9 Tapering Factor for Realistic Load Effect of Rise/Fall Times 9
10 Effect of Rise/Fall Times Negative Delay? 10
11 Impact of Rise and Fall Times Impact of Termination m f N k o k o k1 C L 11
12 Required Number of Buffer Stages What about power consumption (and area)? 12
13 Delay versus Area and Power Optimizing t p versus t r /t f 13
14 Problem: Ground Bounce Sizing in Presence of Noise 14
15 RC-line delay O mm 0.35 µm process minimum width wires r = 0.12 Ω/µm c = 0.16 ff/µm τ = fs/µm2 1O mm Waveforms for 10 mm RC Line: tp = 750 psec Delay and Rise Times for a 10 mm line Simulation Results Analytically: t d = 0.4 d 2 RC t r = d 2 RC 15
16 Repeaters Optimum repetition rate t d = (l/l s )2t b For 0.35 mm tech. l s = 3.5 mm n = 17.5 mm/ns Increasing Wire Width and Spacing Reduces impact of fringing capacitance and capacitance to neighboring wires 16
17 Overdrive of Low-Swing RC Lines 300 mv signal 1.5 V overdrive 750 ps -> 350 ps Bipolar Overdrive Signaling Issues: Crosstalk Delay still quadratic with respect to length 17
18 Impact of wire-delay on highperformance design Critical Path Delay Model (Phil Fischer - Sematech) L net 1 2 N Global Wire L Edge t d stage t d global = t d inv + t d Edge t d cycle = N * t d stage + t d global t d = R o (C out + f.o.c g in ) + R o (C w ) + 0.4(C w R w t of 1.6 ) 1/ R w C g in Transistor and Interconnect Parameters Parameter 250nm 180nm 150nm 130nm 100nm 70nm 50nm Wint M1-2 local (nm) Hint M1-2 local (nm) Pitchw M1-2 local (nm) tins M1-2 local (nm) Wint M semi-global (nm) 500 Hint M semi-global (nm) 900 Pitchw M semi-global (nm) tins M semi-global (nm) 900 Wint M global (nm) 2000 Hint M global (nm) 2000 Pitchw M global(nm) tins M global (nm) 1400 Chip area (cm 2 ) Vdd (V) Metal Levels Metal resistivity (µohm-cm) Relative dielectric constant Transistors: Equivalent tox (nm) In nominal (µa/µm) Ip nominal (µa/µm)
19 NAND Gate Stage Delay (with scaled local interconnect, fi = fo = 3) 140 Source: P. Fischer Stage delay Delay (ps) Gate delay Wire delay Technology Min. Feature (nm) For future Cu-low k High-Performance Microprocessor Clock Freq. (MHz) Cu-Low k Al-Low k Cu-SiO 2 Al-SiO Technology Min. Feature (nm) Logic Depth = 12 Gates 19
20 Clock-Cycle Model Summary Parameter 250nm 180nm 150nm 130nm 100nm 70nm 50nm L net Logic wire CP ( µm) Cint M1 (pf/cm) Cint 2µm M global (pf/cm) Rint M1 (Kohm/cm) Rint 2µm M global (ohm/cm) tof (ps/cm) L edge (cm) td-global (ps) td-gates Logic D=12 (ps) td-cycle Model (ps) tcycle time (ps) Ratio (td-cycle/t cycle time) High Perf. Clock, mp (MHz) Rounded Clock, mp (MHz) Cost - Performance (D=25) Cost Perf. Clock, mp (MHz) Rounded Clock, mp (MHz) Wn Output ( µm) Logic Area (cm 2 ) Ng 1.00E E E E E E E+07 Ntr Logic 6.00E E E E E E E+08 Rules of Thumb Keep the fan-in less than 3 Keep the fan-out less than 5 Same delays of gates in the critical path Same rise/fall times Size the transistors to drive the interconnect 20
21 Logical Effort Designing for speed on the Back of an Envelope Sutherland, Sproull, ARVLSI 91 Sutherland, Sproull, Harris, Morgan-Kaufman 99 A simple method for manual sizing of logic gates: simple delay model transistor sizes number of stages Expanding the sizing rules of inverters to complex logic gates Delay Model Normalized delay (d) t pnand tpinv F(Fan-in) Fan-out 21
22 Delay in a Logic Gate Gate delay: d = f + p effort delay parasitic delay Effort delay: f = g h logical effort electrical effort = C out /C in Logical effort is a function of topology, independent of sizing Electrical effort is a function of load/gate size Logical Effort Logical effort is the ratio of input capacitance of a gate to the input capacitance of an inverter with the same output current g = 1 g = 4/3 g = 5/3 22
23 Logical Effort Example 8-input AND 23
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