# CPE/EE 427, CPE 527 VLSI Design I L18: Circuit Families. Outline

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1 CPE/EE 47, CPE 57 VLI Design I L8: Circuit Families Department of Electrical and Computer Engineering University of labama in Huntsville leksandar Milenkovic ( ) Outline Pseudo-nMO Logic Dynamic Logic Pass Transistor Logic 0/4/005 VLI Design I;. Milenkovic VLI Design I;. Milenkovic

2 Introduction What makes a circuit fast? I C dv/dt -> t pd (C/I) V low capacitance high current small swing 4 Logical effort is proportional to C/I 4 pmo are the enemy! High capacitance for a given current Can we take the pmo capacitance off the input? Various circuit families try to do this 0/4/005 VLI Design I;. Milenkovic 3 Pseudo-nMO In the old days, nmo processes had no pmo Instead, use pull-up transistor that is always ON In CMO, use a pmo that is always ON Ratio issue Make pmo about ¼ effective strength of pulldown network.8 load I ds P/.5. V out 0.9 P 4 V out V in 6/ P 4 P V in 0/4/005 VLI Design I;. Milenkovic 4 VLI Design I;. Milenkovic

3 Pseudo-nMO Gates Design for unit current on output to compare with unit inverter. pmo fights nmo inputs f Inverter NND NOR g u g d g avg p u p d p avg g u g d g avg p u p d p avg g u g d g avg p u p d p avg 0/4/005 VLI Design I;. Milenkovic 5 Pseudo-nMO Gates Design for unit current on output to compare with unit inverter. pmo fights nmo inputs f Inverter NND NOR /3 4/3 g u g d g avg p u p d p avg /3 8/3 8/3 g u g d g avg p u p d p avg /3 4/3 4/3 g u g d g avg p u p d p avg 0/4/005 VLI Design I;. Milenkovic 6 VLI Design I;. Milenkovic 3

4 Pseudo-nMO Gates Design for unit current on output to compare with unit inverter. pmo fights nmo inputs f Inverter NND NOR /3 4/3 g u 4/3 g d 4/9 g avg 8/9 p u p d p avg /3 8/3 8/3 g u 8/3 g d 8/9 g avg 6/9 p u p d p avg /3 4/3 4/3 g u 4/3 g d 4/9 g avg 8/9 p u p d p avg 0/4/005 VLI Design I;. Milenkovic 7 Pseudo-nMO Gates Design for unit current on output to compare with unit inverter. pmo fights nmo inputs f Inverter NND NOR /3 4/3 g u 4/3 g d 4/9 g avg 8/9 p u 6/3 p d 6/9 p avg /9 /3 8/3 8/3 g u 8/3 g d 8/9 g avg 6/9 p u 0/3 p d 0/9 p avg 0/9 /3 4/3 4/3 g u 4/3 g d 4/9 g avg 8/9 p u 0/3 p d 0/9 p avg 0/9 0/4/005 VLI Design I;. Milenkovic 8 VLI Design I;. Milenkovic 4

5 Pseudo-nMO Design Ex: Design a k-input ND gate using pseudonmo. Estimate the delay driving a fanout of H G F P N D In In k Pseudo-nMO H 0/4/005 VLI Design I;. Milenkovic 9 Pseudo-nMO Design Ex: Design a k-input ND gate using pseudonmo. Estimate the delay driving a fanout of H G * 8/9 8/9 F GH 8H/9 P + (4+8k)/9 (8k+3)/9 N D NF /N + P 4 H 8k In In k Pseudo-nMO H 0/4/005 VLI Design I;. Milenkovic 0 VLI Design I;. Milenkovic 5

6 Pseudo-nMO Power Pseudo-nMO draws power whenever 0 Called static power P I V DD few m / gate * M gates would be a problem This is why nmo went extinct! Use pseudo-nmo sparingly for wide NORs Turn off pmo when not in use en C 0/4/005 VLI Design I;. Milenkovic Dynamic Logic Dynamic gates uses a clocked pmo pullup Two modes: precharge and evaluate /3 4/3 tatic Pseudo-nMO Dynamic Precharge Evaluate Precharge 0/4/005 VLI Design I;. Milenkovic VLI Design I;. Milenkovic 6

7 The Foot What if pulldown network is ON during precharge? Use series evaluation transistor to prevent fight. precharge transistor inputs f inputs f foot footed unfooted 0/4/005 VLI Design I;. Milenkovic 3 Logical Effort Inverter NND NOR unfooted g d p d g d p d g d p d footed 3 3 g d g d p d 3 p d g d p d 0/4/005 VLI Design I;. Milenkovic 4 VLI Design I;. Milenkovic 7

8 Logical Effort Inverter NND NOR unfooted g d /3 p d /3 g d /3 p d 3/3 g d /3 p d 3/3 footed 3 3 g d /3 g d 3/3 p d 3/3 3 p d 4/3 g d /3 p d 5/3 0/4/005 VLI Design I;. Milenkovic 5 Monotonicity Dynamic gates require monotonically rising inputs during evaluation 0 -> 0 0 -> -> ut not -> 0 violates monotonicity during evaluation Precharge Evaluate Precharge Output should rise but does not 0/4/005 VLI Design I;. Milenkovic 6 VLI Design I;. Milenkovic 8

9 Monotonicity Woes ut dynamic gates produce monotonically falling outputs during evaluation Illegal for one dynamic gate to drive another! X Precharge Evaluate X Precharge 0/4/005 VLI Design I;. Milenkovic 7 Monotonicity Woes ut dynamic gates produce monotonically falling outputs during evaluation Illegal for one dynamic gate to drive another! X Precharge Evaluate X Precharge X monotonically falls during evaluation should rise but cannot 0/4/005 VLI Design I;. Milenkovic 8 VLI Design I;. Milenkovic 9

10 Domino Gates Follow dynamic stage with inverting static gate Dynamic / static pair is called domino gate Produces monotonic outputs domino ND Precharge Evaluate W Precharge W X Z C X Z dynamic NND static inverter W X H C H X Z C Z 0/4/005 VLI Design I;. Milenkovic 9 Domino Optimizations Each domino gate triggers next one, like a string of dominos toppling over Gates evaluate sequentially but precharge in parallel Thus evaluation is more critical than precharge HI-skewed static stages can perform logic 0 D0 D D 3 D3 H 4 D4 5 D5 6 D6 7 D7 0/4/005 VLI Design I;. Milenkovic 0 VLI Design I;. Milenkovic 0

11 Dual-Rail Domino Domino only performs noninverting functions: ND, OR but not NND, NOR, or XOR Dual-rail domino solves this problem Takes true and complementary inputs Produces true and complementary outputs sig_h 0 0 sig_l 0 0 Meaning Precharg 0 ed invalid _l inputs f f _h 0/4/005 VLI Design I;. Milenkovic Example: ND/NND Given _h, _l, _h, _l Compute _h *, _l ~( * ) 0/4/005 VLI Design I;. Milenkovic VLI Design I;. Milenkovic

12 Example: ND/NND Given _h, _l, _h, _l Compute _h *, _l ~( * ) Pulldown networks are conduction complements _l * _h _h * _l _l _h 0/4/005 VLI Design I;. Milenkovic 3 Example: XOR/XNOR ometimes possible to share transistors _l xnor _h _l _l _h _h xor _l _h 0/4/005 VLI Design I;. Milenkovic 4 VLI Design I;. Milenkovic

13 Leakage Dynamic node floats high during evaluation Transistors are leaky (I OFF 0) Dynamic value will leak away over time Formerly miliseconds, now nanoseconds! Use keeper to hold dynamic node Must be weak enough not to fight evaluation weak keeper k X H 0/4/005 VLI Design I;. Milenkovic 5 Charge haring Dynamic gates suffer from charge sharing 0 x C x C x 0/4/005 VLI Design I;. Milenkovic 6 VLI Design I;. Milenkovic 3

14 Charge haring Dynamic gates suffer from charge sharing 0 x C x C Charge sharing noise x V x V 0/4/005 VLI Design I;. Milenkovic 7 Charge haring Dynamic gates suffer from charge sharing 0 x C x C Charge sharing noise x C V V V x DD Cx + C 0/4/005 VLI Design I;. Milenkovic 8 VLI Design I;. Milenkovic 4

15 econdary Precharge olution: add secondary precharge transistors Typically need to precharge every other node ig load capacitance C helps as well x secondary precharge transistor 0/4/005 VLI Design I;. Milenkovic 9 Noise ensitivity Dynamic gates are very sensitive to noise Inputs: V IH V tn Outputs: floating output susceptible noise Noise sources Capacitive crosstalk Charge sharing Power supply noise Feedthrough noise nd more! 0/4/005 VLI Design I;. Milenkovic 30 VLI Design I;. Milenkovic 5

16 Domino ummary Domino logic is attractive for high-speed circuits.5 x faster than static CMO ut many challenges: Monotonicity Leakage Charge sharing Noise Widely used in high-performance microprocessors 0/4/005 VLI Design I;. Milenkovic 3 NMO Transistors in eries/parallel Primary inputs drive both gate and source/drain terminals NMO switch closes when the gate input is high X X if and X X if or Remember NMO transistors pass a strong 0 but a weak 0/4/005 VLI Design I;. Milenkovic 3 VLI Design I;. Milenkovic 6

17 PMO Transistors in eries/parallel Primary inputs drive both gate and source/drain terminals PMO switch closes when the gate input is low X X if and + X X if or Remember PMO transistors pass a strong but a weak 0 0/4/005 VLI Design I;. Milenkovic 33 Pass Transistor (PT) Logic 0 F 0 F Gate is static a low-impedance path exists to both supply rails under all circumstances N transistors instead of N No static power consumption Ratioless idirectional (versus undirectional) 0/4/005 VLI Design I;. Milenkovic 34 VLI Design I;. Milenkovic 7

18 VTC of PT ND Gate.5/ / / /0.5 F V out, V 0 V DD, 0 V DD V DD, 0 V DD 0 V DD 0 V in, V Pure PT logic is not regenerative - the signal gradually degrades after passing through a number of PTs (can fix with static CMO inverter insertion) 0/4/005 VLI Design I;. Milenkovic 35 NMO Only PT Driving an Inverter In V DD V x V G V V DD DD -V Tn D M M V x does not pull up to V DD, but V DD V Tn Threshold voltage drop causes static power consumption (M may be weakly conducting forming a path from V DD to GND) Notice V Tn increases of pass transistor due to body effect (V ) 0/4/005 VLI Design I;. Milenkovic 36 VLI Design I;. Milenkovic 8

19 Voltage wing of PT Driving an Inverter V DD In 0 V DD D 0.5/0.5 x.5/ /0.5 Out Voltage, V 3 0 Out In x.8v Time, ns ody effect large V at x - when pulling high ( is tied to GND and charged up close to V DD ) o the voltage drop is even worse V x V DD -(V Tn0 + γ( ( f + V x ) - f )) 0/4/005 VLI Design I;. Milenkovic 37 Cascaded NMO Only PTs V DD V DD G M C V DD x V DD -V Tn G y M V DD Out V DD C V DD M x M y Out wing on y V DD -V Tn -V Tn wing on y V DD -V Tn Pass transistor gates should never be cascaded as on the left Logic on the right suffers from static power dissipation and reduced noise margins 0/4/005 VLI Design I;. Milenkovic 38 VLI Design I;. Milenkovic 9

20 olution : Level Restorer Level Restorer M Out0 0 M n M r x 0 For correct operation M r must be sized correctly (ratioed) on off M Out Full swing on x (due to Level Restorer) so no static power consumption by inverter No static backward current path through Level Restorer and PT since Restorer is only active when is high 0/4/005 VLI Design I;. Milenkovic 39 Transient Level Restorer Circuit Response 3 W/L.50/0.5 W/L n 0.50/0.5 W/L 0.50/0.5 Voltage, V W/L r.75/0.5 W/L r.50/0.5 node x never goes below V M of inverter so output never switches 0 W/L r.0/0.5 W/L r.5/ Time, ps Restorer has speed and power impacts: increases the capacitance at x, slowing down the gate; increases t r (but decreases t f ) 0/4/005 VLI Design I;. Milenkovic 40 VLI Design I;. Milenkovic 0

21 olution : Multiple V T Transistors Technology solution: Use (near) zero V T devices for the NMO PTs to eliminate most of the threshold drop (body effect still in force preventing full swing to V DD ) low V T transistors In 0V.5V on Out In.5V off but leaking 0V sneak path Impacts static power consumption due to subthreshold currents flowing through the PTs (even if V G is below V T ) 0/4/005 VLI Design I;. Milenkovic 4 olution 3: Transmission Gates (TGs) Most widely used solution C C C C C GND C GND V DD GND C V DD C V DD Full swing bidirectional switch controlled by the gate signal C, if C 0/4/005 VLI Design I;. Milenkovic 4 VLI Design I;. Milenkovic

22 olution 3: Transmission Gates (TGs) Most widely used solution C C C C C GND C GND V DD GND C V DD C V DD Full swing bidirectional switch controlled by the gate signal C, if C 0/4/005 VLI Design I;. Milenkovic 43 Resistance of TG 30 5 R n W/L p 0.50/0.5 0V R p Resistance, kω R p.5v V out R n.5v R eq W/L n 0.50/ V out, V 0/4/005 VLI Design I;. Milenkovic 44 VLI Design I;. Milenkovic

23 Pass Transistor Circuits Use pass transistors like switches to do logic Inputs drive diffusion terminals as well as gates CMO + Transmission Gates: -input multiplexer Gates should be restoring 0/4/005 VLI Design I;. Milenkovic 45 TG Multiplexer F V DD In F In F!(In + In ) GND In In 0/4/005 VLI Design I;. Milenkovic 46 VLI Design I;. Milenkovic 3

24 Transmission Gate XOR 0/4/005 VLI Design I;. Milenkovic 47 Transmission Gate XOR weak 0 if! 0 on off on off!! weak if an inverter 0/4/005 VLI Design I;. Milenkovic 48 VLI Design I;. Milenkovic 4

25 TG Full dder C in um C out 0/4/005 VLI Design I;. Milenkovic 49 Differential TG Logic (DPL) GND F F GND V DD F F V DD ND/NND XOR/XNOR 0/4/005 VLI Design I;. Milenkovic 50 VLI Design I;. Milenkovic 5

26 CPL Complementary Pass-transistor Logic Dual-rail form of pass transistor logic voids need for ratioed feedback Optional cross-coupling for rail-to-rail swing L L 0/4/005 VLI Design I;. Milenkovic 5 Differential PT Logic (CPL) PT Network F F Inverse PT Network F F F F+ F ND/NND F OR/NOR F+ XOR/XNOR F 0/4/005 VLI Design I;. Milenkovic 5 VLI Design I;. Milenkovic 6

27 CPL Properties Differential so complementary data inputs and outputs are always available (so don t need extra inverters) till static, since the output defining nodes are always tied to V DD or GND through a low resistance path Design is modular; all gates use the same topology, only the inputs are permuted. imple XOR makes it attractive for structures like adders Fast (assuming number of transistors in series is small) dditional routing overhead for complementary signals till have static power dissipation problems 0/4/005 VLI Design I;. Milenkovic 53 CPL Full dder C in C in!um um C in C in C in C in!c out C out 0/4/005 VLI Design I;. Milenkovic 54 VLI Design I;. Milenkovic 7

28 CPL Full dder C in C in!um um C in C in C in C in!c out C out 0/4/005 VLI Design I;. Milenkovic 55 VLI Design I;. Milenkovic 8

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