7. Combinational Circuits
|
|
|
- Elfrieda Paul
- 6 years ago
- Views:
Transcription
1 7. Combinational Circuits Jacob Abraham Department of Electrical and Computer Engineering The University of Texas at Austin VLSI Design Fall 2017 September 25, 2017 ECE Department, University of Texas at Austin Lecture 7. Combinational Circuits Jacob Abraham, September 25, / 23
2 Review: Decoder Example, Number of Stages 16 word, (32 bit) register file Each bit presents load of 3 unit-sized transistors True and complementary address inputs A[3:0] Each input may drive 10 unit-sized transistors Find: number of stages, sizes of gates, speed Decoder effort is mainly electrical and branching Electrical Effort: H = (32*3)/10 = 9.6 Branching Effort: B = 8 If we neglect logical effort (assume G = 1) Path Effort: F = GBH = 76.8 Number of Stages: N = log 4 F = 3.1 Try a 3-stage design ECE Department, University of Texas at Austin Lecture 7. Combinational Circuits Jacob Abraham, September 25, / 23
3 Decoder Review: Gate Sizes and Delay Logical Effort: G = 1 * 6/3 * 1 = 2 Path Effort: F = GBH = 154 Stage Effort: ˆf = F 1 3 = 5.36 Path Delay: D = 3 ˆf = 22.1 Gate sizes: z = 96*1/5.36 = 18 Gate sizes: y = 18*2/5.36 = 6.7 ECE Department, University of Texas at Austin Lecture 7. Combinational Circuits Jacob Abraham, September 25, / 23
4 Decoder Review: Comparison Compare many alternatives with a spreadsheet Design N G P D NAND4-INV NAND2-NOR2 2 20/ INV-NAND4-INV NAND4-INV-INV-INV NAND2-NOR2-INV-INV 4 20/ NAND2-INV-NAND2-INV 4 16/ INV-NAND2-INV-NAND2-INV 5 16/ NAND2-INV-NAND2-INV-INV-INV 6 16/ ECE Department, University of Texas at Austin Lecture 7. Combinational Circuits Jacob Abraham, September 25, / 23
5 Review: Logical Effort Example Find the logical efforts for the inputs, a, b, and c in the circuit below. Output a b c Rising Falling Suggest a way to reduce the parasitic delay of this circuit by modifying the structure (but keeping the same function). ECE Department, University of Texas at Austin Lecture 7. Combinational Circuits Jacob Abraham, September 25, / 23
6 Example, Cont d Find the logical efforts for the inputs, a, b, and c in the circuit below. Output Rising Falling a 55/18 22/15 b 55/18 22/15 c 35/18 7/9 To reduce the parasitic delay of this circuit, swap the parallel combination of pmos transistors with inputs a, b with the pmos transistor with input c ECE Department, University of Texas at Austin Lecture 7. Combinational Circuits Jacob Abraham, September 25, / 23
7 Example: Sizing Paths Size the path G1-G2-G3-G4 in the circuit below using logical effort Find the minimum delay and give the sizes of the P and N transistors to achieve this delay Assume that the off-path capacitance is the same as the on-path capacitance for each branch Input capacitance of Inverter G1 = 3 units. Load capacitance driven by Gate G4 = 52 units. ECE Department, University of Texas at Austin Lecture 7. Combinational Circuits Jacob Abraham, September 25, / 23
8 Sizing Paths, Cont d Size the path G1-G2-G3-G4 in the circuit Input capacitance of Inverter G1 = 3 units. Load capacitance driven by Gate G4 = 52 units. Delay = 4.8 FO4 units Sizes of transistors: Gate P N Gate G4 8 8 Gate G3 5 5 Gate G2 3 3 Gate G1 2 1 Delay of the path from A through gates G5 and G4 (assuming the input from G2=1 and D=0): 2.08 FO4 units ECE Department, University of Texas at Austin Lecture 7. Combinational Circuits Jacob Abraham, September 25, / 23
9 Example of Bubble Pushing Implement the circuit described by the code below module mux(input s, d0, d1, output y); assign y = s? d1 : d0; endmodule The specifications are easily met with a design using AND, OR and NOT gates ECE Department, University of Texas at Austin Lecture 7. Combinational Circuits Jacob Abraham, September 25, / 23
10 Convert to Design using NAND/NOR/NOT Gates Bubble Pushing Start with network of AND/OR gates Convert to NAND/NOR + inverters Push bubbles around to simplify logic Use DeMorgan s Law ECE Department, University of Texas at Austin Lecture 7. Combinational Circuits Jacob Abraham, September 25, / 23
11 Example, Continued Now, design the circuit with one compound gate and one inverter. Assume that S is available CE Department, University of Texas at Austin Lecture 7. Combinational Circuits Jacob Abraham, September 25, / 23
12 Compound Gates ECE Department, University of Texas at Austin Lecture 7. Combinational Circuits Jacob Abraham, September 25, / 23
13 Another Example A multiplexer has a maximum input capacitance of 16 units on each input. It must drive a load of 160 units Estimate the delay of the NAND and compound gate designs NAND Solution Compound Solution H = 160/16 = 10 B = 1 N = 2 P = = 4 G = (4/3) (4/3) = 16/9 F = GBH = 160/9 ˆf = N F = 4.2 D = N ˆf + P = 12.4τ H = 160/16 = 10 B = 1 N = 2 P = = 5 G = (6/3) (1) = 2 F = GBH = 20 ˆf = N F = 4.5 D = N ˆf + P = 14τ CE Department, University of Texas at Austin Lecture 7. Combinational Circuits Jacob Abraham, September 25, / 23
14 Example, Cont d Annotate the designs for the multiplexer with transistor sizes which achieve the minimum delay ECE Department, University of Texas at Austin Lecture 7. Combinational Circuits Jacob Abraham, September 25, / 23
15 Order of Inputs to a Transistor Stack Delay of CMOS gate is affected by input order Parasitic delay model used in logical effort calculations is too simple Example, calculate parasitic delay for Y falling If A arrives latest: 2τ If B arrives latest: 2.33τ Choosing inner and outer inputs Outer input is closest to rail (power or ground): B Inner input is closest to output: A If input arrival time is known Connect latest arriving input to inner terminal ECE Department, University of Texas at Austin Lecture 7. Combinational Circuits Jacob Abraham, September 25, / 23
16 Asymmetric Gates Asymmetric gates favor one input over another Example, suppose input A of a NAND gate is most critical Use smaller transistor on A (less capacitance) Boost size of noncritical input So total resistance is same Calculate logical effort g A = 10/9 g B = 2 g total = g A + g B = 28/9 Symmetric gate approaches g = 1 on critical input However, total logical effort goes up CE Department, University of Texas at Austin Lecture 7. Combinational Circuits Jacob Abraham, September 25, / 23
17 Symmetric Gates Inputs can be made perfectly symmetric Make both A and B behave like inner/outer inputs, and keep the P:N ratio 2:1 ECE Department, University of Texas at Austin Lecture 7. Combinational Circuits Jacob Abraham, September 25, / 23
18 Skewed Gates Favor One Edge Over Another Example, suppose rising output of inverter is most critical Downsize noncritical nmos transistor Calculate logical effort by comparing to unskewed inverter with same effective resistance on that edge g u = 2.5/3 = 5/6; g d = 2.5/1.5 = 5/3 Definition: Logical effort of a skewed gate for a particular transition is the ratio of the input capacitance of that gate to the input capacitance of an unskewed inverter delivering the same output current for the same transition Skewed gates reduce size of noncritical transistors HI-skew gates favor rising output (small nmos) LO-skew gates favor falling output (small pmos) Logical effort is smaller for favored direction, but larger for the other direction ECE Department, University of Texas at Austin Lecture 7. Combinational Circuits Jacob Abraham, September 25, / 23
19 Catalog of Skewed Gates ECE Department, University of Texas at Austin Lecture 7. Combinational Circuits Jacob Abraham, September 25, / 23
20 Asymmetric Skew Combine asymmetric and skewed gates Downsize noncritical transistor on unimportant input Reduces parasitic delay for critical input ECE Department, University of Texas at Austin Lecture 7. Combinational Circuits Jacob Abraham, September 25, / 23
21 Example I Find the (worst case) logical efforts of the different inputs in the CMOS circuit below. ECE Department, University of Texas at Austin Lecture 7. Combinational Circuits Jacob Abraham, September 25, / 23
22 Example - II (a) Calculate the delay of the segment from B to S of the adder shown below (the AOI21 is a single stage, shown on the right), given that the output capacitance is 25 units (normalized), and the input capacitance at B is 6 units. ECE Department, University of Texas at Austin Lecture 7. Combinational Circuits Jacob Abraham, September 25, / 23
23 Example - II, Cont d (b) Calculate the capacitances of the nodes y, x and w, and the resulting widths of the transistors. ECE Department, University of Texas at Austin Lecture 7. Combinational Circuits Jacob Abraham, September 25, / 23
24 Best P/N Ratio We have selected P/N ratio for unit rise and fall resistance (µ = 2-3 for an inverter). Alternative: choose ratio for least average delay Example: inverter Delay driving identical inverter t pdf = (P + 1) t pdr = (P + 1)(µ/P ) t pd = (P + 1)(1 + µ/p )/2 = (P µ + µ/p )/2 Differentiating t pd w.r.t. P, we get, least delay for P = µ In general, best P/N ratio is sqrt of that giving equal delay Only improves average delay slightly for inverters But significantly decreases area and power CE Department, University of Texas at Austin Lecture 7. Combinational Circuits Jacob Abraham, September 25, / 23
Lecture 9: Combinational Circuit Design
Lecture 9: Combinational Circuit Design Outline Bubble Pushing Compound Gates Logical Effort Example Input Ordering symmetric Gates Skewed Gates Best P/N ratio 0: Combinational Circuits CMOS VLSI Design
Lecture 8: Combinational Circuits
Introduction to CMOS VLSI Design Lecture 8: Combinational Circuits David Harris Harvey Mudd College Spring 00 Outline ubble Pushing Compound Gates Logical Effort Example Input Ordering symmetric Gates
Lecture 8: Combinational Circuits
Introduction to CMOS VLSI Design Lecture 8: Combinational Circuits David Harris Harvey Mudd College Spring 004 Outline ubble Pushing Compound Gates Logical Effort Example Input Ordering symmetric Gates
Lecture 9: Combinational Circuits
Introduction to CMOS VLSI Design Lecture 9: Combinational Circuits David Harris, Harvey Mudd College Kartik Mohanram and Steven Levitan University of Pittsburgh Outline q ubble Pushing q Compound Gates
Static CMOS Circuits. Example 1
Static CMOS Circuits Conventional (ratio-less) static CMOS Covered so far Ratio-ed logic (depletion load, pseudo nmos) Pass transistor logic ECE 261 Krish Chakrabarty 1 Example 1 module mux(input s, d0,
Lecture 8: Logic Effort and Combinational Circuit Design
Lecture 8: Logic Effort and Combinational Circuit Design Slides courtesy of Deming Chen Slides based on the initial set from David Harris CMOS VLSI Design Outline q Logical Effort q Delay in a Logic Gate
Lecture 8: Combinational Circuit Design
Lecture 8: Combinational Circuit Design Mark McDermott Electrical and Computer Engineering The University of Texas at ustin 9/5/8 Verilog to Gates module mux(input s, d0, d, output y); assign y = s? d
VLSI Design, Fall Logical Effort. Jacob Abraham
6. Logical Effort 6. Logical Effort Jacob Abraham Department of Electrical and Computer Engineering The University of Texas at Austin VLSI Design Fall 207 September 20, 207 ECE Department, University of
Lecture 6: Circuit design part 1
Lecture 6: Circuit design part 6. Combinational circuit design 6. Sequential circuit design 6.3 Circuit simulation 6.4. Hardware description language Combinational Circuit Design. Combinational circuit
Logical Effort: Designing for Speed on the Back of an Envelope David Harris Harvey Mudd College Claremont, CA
Logical Effort: Designing for Speed on the Back of an Envelope David Harris David_Harris@hmc.edu Harvey Mudd College Claremont, CA Outline o Introduction o Delay in a Logic Gate o Multi-stage Logic Networks
ECE429 Introduction to VLSI Design
ECE429 Introduction to VLSI Design Lecture 5: LOGICAL EFFORT Erdal Oruklu Illinois Institute of Technology Some of these slides have been adapted from the slides provided by David Harris, Harvey Mudd College
EE 447 VLSI Design. Lecture 5: Logical Effort
EE 447 VLSI Design Lecture 5: Logical Effort Outline Introduction Delay in a Logic Gate Multistage Logic Networks Choosing the Best Number of Stages Example Summary EE 4475: VLSI Logical Design Effort
Lecture 6: Logical Effort
Lecture 6: Logical Effort Outline Logical Effort Delay in a Logic Gate Multistage Logic Networks Choosing the Best Number of Stages Example Summary Introduction Chip designers face a bewildering array
Very Large Scale Integration (VLSI)
Very Large Scale Integration (VLSI) Lecture 4 Dr. Ahmed H. Madian Ah_madian@hotmail.com Dr. Ahmed H. Madian-VLSI Contents Delay estimation Simple RC model Penfield-Rubenstein Model Logical effort Delay
EE M216A.:. Fall Lecture 5. Logical Effort. Prof. Dejan Marković
EE M26A.:. Fall 200 Lecture 5 Logical Effort Prof. Dejan Marković ee26a@gmail.com Logical Effort Recap Normalized delay d = g h + p g is the logical effort of the gate g = C IN /C INV Inverter is sized
Introduction to CMOS VLSI Design. Lecture 5: Logical Effort. David Harris. Harvey Mudd College Spring Outline
Introduction to CMOS VLSI Design Lecture 5: Logical Effort David Harris Harve Mudd College Spring 00 Outline Introduction Dela in a Logic Gate Multistage Logic Networks Choosing the Best Number of Stages
Logical Effort. Sizing Transistors for Speed. Estimating Delays
Logical Effort Sizing Transistors for Speed Estimating Delays Would be nice to have a back of the envelope method for sizing gates for speed Logical Effort Book by Sutherland, Sproull, Harris Chapter 1
Lecture 4: DC & Transient Response
Introduction to CMOS VLSI Design Lecture 4: DC & Transient Response David Harris Harvey Mudd College Spring 004 Outline DC Response Logic Levels and Noise Margins Transient Response Delay Estimation Slide
C.K. Ken Yang UCLA Courtesy of MAH EE 215B
Decoders: Logical Effort Applied C.K. Ken Yang UCLA yang@ee.ucla.edu Courtesy of MAH 1 Overview Reading Rabaey 6.2.2 (Ratio-ed logic) W&H 6.2.2 Overview We have now gone through the basics of decoders,
Spiral 2 7. Capacitance, Delay and Sizing. Mark Redekopp
2-7.1 Spiral 2 7 Capacitance, Delay and Sizing Mark Redekopp 2-7.2 Learning Outcomes I understand the sources of capacitance in CMOS circuits I understand how delay scales with resistance, capacitance
EE 466/586 VLSI Design. Partha Pande School of EECS Washington State University
EE 466/586 VLSI Design Partha Pande School of EECS Washington State University pande@eecs.wsu.edu Lecture 9 Propagation delay Power and delay Tradeoffs Follow board notes Propagation Delay Switching Time
Lecture 5. Logical Effort Using LE on a Decoder
Lecture 5 Logical Effort Using LE on a Decoder Mark Horowitz Computer Systems Laboratory Stanford University horowitz@stanford.edu Copyright 00 by Mark Horowitz Overview Reading Harris, Logical Effort
Topics. CMOS Design Multi-input delay analysis. John A. Chandy Dept. of Electrical and Computer Engineering University of Connecticut
Topics CMO Design Multi-input delay analysis pring 25 Transmission Gate OUT Z OUT Z pring 25 Transmission Gate OUT When is low, the output is at high impedance When is high, the output follows However,
Lecture 14: Circuit Families
Introduction to CMOS VLSI Design Lecture 4: Circuit Families David Harris, Harvey Mudd College Kartik Mohanram and Steven Levitan University of Pittsburgh Outline q Pseudo-nMOS Logic q Dynamic Logic q
EE5780 Advanced VLSI CAD
EE5780 Advanced VLSI CAD Lecture 4 DC and Transient Responses, Circuit Delays Zhuo Feng 4.1 Outline Pass Transistors DC Response Logic Levels and Noise Margins Transient Response RC Delay Models Delay
Interconnect (2) Buffering Techniques. Logical Effort
Interconnect (2) Buffering Techniques. Logical Effort Lecture 14 18-322 Fall 2002 Textbook: [Sections 4.2.1, 8.2.3] A few announcements! M1 is almost over: The check-off is due today (by 9:30PM) Students
Introduction to CMOS VLSI Design. Logical Effort B. Original Lecture by Jay Brockman. University of Notre Dame Fall 2008
Introduction to CMOS VLSI Design Logical Effort Part B Original Lecture b Ja Brockman Universit of Notre Dame Fall 2008 Modified b Peter Kogge Fall 2010,2011,2015, 2018 Based on lecture slides b David
Lecture 6: DC & Transient Response
Lecture 6: DC & Transient Response Slides courtesy of Deming Chen Slides based on the initial set from David Harris CMOS VLSI Design Outline Pass Transistors DC Response Logic Levels and Noise Margins
Lecture 5: DC & Transient Response
Lecture 5: DC & Transient Response Outline q Pass Transistors q DC Response q Logic Levels and Noise Margins q Transient Response q RC Delay Models q Delay Estimation 2 Activity 1) If the width of a transistor
UNIVERSITY OF CALIFORNIA, BERKELEY College of Engineering Department of Electrical Engineering and Computer Sciences
UNIVERSITY OF CALIFORNIA, BERKELEY College of Engineering Department of Electrical Engineering and Computer Sciences Elad Alon Homework #9 EECS141 PROBLEM 1: TIMING Consider the simple state machine shown
Name: Answers. Mean: 83, Standard Deviation: 12 Q1 Q2 Q3 Q4 Q5 Q6 Total. ESE370 Fall 2015
University of Pennsylvania Department of Electrical and System Engineering Circuit-Level Modeling, Design, and Optimization for Digital Systems ESE370, Fall 2015 Final Tuesday, December 15 Problem weightings
Lecture 4: Implementing Logic in CMOS
Lecture 4: Implementing Logic in CMOS Mark Mcermott Electrical and Computer Engineering The University of Texas at ustin Review of emorgan s Theorem Recall that: () = + and = ( + ) (+) = and + = ( ) ()
Digital Integrated Circuits A Design Perspective
igital Integrated Circuits esign Perspective esigning Combinational Logic Circuits 1 Combinational vs. Sequential Logic In Combinational Logic Circuit Out In Combinational Logic Circuit Out State Combinational
KINGS COLLEGE OF ENGINEERING DEPARTMENT OF ELECTRONICS AND COMMUNICATION ENGINEERING QUESTION BANK
KINGS COLLEGE OF ENGINEERING DEPARTMENT OF ELECTRONICS AND COMMUNICATION ENGINEERING QUESTION BANK SUBJECT CODE: EC 1354 SUB.NAME : VLSI DESIGN YEAR / SEMESTER: III / VI UNIT I MOS TRANSISTOR THEORY AND
EE115C Digital Electronic Circuits Homework #5
EE115C Digital Electronic Circuits Homework #5 Due Thursday, May 13, 6pm @ 56-147E EIV Problem 1 Elmore Delay Analysis Calculate the Elmore delay from node A to node B using the values for the resistors
Name: Grade: Q1 Q2 Q3 Q4 Q5 Total. ESE370 Fall 2015
University of Pennsylvania Department of Electrical and System Engineering Circuit-Level Modeling, Design, and Optimization for Digital Systems ESE370, Fall 205 Midterm Wednesday, November 4 Point values
ECE 342 Electronic Circuits. Lecture 34 CMOS Logic
ECE 34 Electronic Circuits Lecture 34 CMOS Logic Jose E. Schutt-Aine Electrical & Computer Engineering University of Illinois jesa@illinois.edu 1 De Morgan s Law Digital Logic - Generalization ABC... ABC...
Answers. Name: Grade: Q1 Q2 Q3 Q4 Total mean: 83, stdev: 14. ESE370 Fall 2017
University of Pennsylvania Department of Electrical and System Engineering Circuit-Level Modeling, Design, and Optimization for Digital Systems ESE370, Fall 2017 Midterm 2 Monday, November 6 Point values
Lecture 12 CMOS Delay & Transient Response
EE 471: Transport Phenomena in Solid State Devices Spring 2018 Lecture 12 CMOS Delay & Transient Response Bryan Ackland Department of Electrical and Computer Engineering Stevens Institute of Technology
9/18/2008 GMU, ECE 680 Physical VLSI Design
ECE680: Physical VLSI Design Chapter III CMOS Device, Inverter, Combinational circuit Logic and Layout Part 3 Combinational Logic Gates (textbook chapter 6) 9/18/2008 GMU, ECE 680 Physical VLSI Design
EE M216A.:. Fall Lecture 4. Speed Optimization. Prof. Dejan Marković Speed Optimization via Gate Sizing
EE M216A.:. Fall 2010 Lecture 4 Speed Optimization Prof. Dejan Marković ee216a@gmail.com Speed Optimization via Gate Sizing Gate sizing basics P:N ratio Complex gates Velocity saturation ti Tapering Developing
Lecture 34: Portable Systems Technology Background Professor Randy H. Katz Computer Science 252 Fall 1995
Lecture 34: Portable Systems Technology Background Professor Randy H. Katz Computer Science 252 Fall 1995 RHK.F95 1 Technology Trends: Microprocessor Capacity 100000000 10000000 Pentium Transistors 1000000
EE213, Spr 2017 HW#3 Due: May 17 th, in class. Figure 1
RULES: Please try to work on your own. Discussion is permissible, but identical submissions are unacceptable! Please show all intermediate steps: a correct solution without an explanation will get zero
and V DS V GS V T (the saturation region) I DS = k 2 (V GS V T )2 (1+ V DS )
ECE 4420 Spring 2005 Page 1 FINAL EXAMINATION NAME SCORE /100 Problem 1O 2 3 4 5 6 7 Sum Points INSTRUCTIONS: This exam is closed book. You are permitted four sheets of notes (three of which are your sheets
EECS 151/251A Homework 5
EECS 151/251A Homework 5 Due Monday, March 5 th, 2018 Problem 1: Timing The data-path shown below is used in a simple processor. clk rd1 rd2 0 wr regfile 1 0 ALU REG 1 The elements used in the design have
Integrated Circuits & Systems
Federal University of Santa Catarina Center for Technology Computer Science & Electronics Engineering Integrated Circuits & Systems INE 5442 Lecture 16 CMOS Combinational Circuits - 2 guntzel@inf.ufsc.br
Errata of K Introduction to VLSI Systems: A Logic, Circuit, and System Perspective
Errata of K13126 Introduction to VLSI Systems: A Logic, Circuit, and System Perspective Chapter 1. Page 8, Table 1-1) The 0.35-µm process parameters are from MOSIS, both 0.25-µm and 0.18-µm process parameters
Lecture 5: DC & Transient Response
Lecture 5: DC & Transient Response Outline Pass Transistors DC Response Logic Levels and Noise Margins Transient Response RC Delay Models Delay Estimation 2 Pass Transistors We have assumed source is grounded
EE371 - Advanced VLSI Circuit Design
EE371 - Advanced VLSI Circuit Design Midterm Examination May 1999 Name: No. Points Score 1. 20 2. 24 3. 26 4. 20 TOTAL / 90 In recognition of and in the spirit of the Stanford University Honor Code, I
CPE/EE 427, CPE 527 VLSI Design I Delay Estimation. Department of Electrical and Computer Engineering University of Alabama in Huntsville
CPE/EE 47, CPE 57 VLSI Design I Delay Estimation Department of Electrical and Computer Engineering University of labama in Huntsville leksandar Milenkovic ( www.ece.uah.edu/~milenka ) Review: CMOS Circuit
Digital Integrated Circuits A Design Perspective
Digital Integrated Circuits Design Perspective Jan M. Rabaey nantha Chandrakasan orivoje Nikolić Designing Combinational Logic Circuits November 2002. 1 Combinational vs. Sequential Logic In Combinational
Properties of CMOS Gates Snapshot
MOS logic 1 Properties of MOS Gates Snapshot High noise margins: V OH and V OL are at V DD and GND, respectively. No static power consumption: There never exists a direct path between V DD and V SS (GND)
EE115C Digital Electronic Circuits Homework #6
Problem 1 Sizing of adder blocks Electrical Engineering Department Spring 2010 EE115C Digital Electronic Circuits Homework #6 Solution Figure 1: Mirror adder. Study the mirror adder cell (textbook, pages
Digital Microelectronic Circuits ( ) Logical Effort. Lecture 7: Presented by: Adam Teman
Digital Microelectronic ircuits (361-1-3021 ) Presented by: Adam Teman Lecture 7: Logical Effort Digital Microelectronic ircuits The VLSI Systems enter - BGU Lecture 7: Logical Effort 1 Last Lectures The
EE141Microelettronica. CMOS Logic
Microelettronica CMOS Logic CMOS logic Power consumption in CMOS logic gates Where Does Power Go in CMOS? Dynamic Power Consumption Charging and Discharging Capacitors Short Circuit Currents Short Circuit
5. CMOS Gate Characteristics CS755
5. CMOS Gate Characteristics Last module: CMOS Transistor theory This module: DC Response Logic Levels and Noise Margins Transient Response Delay Estimation Transistor ehavior 1) If the width of a transistor
CMOS Digital Integrated Circuits Lec 10 Combinational CMOS Logic Circuits
Lec 10 Combinational CMOS Logic Circuits 1 Combinational vs. Sequential Logic In Combinational Logic circuit Out In Combinational Logic circuit Out State Combinational The output is determined only by
Lecture Outline. ESE 570: Digital Integrated Circuits and VLSI Fundamentals. Review: 1st Order RC Delay Models. Review: Two-Input NOR Gate (NOR2)
ESE 570: Digital Integrated Circuits and VLSI Fundamentals Lec 14: March 1, 2016 Combination Logic: Ratioed and Pass Logic Lecture Outline! CMOS Gates Review " CMOS Worst Case Analysis! Ratioed Logic Gates!
Miscellaneous Lecture topics. Mary Jane Irwin [Adapted from Rabaey s Digital Integrated Circuits, 2002, J. Rabaey et al.]
![Miscellaneous Lecture topics. Mary Jane Irwin [Adapted from Rabaey s Digital Integrated Circuits, 2002, J. Rabaey et al.]](/thumbs/81/84503671.jpg "Miscellaneous Lecture topics. Mary Jane Irwin [Adapted from Rabaey s Digital Integrated Circuits, 2002, J. Rabaey et al.]")
Miscellaneous Lecture topics Mary Jane Irwin [dapted from Rabaey s Digital Integrated Circuits, 2002, J. Rabaey et al.] MOS Switches MOS transistors can be viewed as simple switches. In an N-Switch, the
University of Toronto. Final Exam
University of Toronto Final Exam Date - Apr 18, 011 Duration:.5 hrs ECE334 Digital Electronics Lecturer - D. Johns ANSWER QUESTIONS ON THESE SHEETS USING BACKS IF NECESSARY 1. Equation sheet is on last
Digital Logic. CS211 Computer Architecture. l Topics. l Transistors (Design & Types) l Logic Gates. l Combinational Circuits.
CS211 Computer Architecture Digital Logic l Topics l Transistors (Design & Types) l Logic Gates l Combinational Circuits l K-Maps Figures & Tables borrowed from:! http://www.allaboutcircuits.com/vol_4/index.html!
ECE 425 Midterm Overview. Fall 2017
ECE 425 Midterm Overview Fall 2017 Overview q Midterm (20% of total grade) Oct 24 th 3:30-5:00pm in class q Materials Lecture 1 through 11 MP0, MP1 HW1, HW2 Practice exam q Rules 1 page of cheat sheet,
Logic Gate Sizing. The method of logical effort. João Canas Ferreira. March University of Porto Faculty of Engineering
Logic Gate Sizing The method of logical effort João Canas Ferreira University of Porto Faculty of Engineering March 016 Topics 1 Modeling CMOS Gates Chain of logic gates João Canas Ferreira (FEUP) Logic
Physical Design of Digital Integrated Circuits (EN0291 S40) Sherief Reda Division of Engineering, Brown University Fall 2006
Physical Design of Digital Integrated Circuits (EN0291 S40) Sherief Reda Division of Engineering, Brown University Fall 2006 1 Lecture 04: Timing Analysis Static timing analysis STA for sequential circuits
Homework Assignment #1 Solutions EE 477 Spring 2017 Professor Parker
Homework Assignment #1 Solutions EE 477 Spring 2017 Professor Parker Note: + implies OR,. implies AND, ~ implies NOT Question 1: a) (4%) Use transmission gates to design a 3-input OR gate Note: There are
9. Datapath Design. Jacob Abraham. Department of Electrical and Computer Engineering The University of Texas at Austin VLSI Design Fall 2017
9. Datapath Design Jacob Abraham Department of Electrical and Computer Engineering The University of Texas at Austin VLSI Design Fall 2017 October 2, 2017 ECE Department, University of Texas at Austin
Topic 4. The CMOS Inverter
Topic 4 The CMOS Inverter Peter Cheung Department of Electrical & Electronic Engineering Imperial College London URL: www.ee.ic.ac.uk/pcheung/ E-mail: p.cheung@ic.ac.uk Topic 4-1 Noise in Digital Integrated
EECS 312: Digital Integrated Circuits Midterm Exam 2 December 2010
Signature: EECS 312: Digital Integrated Circuits Midterm Exam 2 December 2010 obert Dick Show your work. Derivations are required for credit; end results are insufficient. Closed book. No electronic mental
Chapter 4. Digital Integrated Circuit Design I. ECE 425/525 Chapter 4. CMOS design can be realized meet requirements from
Digital Integrated Circuit Design I ECE 425/525 Professor R. Daasch Depar tment of Electrical and Computer Engineering Portland State University Portland, OR 97207-0751 (daasch@ece.pdx.edu) http://ece.pdx.edu/~ecex25
Dynamic Combinational Circuits. Dynamic Logic
Dynamic Combinational Circuits Dynamic circuits Charge sharing, charge redistribution Domino logic np-cmos (zipper CMOS) Krish Chakrabarty 1 Dynamic Logic Dynamic gates use a clocked pmos pullup Two modes:
Testability. Shaahin Hessabi. Sharif University of Technology. Adapted from the presentation prepared by book authors.
Testability Lecture 6: Logic Simulation Shaahin Hessabi Department of Computer Engineering Sharif University of Technology Adapted from the presentation prepared by book authors Slide 1 of 27 Outline What
Floating Point Representation and Digital Logic. Lecture 11 CS301
Floating Point Representation and Digital Logic Lecture 11 CS301 Administrative Daily Review of today s lecture w Due tomorrow (10/4) at 8am Lab #3 due Friday (9/7) 1:29pm HW #5 assigned w Due Monday 10/8
EEE 421 VLSI Circuits
EEE 421 CMOS Properties Full rail-to-rail swing high noise margins» Logic levels not dependent upon the relative device sizes transistors can be minimum size ratioless Always a path to V dd or GND in steady
ECE 546 Lecture 10 MOS Transistors
ECE 546 Lecture 10 MOS Transistors Spring 2018 Jose E. Schutt-Aine Electrical & Computer Engineering University of Illinois jesa@illinois.edu NMOS Transistor NMOS Transistor N-Channel MOSFET Built on p-type
ESE 570: Digital Integrated Circuits and VLSI Fundamentals
ESE 570: Digital Integrated Circuits and VLSI Fundamentals Lec 15: March 3, 2016 Combination Logic: Ratioed & Pass Logic, and Performance Lecture Outline! CMOS NOR2 Worst Case Analysis! Pass Transistor
EE371 - Advanced VLSI Circuit Design
EE371 - Advanced VLSI Circuit Design Midterm Examination May 7, 2002 Name: No. Points Score 1. 18 2. 22 3. 30 TOTAL / 70 In recognition of and in the spirit of the Stanford University Honor Code, I certify
ESE 570: Digital Integrated Circuits and VLSI Fundamentals
ESE 570: Digital Integrated Circuits and VLSI Fundamentals Lec 2: January 17, 2017 MOS Fabrication pt. 1: Physics and Methodology Lecture Outline! Digital CMOS Basics! VLSI Fundamentals! Fabrication Process
ESE 570: Digital Integrated Circuits and VLSI Fundamentals
ESE 570: Digital Integrated Circuits and VLSI Fundamentals Lec 2: January 19, 2016 MOS Fabrication pt. 1: Physics and Methodology Lecture Outline! Digital CMOS Basics! VLSI Fundamentals! Fabrication Process
Lecture 7: Logic design. Combinational logic circuits
/24/28 Lecture 7: Logic design Binary digital circuits: Two voltage levels: and (ground and supply voltage) Built from transistors used as on/off switches Analog circuits not very suitable for generic
Lecture 22 Chapters 3 Logic Circuits Part 1
Lecture 22 Chapters 3 Logic Circuits Part 1 LC-3 Data Path Revisited How are the components Seen here implemented? 5-2 Computing Layers Problems Algorithms Language Instruction Set Architecture Microarchitecture
VLSI Design. [Adapted from Rabaey s Digital Integrated Circuits, 2002, J. Rabaey et al.] ECE 4121 VLSI DEsign.1
![VLSI Design. [Adapted from Rabaey s Digital Integrated Circuits, 2002, J. Rabaey et al.] ECE 4121 VLSI DEsign.1](/thumbs/72/67474772.jpg "VLSI Design. [Adapted from Rabaey s Digital Integrated Circuits, 2002, J. Rabaey et al.] ECE 4121 VLSI DEsign.1")
VLSI Design Adder Design [Adapted from Rabaey s Digital Integrated Circuits, 2002, J. Rabaey et al.] ECE 4121 VLSI DEsign.1 Major Components of a Computer Processor Devices Control Memory Input Datapath
CMOS logic gates. João Canas Ferreira. March University of Porto Faculty of Engineering
CMOS logic gates João Canas Ferreira University of Porto Faculty of Engineering March 2016 Topics 1 General structure 2 General properties 3 Cell layout João Canas Ferreira (FEUP) CMOS logic gates March
CMPEN 411 VLSI Digital Circuits Spring 2011 Lecture 07: Pass Transistor Logic
CMPEN 411 VLSI Digital Circuits Spring 2011 Lecture 07: Pass Transistor Logic [dapted from Rabaey s Digital Integrated Circuits, Second Edition, 2003 J. Rabaey,. Chandrakasan,. Nikolic] Sp11 CMPEN 411
EECS 141: SPRING 09 MIDTERM 2
University of California College of Engineering Department of Electrical Engineering and Computer Sciences J. Rabaey WeFr 2-3:30pm We, April 22, 2:00-3:30pm EECS 141: SPRING 09 MIDTERM 2 NAME Last First
DC and Transient. Courtesy of Dr. Daehyun Dr. Dr. Shmuel and Dr.
DC and Transient Courtesy of Dr. Daehyun Lim@WSU, Dr. Harris@HMC, Dr. Shmuel Wimer@BIU and Dr. Choi@PSU http://csce.uark.edu +1 (479) 575-604 yrpeng@uark.edu Pass Transistors We have assumed source is
EECS 427 Lecture 8: Adders Readings: EECS 427 F09 Lecture 8 1. Reminders. HW3 project initial proposal: due Wednesday 10/7
EECS 427 Lecture 8: dders Readings: 11.1-11.3.3 3 EECS 427 F09 Lecture 8 1 Reminders HW3 project initial proposal: due Wednesday 10/7 You can schedule a half-hour hour appointment with me to discuss your
EECS 312: Digital Integrated Circuits Final Exam Solutions 23 April 2009
Signature: EECS 312: Digital Integrated Circuits Final Exam Solutions 23 April 2009 Robert Dick Show your work. Derivations are required for credit; end results are insufficient. Closed book. You may use
Chapter 9. Estimating circuit speed. 9.1 Counting gate delays
Chapter 9 Estimating circuit speed 9.1 Counting gate delays The simplest method for estimating the speed of a VLSI circuit is to count the number of VLSI logic gates that the input signals must propagate
VLSI Circuit Design (EEC0056) Exam
Mestrado Integrado em Engenharia Eletrotécnica e de omputadores VLSI ircuit esign (EE0056) Exam 205/6 4 th year, 2 nd sem. uration: 2:30 Open notes Note: The test has 5 questions for 200 points. Show all
CARNEGIE MELLON UNIVERSITY DEPARTMENT OF ELECTRICAL AND COMPUTER ENGINEERING DIGITAL INTEGRATED CIRCUITS FALL 2002
CARNEGIE MELLON UNIVERSITY DEPARTMENT OF ELECTRICAL AND COMPUTER ENGINEERING 18-322 DIGITAL INTEGRATED CIRCUITS FALL 2002 Final Examination, Monday Dec. 16, 2002 NAME: SECTION: Time: 180 minutes Closed
Dynamic Combinational Circuits. Dynamic Logic
Dynamic Combinational Circuits Dynamic circuits Charge sharing, charge redistribution Domino logic np-cmos (zipper CMOS) Krish Chakrabarty 1 Dynamic Logic Dynamic gates use a clocked pmos pullup Two modes:
Fault Modeling. 李昆忠 Kuen-Jong Lee. Dept. of Electrical Engineering National Cheng-Kung University Tainan, Taiwan. VLSI Testing Class
Fault Modeling 李昆忠 Kuen-Jong Lee Dept. of Electrical Engineering National Cheng-Kung University Tainan, Taiwan Class Fault Modeling Some Definitions Why Modeling Faults Various Fault Models Fault Detection
Bit-Sliced Design. EECS 141 F01 Arithmetic Circuits. A Generic Digital Processor. Full-Adder. The Binary Adder
it-liced Design Control EEC 141 F01 rithmetic Circuits Data-In Register dder hifter it 3 it 2 it 1 it 0 Data-Out Tile identical processing elements Generic Digital Processor Full-dder MEMORY Cin Full adder
Topics to be Covered. capacitance inductance transmission lines
Topics to be Covered Circuit Elements Switching Characteristics Power Dissipation Conductor Sizes Charge Sharing Design Margins Yield resistance capacitance inductance transmission lines Resistance of
CPE/EE 427, CPE 527 VLSI Design I L18: Circuit Families. Outline
CPE/EE 47, CPE 57 VLI Design I L8: Circuit Families Department of Electrical and Computer Engineering University of labama in Huntsville leksandar Milenkovic ( www.ece.uah.edu/~milenka ) www.ece.uah.edu/~milenka/cpe57-05f
EE 330 Lecture 37. Digital Circuits. Other Logic Families. Propagation Delay basic characterization Device Sizing (Inverter and multiple-input gates)
EE 330 Lecture 37 Digital Circuits Other Logic Families Static Power Dissipation Propagation Delay basic characterization Device Sizing (Inverter and multiple-input gates) Review from Last Time Inverter
ECE 407 Computer Aided Design for Electronic Systems. Simulation. Instructor: Maria K. Michael. Overview
407 Computer Aided Design for Electronic Systems Simulation Instructor: Maria K. Michael Overview What is simulation? Design verification Modeling Levels Modeling circuits for simulation True-value simulation
Review: Additional Boolean operations
Review: Additional Boolean operations Operation: NAND (NOT-AND) NOR (NOT-OR) XOR (exclusive OR) Expressions: (xy) = x + y (x + y) = x y x y = x y + xy Truth table: x y (xy) x y (x+y) x y x y 0 0 1 0 1
Lecture 14 - Digital Circuits (III) CMOS. April 1, 2003
6.12 - Microelectronic Devices and Circuits - Spring 23 Lecture 14-1 Lecture 14 - Digital Circuits (III) CMOS April 1, 23 Contents: 1. Complementary MOS (CMOS) inverter: introduction 2. CMOS inverter:
MASSACHUSETTS INSTITUTE OF TECHNOLOGY Department of Electrical Engineering and Computer Sciences
MASSACHUSETTS INSTITUTE OF TECHNOLOGY Department of Electrical Engineering and Computer Sciences Analysis and Design of Digital Integrated Circuits (6.374) - Fall 2003 Quiz #2 Prof. Anantha Chandrakasan