EE141. Administrative Stuff


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1 Spring 2004 Digital Integrated ircuits Lecture 15 Logical Effort Pass Transistor Logic 1 dministrative Stuff First (short) project to be launched next Th. Overall span: 1 week Hardware lab this week Hw 5 due on Th New Hw 6 2 1
2 Schedule Last lecture: complex logic Today: Logical effort Pass Transistor Logic 3 FanIn onsiderations D 3 L Distributed R model (Elmore delay) D 2 1 t phl = 0.69 R eqn ( L ) Propagation delay deteriorates rapidly as a function of fanin quadratically in the worst case. 4 2
3 t p as a Function of FanIn (NND) t p (psec) t phl t plh quadratic 250 linear fanin t p Gates with a fanin greater than 4 should be avoided. 5 t p as a Function of FanOut t p (psec) t p NOR2 t p NND2 t p INV eff. fanout ll gates have the same drive current. Slope is a function of driving strength 6 3
4 t p as a Function of FanIn and FanOut Fanin: quadratic due to increasing resistance and capacitance Fanout: each additional fanout gate adds two gate capacitances to L t p = a 1 FI + a 2 FI 2 + a 3 FO 7 Fast omplex Gates: Design Technique 1 Transistor sizing as long as fanout capacitance dominates Progressive sizing In N MN L Distributed R line In 3 M3 3 M1 > M2 > M3 > > MN (the FET closest to the output is the smallest) In 2 In 1 M2 M1 2 1 an reduce delay by more than 20%; e careful: input loading, junction caps, decreasing gains as technology shrinks 8 4
5 Fast omplex Gates: Design Technique 2 Transistor ordering critical path critical path In 3 1 In 2 1 In M3 0 1 charged L In 1 M3 charged L M2 2 charged In 2 1 M2 2 discharged In M1 charged 3 1 M1 discharged 1 1 delay determined by time to discharge L, 1 and 2 delay determined by time to discharge L 9 Fast omplex Gates: Design Technique 3 lternative logic structures F = DEFGH 10 5
6 Fast omplex Gates: Design Technique 4 Isolating fanin from fanout using buffer insertion L L 11 Fast omplex Gates: Design Technique 5 Reducing the voltage swing t phl = 0.69 (3/4 ( L )/ I DSTn ) = 0.69 (3/4 ( L V swing )/ I DSTn ) linear reduction in delay also reduces power consumption ut the following gate is much slower! Or requires use of sense amplifiers on the receiving end to restore the signal level (memory design) 12 6
7 Sizing Logic Paths for Speed Frequently, input capacitance of a logic path is constrained Logic has to drive some capacitance Example: LU load in an Intel s microprocessor is 0.5pF How do we size the LU datapath to achieve maximum speed? We have already solved this for the inverter chain can we generalize it for any type of logic? 13 uffer Example In Out 1 2 N Delay = N ( pi + gi hi ) i= 1 L (in units of τ inv ) For given N: i+1 / i = i / i1 To find N: i+1 / i ~ 4 How to generalize this to any logic path? 14 7
8 Delay in a Logic Gate Gate delay: d = h + p effort delay intrinsic delay Effort delay: h = g f logical effort effective fanout = out / in Logical effort is a function of topology, independent of sizing Effective fanout (electrical effort) is a function of load/gate size 15 Logical Effort Delay = k τ 0 p + gf γ p parasitic delay  gate parameter f(w) g logical effort gate parameter f(w) f electrical effort (effective fanout) Normalize everything to an inverter: g inv =1, p inv = 1 Everything is measured in unit delays τ
9 uffer Example In Out 1 2 N L Delay = N i i pi + i= 1 γ g f p i, g i are constant (and equal to 1) Variables are f i Minimum delay is when f i s are equal (each stage bears the same effort) (in units of τ 0 ) 17 Logical Effort Inverter has the smallest logical effort and intrinsic delay of all static MOS gates Logical effort of a gate presents the ratio of its input capacitance to the inverter capacitance when sized to deliver the same current Logical effort increases with the gate complexity 18 9
10 alculating Logical Effort Logical effort is the ratio of input capacitance of a gate to the input capacitance of an inverter with the same output current g = 1 g = 4/3 g = 5/3 19 Logical Effort of Gates Normalized delay (d) g= p= d= t pnnd g= p= d= tpinv F(Fanin) Fanout (h) 20 10
11 Logical Effort of Gates Normalized delay (d) g=4/3 p=2 d=(4/3)f+2 t pnnd tpinv g=1 p=1 d=f+1 F(Fanin) Fanout (f) 21 Logical Effort 22 11
12 dd ranching Effort ranching effort: on path + off path b = on path 23 Multistage Networks Delay = Stage effort: h i = g i f i Path electrical effort: F = out / in Path logical effort: G = g 1 g 2 g N ranching effort: = b 1 b 2 b N Path effort: H = GF N i i pi + i= 1 γ Path delay D = Σd i = Σp i + Σf i g i /γ g f 24 12
13 Optimum Effort per Stage When each stage bears the same effort: hˆ N = H h ˆ = N H Effective fanout of each stage: f = hˆ i g i Minimum path delay g fi NH Dˆ = + pi = γ γ 1/ N i + P 25 Example: Optimize Path f F = 2 G = 20/9 H = 40/9 h =1.45 x =10f1 = 10h/g1=14.5 y = 14.5(1.45*3/5)=12.6 z = 12.6(1.45*3/4)=13.7 From David Harris ssume that size factors relate to gate with some input cap as inverter 26 13
14 Multilevel level logic: What is best? g = 10/3 g =1 G = 10/3 g = 2 g =5/3 G = 10/3 g =10/3 g=5/3 g=4/3 g=1 G = 80/27 27 Summary Logical Effort Electrical Effort ranching Effort Effort Effort Delay Number of Stages Parasitic Delay Delay Stage g f = out / in n/a h = fg h 1 p d = h + p Path G = g i F = out / in = bi H = FG D H = hi N D P= D H + Pp = i 28 14
15 Method of Logical Effort ompute the path effort: H = GF Find the best number of stages N ~ log 4 H ompute the stage effort h = H 1/N Sketch the path with this number of stages Work either from either end, find sizes: in = out *g/h Reference: Sutherland, Sproull, Harris, Logical Effort, MorganKaufmann Ratioed Logic 30 15
16 Ratioed Logic Resistive Load R L F Depletion Load V T < 0 F PMOS Load V SS F In 1 In 2 In 3 PDN In 1 In 2 In 3 PDN In 1 In 2 In 3 PDN V SS V SS V SS (a) resistive load (b) depletion load NMOS (c) pseudonmos Goal: to reduce the number of devices over complementary MOS 31 Ratioed Logic Resistive Load R L N transistors + Load V OH = F V OL = R PN R PN + R L In 1 In 2 In 3 PDN ssymetrical response Static power consumption V SS t pl = 0.69 R L L 32 16
17 ctive Loads Depletion Load V T < 0 PMOS Load F V SS F In 1 In 2 In 3 PDN In 1 In 2 In 3 PDN V SS V SS depletion load NMOS pseudonmos 33 PseudoNMOS With long channel devices D F L V OH = (similar to complementary MOS) V2 k V V OL k n ( DD Tn )V OL = p ( V V 2 2 DD Tp ) 2 V OL = ( V DD V T ) 1 1 k p (assuming that V k T = V Tn = V Tp ) n SMLLER RE & LOD UT STTI POWER DISSIPTION!!! 34 17
18 PseudoNMOS VT W/L p = 4 V ou t [V] W/L p = W/L p = 0.5 W/L p = 0.25 W/L p = V in [V] 35 Improved Loads Enable M1 M2 M1 >> M2 F D L daptive Load 36 18
19 Improved Loads (2) M1 M2 Out Out PDN1 PDN2 V SS V SS Differential ascode Voltage Switch Logic (DVSL) 37 DVSL Example Out Out XORNXOR gate 38 19
20 DVSL Transient Response 2.5 V oltage [V] ,, Time [ns] 39 PassTransistor Logic 40 20
21 PassTransistor Logic Inputs Switch Network Out Out N transistors No static consumption 41 Example: ND Gate F =
22 NMOSOnly Only Logic In x 0.5µm/0.25µm 1.5µm/ 0.25µm Out 0.5µm/ 0.25µm Voltage [V] Out x In Time [ns] 43 NMOSonly Switch = 2.5V = 2.5 V = 2.5 V = 2.5 V M n M 2 L M 1 V does not pull up to 2.5V, but 2.5V V TN Threshold voltage loss causes static power consumption NMOS has higher threshold than PMOS (body effect) 44 22
23 NMOS Only Logic: Level Restoring Transistor Level Restorer M n M r X M 2 Out M 1 dvantage: Full Swing Restorer adds capacitance, takes away pull down current at X Ratio problem 45 Restorer Sizing Voltage [V] W/L r =1.75/0.25 W/L r =1.50/0.25 W/L r =1.0/0.25 W/L r =1.25/0.25 Upper limit on restorer size Passtransistor pulldown can have several transistors in stack Time [ps] 46 23
24 Solution 2: Single Transistor Pass Gate with V T =0 0V 2.5V 0V Out 2.5V WTH OUT FOR LEKGE URRENTS 47 omplementary Pass Transistor Logic PassTransistor Network F (a) Inverse PassTransistor Network F F= F=+ F= ΒÝ (b) F= F=+ F= ΒÝ ND/NND OR/NOR EXOR/NEXOR 48 24
25 Solution 3: Transmission Gate = 2.5 V = 2.5 V L = 0 V 49 Resistance of Transmission Gate 30 R n 2. 5 V Rn Resistance, ohms R p R n R p 2.5 V 0 V R p V ou t V ou t, V 50 25
26 PassTransistor ased Multiplexer S S S M 2 S F M 1 S GND In 1 S S In 2 51 Transmission Gate XOR M2 M1 F M3/M
27 Delay in Transmission Gate Networks In V 1 V i1 V i V i+1 V n1 V n (a) In R eq R V eq R eq R 1 V i V eq Vi+1 n1 Vn m (b) Req Req R eq Req Req Req In (c) 53 Delay Optimization 54 27
28 Transmission Gate Full dder P P i i P S Sum Generation P P P o arry Generation i i i Setup P Similar delays for sum and carry 55 Next Lecture Project launch Dynamic logic 56 28
29 Next Lecture MOS Logic Properties 57 29
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