UNIVERSITY OF CALIFORNIA, BERKELEY College of Engineering Department of Electrical Engineering and Computer Sciences

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1 UNIVERSITY OF CALIFORNIA, BERKELEY College of Engineering Department of Electrical Engineering and Computer Sciences Elad Alon Homework #9 EECS141 PROBLEM 1: TIMING Consider the simple state machine shown above. A, B, and C represent combinational logic blocks with the following properties: t logic,mina = 00 ps; t logic,maxa = 1 ns; t logic,minb = 300 ps; t logic,maxb = ns; t logic,minc = 100 ps; t logic,maxc = 0.5 ns; The L-units represent positive latches clocked by φ (i.e., the latches are transparent when φ is high). These latches have a setup time of 150 ps and a t d-q delay of 50 ps (when the latch is transparent). The clock to output delay t clk-q is 100 ps, and t hold is 100 ps. The clock φ has a period T clk and is high for a duration of T on in other words, the duty cycle of the clock is T on /T clk. a) Determine the conditions on the clock necessary to avoid the occurrence of holdtime violations. We want to ensure that there is no way for a new value at the output of a latch to race through the logic so quickly that the value of the latch changes again before the clock goes low. There are two possible paths for this to happen: L1 A C L, and

2 L B C L; since t logic,mina is less than t logic,minb, the first of these two paths is the most critical one. Therefore, the maximum T on we can use is set by: t clk-q + t logic,mina + t logic,minc > T on + t hold T on < 100ps + 00ps + 100ps 100ps T on < 300ps b) Determine the absolute minimum clock period for this circuit to work correctly as well as the maximum duty cycle. The two possible paths that set the minimum clock period are the same two paths that set the maximum T on. However, this time, since t logic,maxb > t logic,maxa, it is the L B C L path that we need to consider. There are actually two possible scenarios that could set the minimum clock period: 1) The old data arrives right before φ goes high, and the new data must arrive t setup before the falling edge of φ. In this case, T clk is set by: t clk-q + t logic,maxb + t logic,maxc + t setup < T clk 100ps + ns + 0.5ns + 150ps < T clk T clk >.75ns ) The old data arrives exactly t setup before φ goes low (i.e., while L is transparent), and the new data must arrive at most one clock cycle later (so that in the worst case, the new data also arrives exactly t setup before φ goes low on the next clock cycle). In this case, T clk is set by: t d-q + t logic,maxb + t logic,maxc < T clk 50ps + ns + 0.5ns < T clk T clk >.75ns In general, we would have to take the maximum of the results from cases 1) and ) to find the minimum clock period, but since t clk-q + t setup = t d-q for these latches, both cases give the same result of T clk >.75ns. Combining this with the answer from a), the maximum duty cycle of the clock is T on,max /T clk,min = 300ps/.75ns 10.91% c) Suppose that due to some sloppy clock-network routing, the clock signal at L1 arrives 100ps earlier than the clock signal at L. Calculate the absolute minimum clock period for this circuit to work properly as well as the maximum duty cycle.

3 Clearly, this clock skew only affects the L1 A C L path. Since this path does not impact the minimum cycle time, T clk,min is unchanged, and remains.75ns. It is exactly this path that determines the maximum T on however; since the clock to L1 arrives early, there is more time for the new value to race through logic block A and C and be latched by L. So, T on is now set by: -t skew + t clk-q + t logic,mina + t logic,minc > T on + t hold T on < -100ps + 100ps + 00ps + 100ps 100ps T on < 00ps So, the maximum duty cycle is now 00ps/.75ns 7.3%. PROBLEM : LIMITED SWITCH DYNAMIC LOGIC Clk 1 1 V x Out A B C PMOS: NMOS: 1 1 The circuit above (with relative transistor sizes annotated) is a Limited Switch Dynamic Logic (LSDL) NOR3 gate, which is essentially a dynamic gate followed by a latch. a) What purpose are the shaded transistors serving? The shaded transistors act as keepers to maintain a static output. Without these transistors, the input of the inverter would be floating during the pre-charge phase.

4 b) Assuming no propagation delay, complete the following ideal timing diagram. Clk A B C V x Out c) Calculate the t setup of this gate in terms of t inv. In other words, how long before the falling edge of the clock do the inputs have to be stable to ensure that the correct value is latched at the output? You can assume that γ=1. The circuit is composed of three stages: the first stage is a domino gate, the second stage is the inverter with keepers, and the third stage is the output inverter. For t setup we only need to consider the propagation delay through the first two stages. Once the output of the second stage is set, the clock can safely transition without the risk of losing the latched data.

5 The delay of the first two stages can be analyzed using either logical effort or simply an RC model. We will describe the method based on logical effort. First, let s calculate the logical effort and worst-case parasitic delay of the first stage during the evaluation phase: LE NOR3 = /3 p NOR3 = 7/3t inv f NOR3 =4/ = So, the delay of the first stage is (/3*+7/3)t inv = (11/3)t inv For the second stage, the input to the latch transitions from high to low during evaluation, so we should calculate the logical effort and parasitic delay of the gate when it is pulling the output high. Since V x is low when the second stage is pulling its output high, we don t need to worry about the NMOS keeper. Thus: LE latch = 4/3 p latch = 5/3t inv f latch = 3/4 So, the delay of the second stage is (4/3*3/4+5/3)t inv = (8/3)t inv Hence, the setup time is: (19/3)t inv d) Assuming that A=B=C=1, compare the activity factor at node Out to the activity factor at node V x (which would be the output of a standard dynamic logic gate). What can you infer about the dynamic power consumption of static gates being driven by this LSDL gate compared to gates driven by domino logic? In the LSDL gate with A=B=C=1, V x transitions every cycle. However, because of the latch, Out will remain constant despite the transitions on V x. Thus, in comparison to a standard domino gate, the number of transitions at the output of an LSDL gate is significantly lower, leading to less data-dependent dynamic power consumption. Of course, this reduced activity factor at the output doesn t come for free the LSDL gate has higher clock loading due to the extra clock transistor in the latch.

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