Chapter 4. Digital Integrated Circuit Design I. ECE 425/525 Chapter 4. CMOS design can be realized meet requirements from

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1 Digital Integrated Circuit Design I ECE 425/525 Professor R. Daasch Depar tment of Electrical and Computer Engineering Portland State University Portland, OR (daasch@ece.pdx.edu) 1 October 2014 Many CMOS designs meet the logical requirements Fewer CMOS designs meet all requirements delay, power, manufacturable, reliable CMOS design can be realized meet requirements from extensive trial and error simulation Initial guesses far from final solution Improvements are slow Lower reliability and difficult to reach yield targets Design choices that require a rapid estimate What circuit topology? How may stages between flip-flops Size oftransistors 2 October 2014

2 Asimple delay model addresses these and other questions Are all gates different, the delay model says no Does every design decision need spice, the delay model says no Can the decision be technology independent, the delay model says most of the time Delay models delay = parasitic delay + stage delay Stage delay How much current can this gate deliver to the load compared to a predetermined base (typically an inverter) What is the fan-out of the gate output Parasitic delay October 2014 What would be the delay without an exter nal load Parasitic delay aka internal delay isthe internal delays of the (primar ily) diffusion capacitance Logical effor t is the ratio of the input capacitance to inverter with the drive same current Major contributions to RC delay are Gate delay transistor sizing, circuit topology Interconnect wiring Delay estimates are particular ly impor tant for the critical path RC time constant first delay estimate t pd = RC ln V DD Vout = RC ln 2 V out = VDD /2 4 October 2014

3 Delay estimates early in design means improvements are str uctured for efficient design intervals Estimates are not for perfection but for reliability Good estimates get 80%-90% of the final detailed solution Common to expend design effor t (and time) on small corrections when the overall solution is still unknown Reff is the equivalent replacement of the average current through FET Each node in pullup/pulldown resistor tree has an effective resistance R1 R2 C1 C2 Total time constant approximated by sum (dominant pole approximation) 5 October 2014 t 1 + t 2 = t pd = R1C1 + (R1 + R2)C2 Such an estimate is accurate for only a brief moment in the logic transition Ceff is the load such that the transition time Contr ibutions to C Reff Ceff = t plh + t phl 2 Diffusion drain terminal of transistor at output of gate (ie parasitic delay) Gate oxide gate terminals of transistors controlled by output of gate (ie logical effor t) Interconnect the wire, metal, poly, contacts, vias linking drain to gate 6 October 2014

4 Contr ibutions to R Ser ies transistor networ k effective increases L of combined logic transistor Parallel transistor networ k effective increase of W of combined logic transistor Naturally propagation delay accumulates from gate to circuit, circuit to the system There are a few (< 10%) of the gate paths that limit perfor mance, the critical path Rapid delay estimate within 10% key element to designer productivity A RC delay estimate includes all major design decisions Effective resistance of single FET Reff L W 1 VDD Vt 7 October 2014 Common to incorporate the ln 2from the first time constant Inter nal capacitance of the gate Ceff W + Fanout Logical effor t ratio of logic gate input capacitance (CoxWL) tounit inverter input capacitance Common gates NANDn = (n + 2) / NORn = (2n + 1) / Xor depends on networ k topology with different g values for different inputs The inverter delay is a convenient delay nor malization 8 October 2014

5 Each inverter drive isscaled from minimum sizing Tr acks each shift in technology node Inverter drive current proportional to input capacitance (transistor W Inverter current combines all major contributions of process (tox, N A, W, L etc.) Logical effor t is the slope of the linear delay model Electr ical effor t is the independent var iable Unit analysis Nor malized delay time is a scaled time constant d = RC inverter Delay capacitance is gate output capacitance 9 October 2014 Delay resistance is logic gates transistor sourcing or sinking current Logical effor t is inverse of drive (not to be confused with output current) Drive Cin logical effort Logical effor t indicates how much worse a gate is at producing output current compared to the inverter, Weste p. 166 Logical effor t measures the effects of transistor sizing on the input transition compared to the inverter input Logical effor t favors NANDs over NORs Inverters and NAND2 best for driving large capacitive loads 10 October 2014

6 Identical functions may have different logical effor ts Different inputs of the same gate may have different logical effor ts First estimate parasitic delay Common gate s inter nal delay can be adjusted to near equal values (pullup and pulldown networ ks are duals) NANDs and NORs have the same total output diffusion capacitance Second method parasitic delays consider internal capacitance second (Elmore) model = R(nC) + n 1 Σ irc = ( i n(n 1) 2 + n)rc As the series transistor stack grows the delay grows by n 2 11 October 2014 Inter nal parasitic capacitance favors NAND gates A chain of identical inverters each block has g=1, h=1, p=1 d = g h + p = = 2 Tw o units of normalized delay for each inverter in the chain Logical effor t for single gates nor malized frequency = 1/d Evaluate transistor topology options for a specific Boolean function Tr ansistors sized for equivalent gate-to-gate perfor mance for var ying output load Logical effor t for multiple stage logic functions Expands beyond a single logic gate design 12 October 2014

7 Select topology (as before) Select the number of levels (inverting stages) in the logic Inverting stages is any restor ing gate, NAND, NOR, AOI... Size transistors for best (optimum) overall perfor mance (inter nal gate-to-gate load and output load) A path delay is a linear sum of stage delays Paths are fastest when effor t delays are f 4 Said another way, delay ofpath is log4 delays Path delay is weakly sensitive to stages, sizes Using few er stages doesn t mean faster paths Consider a path of two stages (NAND - NOR) F FO4 inver ter 1 October 2014 g 1 = 4/ h1 g 2 = 5/ h2 H Path delay is sum of two stages Delay = (g 1h1 + p1) + (g 2h2 + p2) = (g 1h1 + p1) + g 2 H h1 + p2 D h1 = g 1 g 2H h 2 1 = 0 after algebra g 1h1 = g 2h2 To minimize the delay by the choice of input load h1 The equal stage effor t (ie g 1h1 = g 2h2) generalizes to N stages Method for computing the logical effor t 14 October 2014

8 Care must be used to identify the critical path (normally the highest stage count) in multi-path circuits Selecting logic gate (NAND, NOR etc) determines the logical effor t Inver ter of some size nor malizes the effects of increasing output current Output and number of load sets transistor sizing 1) Compute the path effor t F = GBH 2) Estimate the stages N = log4 F ) Sketch path for N 4) Estimate least delay D = NF 1/N + P 5) Determine stage effor t ˆf = F 1/N 6) Find gate widths (sizes) Cin,i = gicout,i /ˆf 15 October 2014 Step 5 is the key step and comes from constrained sums and products Minimize the sum of f 1 + f... 2 and limit the product f 1 f... 2 to a constant fi = constant = F 1/N Sets the number of stages for driving specific output load Remember : Roughly delay isoptimized by effor t delays of 4 unit inverters Smaller gates (inverters and NANDs) best for large output loads Clar ification of drive versus size and interpretations for numer ical values shown in logic gate 16 October 2014

9 Dr ive strength x reflects multiple of unit current (from unit inverter) Total capacitance of a specific input Cin Te xteq4.24 assumes a new unit inverter and new g from or iginal Cin,inv = tocin,inv = 1 x = C in g when Cin,inv = 1 Iprefer to retain one definition for unit inverter and original g x = Cin g Cin,inv when Cin,inv = Example October x2 x4 x5 x c4=10 c5=12 d 1 = d 2 = d = d 4 = d 5 = x 2 7 x 4 4 x 2 7 x 4 5 x x 5 7 x 4 12 x x x October 2014

10 Limitations of the linear logic effor t model G and stages are dependent on each other No rise and fall times of the inputs (see laborator y) Interconnect adds a significant delay Optimization speed not power or area 19 October 2014