# EECS 312: Digital Integrated Circuits Final Exam Solutions 23 April 2009

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1 Signature: EECS 312: Digital Integrated Circuits Final Exam Solutions 23 April 2009 Robert Dick Show your work. Derivations are required for credit; end results are insufficient. Closed book. You may use a calculator. Honor Pledge: I have neither given nor received aid in this exam. 1. (10 pts.) k n = W µnɛox Lt ox When the move from SiO 2 to high-κ gate dielectric occurred, what qualitative changes were made to the variables upon which k n depends? You may assume that k n remains fixed. Use only a few sentence fragments for your answer. ɛ ox, t ox. Note: If you didn t get this one, please read the Spectrum article and the midterm solutions. 2. (10 pts.) Consider the following circuit: CLK Q CLK Q 1d CLK Q 1d 7d 7d 7d 7d The numbers near the logic gates indicate delays. Disconnected logic gate inputs may be assumed to be stable. Draw the gate- and latch-level diagram of a two-phase latch-based reimplementation of this circuit and indicate the minimal safe clock period. Do not change anything but the positions of the latches. You may neglect latch delays. CLK C Q C Q C Q 7d 7d 1d C Q Q CLK CLK CLK 7d CLK 7d CLK The clock period must clearly be greater than Given that n 1 p = 2 d i /n = 10d. i=0 φ i+1 = φ i p/2 + d i, we can compute the phase each stage: C C Q 1d φ 0 = 2d, φ 1 = 4d, φ 2 = 0d, φ 3 = 2d, φ 4 = 4d, φ 5 = 0d.

3 6. (10 pts.) Use the concept of logical effort to size the gates in the following circuit to minimize the delay for path A B. A 1C B 10C VSS You need not round your sizes. F = BGH 7/3 + 4/3 B = = 11 7/3 7 = 1.57 G = = 4.15 H = 10C/C = 10 F = ˆf = = 2.84 ĥ i = ˆf/g i ĥ 4 = 2.13 ĥ 3 = 2.13 ĥ 2 = 1.22 ĥ 1 = 2.84 h i = Cout i /Cin i Cin i = Cout i /h i Cin ˆ i = Cout ˆ i /ĥi Cin ˆ 4 = 10C/2.13 = 4.69C Cin ˆ 3 = 4.69C/2.13 = 2.20C Cin ˆ 2 = 2.20C/1.22 = 1.80C Cin ˆ 1.80C C 4/7 1 = = 1.00C (10 pts.) Draw a transistor-level diagram of a 3:8 decoder in which the transistors are sized to achieve the same output resistance to ground and V DD as an inverter with gate capacitance 3C. This is a set of three-input NOR gates in which the PMOSFETs have

4 gate capacitances of 6C and the NMOSFETs have gate capacitances of C. You may assume access to complemented input literals, but no credit will be taken off for those who include inverters in their designs. 8. (10 pts.) Draw the gate-level diagram of a rising edge triggered scan-flop, i.e., a flip-flop that can be used to support normal operation and scan-chain testing. You may use transistors in addition to logic gates. If sizing is essential for correct operation, label the appropriate gates and/or transistors as narrow and wide. combinational scan chain 2:1 MUX clk D Q test/operate Instead of showing all the possible designs of the D flip-flop and 2:1 MUX, the reader can refer to the textbook. 9. (10 pts.) Determine the worst-case delay from precharge disable to output transition for a single-bit cell in a four-word MOS NAND ROM. λ =125 nm. All gates are 2λ long and 4λ wide. Sources and drains are 3λ long and 4λ wide. Assume (1) a default 0.25 µm process, (2) all inputs experiences a perfect step voltage change, and (3) an output capacitance of 10 ff. See Figure on page 639 in the textbook (Rabaey et. al) for the NAND ROM schematic. We replace the grounded PMOS inputs with a precharge PMOS and add an NMOS footer below the NMOS stack. Note that if one assumes that the wordline inputs change before the end of the precharge period, the footer is not necessary. Assume that bits 0-2 store logic 1 values and bit 3 stores a logic 0 value. The worst case delay will occur when reading bit 3, because the output must discharge through the three NMOS controlled by wordlines 0 2 and the footer. Assume that bit 3 is implemented by a wire, as shown in Figure in the book. We compute the Elmore delay of the equivalent RC network. Note that when determining the capacitances, due to the step function (i.e., instantaneous) inputs we include only the diffusion caps and not gate caps. Many of the diffusion caps will only charge to V dd V th during precharge, but for Elmore delay calculations we assume they charge to the full V dd. This will result in acceptable error. The source and drain caps are given by Equation 3.45 on page 111 in the textbook. The PMOS drain cap is ff. The NMOS source and drain caps are ff. The NMOS equivalent resistance 6.5 kω.

5 Thus, the Elmore delay is given by 11.36f (4 6.5k) f (3 6.5k) f (2 6.5k) f (6.5k) which equals 0.35 ns.

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