Chapter 5 CMOS Logic Gate Design


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1 Chapter 5 CMOS Logic Gate Design Section 5. To achieve correct operation of integrated logic gates, we need to satisfy 1. Functional specification. Temporal (timing) constraint. (1) In CMOS, incorrect functions are caused by 1. Incorrect or insufficient power supplies or power supply noise.. Noise on gate input (so we need noise margin) 3. Faulty transistors 4. Faulty connections to transistors 5. Incorrect ratio in ratioed logic 6. Charge sharing or incorrect clocking dynamic gates In general, CMOS is tolerable to noise > safeness good choice for modern system  level Ic designs () A fair portion of the design cycle may be spent in optimizing the speed of the design. CLoad tf(tr, td) k β V eff DD where k is a constant (1.5~) β eff no.of transistors in parallel or serial e.g., in 3input NAND gate β β = n β = β 3 eff, p p eff, n, 00/5/3 1
2  Cload : Loading capacitance: the performance factor (1) Size of transistors in the gate (selfloading) () Size and number of transistors to which the gate is connected. (3) The routing capacitance own the gate and other the gates it drives Also, speed of gate will be affected by tr/tf of input waveform. * Check speed > Find the critical paths of your design: We can use timing analyzer to find the total delays along the critical paths. * Design Skills: (1) Algorithm level ((Poweroftwo coefficients instead of real multiplier) () Architecture level (e.g., Carry lookahead adder design v.s. Ripple adders) (3) RTL/logic gates (check pipelining, fanin, fanout, etc). (4) Circuitlevel level approaches (Logic AND/OR gates v.s. CMOS compound gates) (5) Good floorplanning (relationship between blocks and I/O pins) (6) Layoutlevel design skills (Fullcustom designs and automatic Placement and Routing (P&R)). * Most leveraged way is achieved by Design a good algorithm (e.g., Fast Discrete Cosine Transform in JPEG and MPEG) Novel architectural designs (minimize the critical paths) Registertransfer Level (RTL) designs: Describe your designs in terms of Gates, Basic operators (adders, multipliers, division units, etc.), and Delay elements. For example, MIPS CPU architecture and FIR filter architectures. 00/5/3
3 5..1 Fanin and Fanout of Logic gates (a) Fanin: Number of inputs e.g., 4input NAND gate has a fanin of 4; input NAND gate has a fanin of (it is known in advance.) (b) Fanout: Total number of gate inputs that are driven by a gate output. Default gate size=minimum sized inverter as unity. (c) Fanin and Fanout will be affected by stage ratio and transistors in parallel or serial (effective Beta values for NMOS and PMOS). 00/5/3 3
4 R tr = n p ( m n C + C + K C ) d r g Tr (rise time) for an minput NAND gate: a } m.pos b c a b vout (1) Rp: effective resistance of a pdevice in a unit inverter (size: L/W = 1/n) () n: width multiplier of PMOS (3) k: fanout (4) m: fanin (5) Cg: Gate capacitance of an k.inverters unit inverter. (6) Cd: Drain capacitance cg (7) Cr: Routing capacitance. c 00/5/3 4
5 R p Tr = (m n C r C g + q(k) C g + k C g ) n { {{ Drain cap Routing cap Fanout { where R: Cd/Cg: ratio of the intrinsic drain capacitance of an inverter to the gate Capacitance: q(k): Represent routing cap in terms of Cg 00/5/3 5
6 Sec. 5.. Example: (SPICE simulation) W n W p = 6µ, L n = 1.3µ, L = 1µ  T inputrise/fall =0.1ns  Cl=0 ~ 1pF =>NAND gate is a better choice than NOR gate p = 1µ => Fanin vs. delay => CL vs. Delay Example of an 8input NAND gate construction Approach1: An 8input NAND + an Inverter. Approach: Two 4input NAND + input NOR Approach3: see Figure 00/5/3 6
7 Trade off between Area, speed (and power?) Transistor sizing: stage ratio to drive large Cl (such as Clock Tree and Global Reset) Guideline: Start with minimum sized devices then optimize paths from a criticalpathtiming analysis. Optimizing paths can be done at different levels  Use NAND structures where possible  Place (big) inverters at high fanout nodes if possible  Avoid the use of NOR structures in highspeed circuits (fanin > 4 or fanout is large)  Use a fanout below Use minimumsized gate on high fanout nodes to minimize Cl presented to the driving gate.  Keep rising and falling edges sharp 00/5/3 7
8 5.4 CMOS Logic structures CMOS complementary logic Two function determining blocks: Nblock and Pblock n transistors for an ninput logic gate PseudoNMOS logic R (active load) a Z = A (B + C) + ( D E) d e b c *need (n+1) transistors 00/5/3 8
9 5.4.4 Dynamic CMOS Logic Z = { 0, nblock short 1, nblock open clk=0, Z=1 (C L is charged to vdd) clk=1, Z is conditionally evaluated { CLK is a singlephase clock Pullup time is improved. Pulldown time is increased due to the ground switch. Problems: (a) Inputs can only change during the precharge phase and must be stable during the precharge phase => charge sharing may corrupt the output node voltage. (b) Simple singlephase dynamic CMOS gates cannot be cascaded (some delay between N1&N) 00/5/3 9
10 Precharge Evaluate Old value = nlogic is short New vlaue = nlogic is open Clocked CMOS Logic C MOS PassTransistor Logic F = PV i i i P V V i i i = = Control _ signals Pass _ signals { 0,1, X, X, Z } i i F = P V ) + P ( V ) + L + 1( 1 P n ( Vn ) 00/5/3 10
11 Example1: Use passtransistor logic to design a input XNOR gate (a) Truth table (b) Passnetwork Karnaugh map (c) Logic function Use: A as the control signals B as the passed signals F = A ( B) + A ( B) (d) Implementation (a) Complementary (b) NMOS (c) Crosscoupled Example: Use passtransistor logic to construct Boolean function (a) Truth Table 00/5/3 11
12 (b) Implementation: The apparent advantages of passtransistor networks in CMOS should be studied carefully (e.g., how to achieve good logic levels?) CMOS Domino Logic (1) During precharge (clk=0), PZ=1, and inverter o/p=0 () Transistors in subsequent logic blocks will be turned off during the precharge phase (3) Each gate in sequence can make at most one transition (1 to 0) => Can be used in cascaded logic gates 00/5/3 1
13 Limitations: (1) Each gate must be buffered (an advantage, too) () Only noninverting structures are possible (3) Common in dynamic CMOS charge sharing Charging sharing problem in Dynamic CMOS C A 0 1 C 5 Q in C Q in C = low = low A = high when clk = 1 is dumpedinto C C 7 V n1 IF C = 1 ( C 7 i= 1 V C ) + C = 3 C i DD 1 & C = C 3 = C 4 = C 5 = C 6 = C 7 then V n1 = 3C 6C + 3C V DD = 0.33V DD = 1.65V turn onthe inverter Solution: (a) Place clocked NMOS at (a) the Place bottom clocked NMOS at the (b) bottom Provide immediate nodes (b) with Provide their immediate own nodes with precharging their own precharging transistors 00/5/3 13
14 5.4.8 NP domino logic (Zipper CMOS) Will turn off next stages during precharging Advantage of D. CMOS (1) Smaller area () C, speed (3) Glitch free if design carefully 5.5 Clocking strategies (a) FSM (Finite State Machine) (b) Pipelined system 00/5/3 14
15 (a) Setup time: the time before the clock edge that the D input has to be stable (b) Hold time: the time after tue clock edge that the Dinput has to main stable (c) ClocktoQ delay (Tq): the delay from the positive clock input to the new value of the Q output. Latches (a) Negative levelsensitive latch (b)positivelevelsensitive latch (c)positive edgetriggered register(masterslave) (d) Operation of the masterslave register (e) CMOS circuit implementation. Keep Q Keep D value 00/5/3 15
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