Topics to be Covered. capacitance inductance transmission lines

Transcription

1 Topics to be Covered Circuit Elements Switching Characteristics Power Dissipation Conductor Sizes Charge Sharing Design Margins Yield resistance capacitance inductance transmission lines

2 Resistance of uniform slabs: R = ρ L / tw ohms ρ = resistivity t = thickness Define Sheet Resistance : R S = ρ/t ohms/square R = R S (L/W) Resistance Calculations

3 Table 4.1 Typical sheet resistances for conductors Sheet Resistance ohm/sq. Material Min. Typical Max. Metal (Al) Silicides Diffusion (n+ and p+) Polysilicon CMOS3 n+ diffusion p+ diffusion * poly CMOS4S metal * Note: Doping poly p+ increases R S by approx. 40%

4 Transistor Channel Resistance In the linear region, approximate: R C = k L/W where k = [µ(ε 0 ε r /t ox ) (V GS - V t )] -1 Typical k = ohms/sq. Approximate CMOS4S: n-channel 2250 p-channel 4500

5 Contact Resistance Typical values: CMOS1B CMOS4S n+ diff contact 5-10 Ω 20 Ω p+ diff contact 5-12 Ω 20 Ω poly (n+ doped) 1 Ω 10 Ω poly (p+ doped) 5-20 Ω 10 Ω metal 1 - metal 2.12 Ω

6 Other Electrical Parameters Resistance ohms/sq. n+ diffusion 45 p+ diffusion 100 n+ poly 30 p+ poly 45 n-well 1.8k (geometry and voltage dependent) metal metal metal 1 - diffusion contacts 20 ohms (1.2 x 1.2 microns)* metal 1 - poly contacts 10 ohms (1.2 x 1.2 microns)* metal 1 - metal 2 vias ohms (1.6 x 1.6 microns)* * physical dimensions, not design scale dimensions

7 Capacitance Area Component (pf/um 2 )* Edge Component (pf/um)* metal 1 - field 2.9E E-5 metal 1 - poly 6.0E-5 metal 1 - diffusion 5.5E-5 poly - field 6.4E E-5 metal 2 - field 1.6E E-5 metal 2 - poly 2.5E-5 metal 2 - diffusion 2.0E-5 metal 2 - metal 1 5.2E-5 capacitor poly to poly 7.76E E-4 *physical dimensions, not design scale dimensions

8 MOS Capacitor Transistor Gates Silicon surface can be in one of 3 modes: 1. Accumulation (V G < 0 for n-device) C 0 = ε 0 ε ox /t ox * A (ε ox is approx. 3.9) 2. Depletion (0 < V G < V t ) Depletion layer of depth d formed under gate. d depends on gate voltage. Effect is C 0 in series with C DEP : C DEP = ε 0 ε SI (A/d) (ε SI is approx. 12) C GB = C 0 C DEP /(C 0 + C DEP ) C DEP decreases with voltage

9 3. Inversion (V G > V t ) Conductive channel restores C GB to C 0 for low frequencies only (< 100 hz) At high frequency, minority carrier mobility gets in the way and behaves like maximum inversion.

10 Transistor Parasitic Capacitance C GS, C GD C DB, C SB C GB Gate-to-channel, lumped at source/drains Diffusion-to-bulk Gate-to-bulk

11 Transistors Parasitic Capacitances (con t) Figure 4.5 Circuit symbols for parasitic capacitances

12 C a p a c i t a n c e P a r a m e t e r O f f L i n e a r S a t u r a t i o n C GB C 0 GS C 0 GD C = C + C + C G GB GS GD ε A 0 0 t OX ε A 2 ε A 2 t 2 t A 3 t ε A ε A 2 ε A t ε t OX OX 0 OX 3 t OX OX OX ε = ε 0 * ε OX i.e.: C G is approx. C 0 Typical = 0.01pF

13 Diffusion Capacitance C ja = area capacitance C jp = peripheral capacitance C D = (C ja )(ab) + (C jp )(2a + 2b) note: (ab) = area ; (2a + 2b) = perimeter *see next slide for basic structure

14 Diffusion Capacitance (con t)

15 Typical Values: C ja (pf/µm 2 ) C jp (pf/µm) MOS1S n-diff. 1 x x 10-4 MOS1S p-diff. 1 x x 10-4 CMOS3 n 4.4 x x 10-4 CMOS3 p 1.5 x x 10-4 CMOS4S n 2.9 x x 10-4 CMOS4S p 4.1 x x 10-4 note: in spice C ja = CJ and C jp = CJSW

16 Inductance Normally not a problem for on-chip wires. Can be a problem for bonding wires. On-chip L = 20 ph/mm Bonding wire and package inductance = 3-15 nh. V = LdI/dt = (5nH)(2.5mA)/(1ns) = 12.5mV Only a problem for high performance chips.

17 Metal / Poly to substrate Parallel plate model: Routing Capacitance C = (ε / t) A But fringing effect gives rise to a perimeter component similar to sidewall cap in diffusion. CMOS3 Data: C A (pf / µm 2 ) C P (pf / µm) Metal field 2.7 x x 10-4 Poly field 6.0 x x 10-4

18 Distributed RC Effect in Wires C dv dt j = (I - I ) j-1 j j-1 j j j+1 = (V - V ) R - (V - V ) R rc dv dt = d 2 V 2 dx where x = distance from input r = resistance per unit legth c = capacitance per unit length

19 Distributed RC Effect in Wires

20 Solving for propagation time of voltage step along wire of length x: t X = k x 2 Alternate solution of: t n = 1/2 (R C n(n+1)) As n = # of sections approaches infinity the alternate solution becomes: t l = 1/2 (r c l 2 ) where r = resistance per µ c = capacitance per µ l = length (µ) The result may be that it is desirable to break long signals into shorter segments with buffers inserted.

21 *continued from last slide Note: Both R and C are important here!! It is helpful to know gate caps, etc.

22 Guideline: Keep wire delay τ W well under gate delay τ G i.e.: τ W << τ G therefore l << sqrt(2 τ G / rc) For τ G = 2 nsec and typical parameters, we get the following as a guidline:

23 Switching Characteristics t r = time 10% to 90% t f = time 90% to 10% t d = delay from input transition to output transition (50%) t r = time 10% to 90% t f = time 90% to 10% t d = delay from input transition to output transition (50%)

24 Delay Time Delay of single gate dominated by output rise and fall time t dr = t r /2 t df = t f /2 Average gate delay t av = (t df +t dr )/2 = (t r + t f )/4 For more accuracy use analytical or emperical models.

25 Switching Characteristics (con t) Circuit Model:

26 Switching Characteristics (con t) Fall Time: t = 0 : V 0 = V DD V IN = 0 C L charged V IN goes to V DD p-transistor goes to off.

27 Switching Characteristics (con t)

28 Switching Characteristics (con t) Two phases: 1. T 1 saturated C L dv 0 /dt + β n /2 (V DD - V tn ) 2 = 0 V 0 >= V DD - V tn 2. T 1 linear Approximate Solution: V t = 1 V ; V DD = 5 V t f is approx. 4 C L / (β n V DD )

29 Emperical Delay Models t f = A N C L t r = A P C L β N A N and A P are derived from SPICE simulations from different transistors Note: A/B is an effective resistance, t f & t r are RC - delays Gate Delays series transistors: 1 / β eff = 1 / β / β parallel transistors: β eff = β 1 + β t f =t r requires b n = b p or W p = 2W n if L p = L n (for CMOS4S) Logic simulators will use a delay vs. load capacitance model for each type of gate. e.g.: β P

30 Thus for this gate the delay equations would be t = k r t = k f 2.12 ns (k is in pf) 3.82 ns (k is in pf)

31 Switch Level Models Model every transistor as a resistor. Simple RC s to determine delays in a circuit.

32 Switch Level Models (con t)

33 SPICE Example Transient Analysis of CMOS Inverter Note: C OUT is gates of load inverter Gate area = (3 x 3) + (3 x 5.4) = 25.2 µ 2 Gate cap = 25.2 x = pf

34

35 Cascaded Stages - It is better to drive a large load with a number of inverters (which increase in size) than with a single small inverter - Stage ratios vary from 2-10 with approx. 2.7 giving optimum speed Power Dissipation Static - Leakage currents ( na) per device P S is approx nw Dynamic - Switching transient current - Charge and discharge of load capacitance P D = C L V DD2 f P For large circuits difficult to estimate what percentage of nodes are switching, typically assume 50% if unknown

36 Conductor Sizes - Always metal power lines - Metal migration : current density < 0.25 ma/µm - Power supply noise - RC delay : power and ground bounce - Large number of small contacts (vias) when changing layers Charge Sharing C B C S - to ensure reliable charge transfer C B > 10 C S

37 Design Margins - Temperature: commercial : 0-70 o C industrial military - Supply Voltage +/- 10% - Process Variations 2-3σ : o C : o C see next slide for the diagram

38 Design Margins (con t) Figure 4.41 The distribution of process parameters

39 - Design corners - simulate circuits at all appropriate corners checking maximum speed, power, setup and hold times, timing hazards, race conditions, etc. Yield number of good chips Y= X 100% total number of chips Depends on : technology : chip area : layout

40 Two common models AD Y = e Small Chips Y > 30% Y = 1 - e AD -AD 2 Large Chips Y < 30% A = area of chip D = defect density (i.e.: lethal defects per cm 2 ) D is typically 1-5 defects per cm 2 - Yield can be improved by the incorporation of redundant structures.

41 Logic Structures - complementary static CMOS : large area : slow : always works - alternate structures : smaller : faster : increased complexity : decreased stability Example Function Z = (A B) + C

42 - pseudo NMOS 1. similar to NMOS 2. ratioed logic 3. power dissipation (static) 4. reduced noise margins 5. 1/2 transistor 6. t f smaller due to reduced load capacitance

43 - dynamic CMOS 1. precharge and evaluate phase 2. pull-down time increased 3. input can change only during recharge 4. cannot be cascaded 5. 1/2 transistors 6. dynamic (minimum clock) 7. charge redistribution

44 - domino logic 1. similar to dynamic CMOS 2. two extra transistors 3. extra inverter delay 4. stages can be cascaded 5. stages evaluate one after another (domino) 6. non-inverting structures only

45 - pass transistor logic 1. reduced transistors 2. no supply current 3. require complementary signals for inputs 4. smaller load capacitances

46 Inverter Layouts

47 Inverter Layouts (cont.)

48 NAND

49 NOR

50 Important Factors to Consider for Complex Gates Series Transistors Connections Body Effect Source-Drain Capacitance Charge Distribution

51

52 1. Series Connection

53 2. Body Effect

54 3. Source-Drain Connections

55 4. Charge Redistribution Routing to a transmission gate 2-input multiplexer a) circuit, b) poly select lines (with metal crossover) a) b)

56 Charge Redistribution (con t) Figure input multiplexer layouts

57 Summary complementary logic is the best option in most CMOS circuits noise immunity low DC power dissipation generally fast creation is highly automated pseudo-nmos finds use in large fan-in NOR gates e.g. ROMs, PLAs, carry look-ahead adders

58 Summary (cont.) higher static power dissipation clocked CMOS logic offers some relief for hot electron processes and conditions pass logic is fast if structures are limited to a few series transmission gates no CAD support for synthesis

59 Summary (cont.) domino logic useful for low-power high speed applications charge redistribution requires lots of simulation/development time speed advantage diminishes in poorly designed clock schemes (i.e. precharge time)

60 Pseudo 2-phase clocking: a) waveforms and special latching

61 Pseudo 2-phase clocking b) clockskew and c) slow clock edges

62 2-phase flip-flop and skew reduction

63

64 Dynamic Flip Flop

65 Static Flip-Flop

66 Static Latch

67 Static D flip-flop Table 5.5 Static D flip-flop set/reset truth table INPUTS OUTPUT CL D R S Q X X X X X X 1 1 NA

68 Recommended Clocking Approaches For first time designs that use mostly static logic, use single phase clocking and selfcontained static registers standard cells gate arrays For RAM s, ROM s and PLA s, use two phase clocking In the past, it guaranteed correct latch behaviour and dynamic latch operation

69 Recommended Clocking Approaches (cont.) Today, cycle times are very short difficult to guarantee non-overlap in all process corners Use single phase clocking for complex high-speed CMOS circuits generate special clock needs locally Use alternative clocking schemes only in special circumstances

70 I/O Pads design required detailed circuits and process knowledge use library functions pads have constant height (power connections) bonding pad 150µ x 150µ (double bond to power)

71 Pads (cont.) Types of Pads input output tristate I/O V DD GND analog

72 Pads (cont.) families of pads with different sizes ring and core supplies multiple supplies for a large number of I/O s > 40 pins 2 sets reduce noise, IR drops automatic frame programs to generate pad ring resistance and protection diodes are to prevent damage from ESD TTL requires switching threshold near 1.4volts

73 Tristate Pad

74 V DD and GND Pads simple pads made out of metal generally placed as far away from each other as possible

75 Output Pads even number of inverters size of inverters dictated by drive requirements can drive either CMOS or TTL

76 Input Pads