EE241  Spring 2001 Advanced Digital Integrated Circuits


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1 EE241  Spring 21 Advanced Digital Integrated Circuits Lecture 12 Low Power Design SelfResetting Logic Signals are pulses, not levels 1
2 SelfResetting Logic SenseAmplifying Logic Matsui, JSSC 12/94 2
3 SAF/F Falling edge Rising edge Dynamic Logic with SAF/F 3
4 Example 4Bit Adder 4
5 2Bit CarrySkip Adder GHz Logic with Sense Amplifiers Takahashi, JSSC 5/99 5
6 Readout scheme Implemented Macros 6
7 Rotator (ROT) Incrementer (INC) 7
8 Low Power, Low Energy Circuit Design Architectures, Circuits and Technology Literature Chapter 4, LowVoltage Technologies, by Kuroda and Sakurai Chapter 3, Techniques for Leakage Power Reduction, by De, et al. A. Chandrakasan and R. Brodersen, Low Power CMOS Design, Kluwer Academic Publishers, J. Rabaey and M. Pedram, Ed., Low Power Design Methodologies, Kluwer Academic Publishers, Proceedings of the IEEE, Special Issue on Low Power, April A. Chandrakasan and R. Brodersen, LowPower CMOS Design, IEEE Press, 1998 (Reprint Volume) 8
9 Power vs. Energy Power in high performance systems» Peak power  power delivery, removal Energy in portable systems» Battery life Constant throughput vs. burstmode computation Active vs. standby consumption Principles of Power Reduction P ~ α + ( C V + I t ) L swing ( I + I ) V DD DC Leak a  switching probability C L load capacitance V swing voltage swing f  frequency SC SC V DD I sc mean value of switching transient current t sc short current time I DC static current I leak leakage current f Dominant: P ~ α C L V swing V DD f Kuroda, Sakurai, IEICE 4/95 9
10 P ~ α C Active Power Reduction L V swing V DD Reducing switching probability (α)» Architectures» Power simulators/estimators (time consuming)» Glitching power reduction (152%) Reducing load capacitance» Technology scaling» Gate sizing, minimization, interconnect, CAD» Circuit techniques (PTL, ) Reducing supply voltage» Quadratic impact on power» Impact on delay how to maintain throughput? Reducing frequency f E ~ α C L V swing V DD Trends in Power Dissipation 1 x1.4 / 3 years 1 κ.7 Power Dissipation (W) x4 / 3 years 85 (a) Power dissipation vs. year. 9 Year MPU DSP 95 Power Density (mw/mm 2 ) 1 1 κ Scaling Factor κ inormalized by 4µm design rule j 1 (b) Power density vs. scaling factor. From Kuroda 1
11 Processor Power 1 Max Power (Watts) Pentium II (R) Pentium Pro (R) Pentium(R) 486 Pentium(R) MMX? m 1m.8m.6m.35m.25m.18m.13m Lead processor power increases every generation Compactions provide higher performance at lower power Power will be a problem Power (Watts) Pentium proc 18KW 5KW 1.5KW 5W Year Power delivery and dissipation will be prohibitive S. Borkar 11
12 Portability BATTERY (4+ lbs) Multimedia Terminals Laptop Computers Digital Cellular Telephony Nominal Capacity (Watthours / lb) Rechargable Lithium NickelCadium NiMetal Hydride Year Expected Battery Lifetime increase over next 5 years: 34% Shannon Beats Moore s Law Algorithmic Complexity (Shannon s Law) 3G Processor Performance (~Moore s Law) 1 2G G Battery Capacity Source: Data compiled from multiple sources
13 Where Does Power Go in CMOS? Dynamic Power Consumption Charging and Discharging Capacitors Leakage Leaking transistors and diodes Short Circuit Currents Short Circuit Path between Supply Rails during Switching Dynamic Power Consumption V dd E >1 = C L V dd 2 PMOS i supply A 1 NETWORK A N NMOS NETWORK V out C L E 1 T T Vdd = Pt ()dt = V i t dd supply ()dt = V C dv dd = C V L out L 2 dd T T Vdd 1 2 E = P t cap cap ()dt = V i t out cap ()dt = C V dv =  C V L out out 2 L dd 13
14 Circuits with Reduced Swing V dd V dd V dd V t C L E 1 = C L V dd ( V dd V t ) Can exploit reduced swing to lower power (e.g., reduced bitline swing in memory) Dynamic Power Consumption  Revisited Power = Energy/transition * transition rate = C L * V dd 2 * f 1 = C L * V dd 2 * P 1 * f = C EFF * V dd 2 * f Power Dissipation is Data Dependent Function of Switching Activity C EFF = Effective Capacitance = C L * P 1 14
15 Node Transition Activity and Power Consider switching a CMOS gate for N clock cycles E N = C L V 2 dd nn ( ) E N : the energy consumed for N clock cycles n(n): the number of >1 transition in N clock cycles P = lim avg N E N f N clk = nn ( ) lim C N N V fclk L dd α 1 = nn ( ) lim N N P avg = α 1 C L V 2 dd fclk Type of Logic Function: NOR vs. XOR 15
16 Type of Logic Function: NOR vs. XOR Transition Probabilities P >1 (NOR,NAND) = (2 N 1)/2 2N P >1 (XOR) = 1/4 16
17 Transition Probabilities for Basic Gates Transition Probability of 2input NOR Gate 17
18 How about Dynamic Circuits? V DD φ M p Out In 1 In 2 In 3 PDN φ M e Power is Only Dissipated when Out=! C EFF = P(Out=).C L 2input NAND Gate Example: Dynamic 2 Input NOR Gate Assume: P(A=1) = 1/2 P(B=1) = 1/2 Then: P(Out=) = 3/4 C EFF = 3/4 * C L Switching Activity Is Always Higher in Dynamic Circuits 18
19 Type of Logic Style: Static vs. Dynamic V dd V dd A CLK B A B C L A B C L CLK Power is only dissipated when Out=! STATIC NOR DYNAMIC NOR α >1 = 3/16 N α 1 = N = Transition Probabilities for Dynamic Gates Switching Activity for Precharged Dynamic Gates P 1 = P 19
20 Another Logic Style: Dynamic DCVSL V dd V dd OUTB IN INB I OUT I Guaranteed transition for every operation! α >1 = 1 Problem: Reconvergent Fanout A X B Z Reconvergence P(Z=1) = P(B=1). P(X=1 B=1) Becomes complex and intractable real fast 2
21 Glitching in Static CMOS also called: dynamic hazards A B X C Z ABC 11 X Z Unit Delay Observe: No glitching in dynamic circuits Example 1: Chain of NOR Gates 1 out1 out2 out3 out4 out V (Volt) out2 out8 out6 out4 out1 out3 out5 out t (nsec) 21
22 Example 2: Adder Circuit C in Add Add1 Add2 Add14 Add15 S S1 S2 S14 S15 Sum Output Voltage, Volts Cin S1 S Time, ns S15 How to Cope with Glitching? F 1 1 F 2 2 F 3 F 1 F F 3 Equalize Lengths of Timing Paths Through Design 22
23 Example: Carry Ripple versus Carry Lookahead A F A 1 A 2 A 3 A 4 A 5 A 6 A 7 Ripple A A 1 A 2 A 3 A 4 A 5 A 6 A 7 F Lookahead 23
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