ΗΜΥ 307 ΨΗΦΙΑΚΑ ΟΛΟΚΛΗΡΩΜΕΝΑ ΚΥΚΛΩΜΑΤΑ Εαρινό Εξάμηνο 2018

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1 ΗΜΥ 307 ΨΗΦΙΑΚΑ ΟΛΟΚΛΗΡΩΜΕΝΑ ΚΥΚΛΩΜΑΤΑ Εαρινό Εξάμηνο 2018 ΔΙΑΛΕΞΕΙΣ 12-13: esigning ynamic and Static CMOS Sequential Circuits ΧΑΡΗΣ ΘΕΟΧΑΡΙΔΗΣ (ack: Prof. Mary Jane Irwin and Vijay Narayanan) [Προσαρμογή από Rabaey s igital Integrated Circuits, 2002, J. Rabaey et al. ]

2 Review: How to Choose a Logic Style l Must consider ease of design, robustness (noise immunity), area, speed, power, system clocking requirements, fan-out, functionality, ease of testing 4-input NAN Style # Trans Ease Ratioed? elay Power Comp Static 8 1 no 3 1 CPL* no 4 3 domino no CVSL* 10 3 yes 1 4 * ual Rail q Current trend is towards an increased use of complementary static CMOS: design support through A tools, robust, more amenable to voltage scaling. q CPL Complementary Pass-Transistor Logic q ynamic Cascade Voltage Swing (Logic) ΗΜΥ307 Δ12-13: ynamic& Static CMOS Sequential Circuits.2 Θεοχαρίδης, ΗΜΥ, 2018

3 Sequential Logic REVIEW Inputs Combinational Logic Outputs Current State State Registers Next State clock ΗΜΥ307 Δ12-13: ynamic& Static CMOS Sequential Circuits.3 Θεοχαρίδης, ΗΜΥ, 2018

4 Timing Metrics In Q Out clock clock t su t hold time In data stable t c-q time Out output stable output stable time ΗΜΥ307 Δ12-13: ynamic& Static CMOS Sequential Circuits.4 Θεοχαρίδης, ΗΜΥ, 2018

5 System Timing Constraints Inputs Combinational Logic Outputs Current State State Registers Next State clock T (clock period) t cdreg + t cdlogic ³ t hold T ³ t c-q + t plogic + t su ΗΜΥ307 Δ12-13: ynamic& Static CMOS Sequential Circuits.5 Θεοχαρίδης, ΗΜΥ, 2018

6 Static vs ynamic Storage l Static storage preserve state as long as the power is on have positive feedback (regeneration) with an internal connection between the output and the input useful when updates are infrequent (clock gating) l ynamic storage store state on parasitic capacitors only hold state for short periods of time (milliseconds to nanoseconds) require periodic refresh usually simpler, so higher speed and lower power ΗΜΥ307 Δ12-13: ynamic& Static CMOS Sequential Circuits.6 Θεοχαρίδης, ΗΜΥ, 2018

7 Latches vs Flipflops l Latches level sensitive circuit that passes inputs to Q when the clock is high (or low) - transparent mode input sampled on the falling edge of the clock is held stable when clock is low (or high) - hold mode l Flipflops (edge-triggered) edge sensitive circuits that sample the inputs on a clock transition positive edge-triggered: 0 1 negative edge-triggered: 1 0 built using latches (e.g., master-slave flipflops) ΗΜΥ307 Δ12-13: ynamic& Static CMOS Sequential Circuits.7 Θεοχαρίδης, ΗΜΥ, 2018

8 Review: The Regenerative Property V i1 V o1 V i2 V o2 cascaded inverters V i2 = V o1 A C B If the gain in the transient region is larger than 1, only A and B are stable operation points. C is a metastable operation point. V i1 = V o2 ΗΜΥ307 Δ12-13: ynamic& Static CMOS Sequential Circuits.8 Θεοχαρίδης, ΗΜΥ, 2018

9 Bistable Circuits l The cross-coupling of two inverters results in a bistable circuit (a circuit with two stable states) V i1 V i2 q Have to be able to change the stored value by making A (or B) temporarily unstable by increasing the loop gain to a value larger than 1 done by applying a trigger pulse at V i1 or V i2 the width of the trigger pulse need be only a little larger than the total propagation delay around the loop circuit (twice the delay of an inverter) q Two approaches used cutting the feedback loop (mux based latch) overpowering the feedback loop (as used in SRAMs) ΗΜΥ307 Δ12-13: ynamic& Static CMOS Sequential Circuits.9 Θεοχαρίδης, ΗΜΥ, 2018

10 Review (from ECE 210): SR Latch S R!Q Q S R Q!Q 0 0 Q!Q memory set reset disallowed ΗΜΥ307 Δ12-13: ynamic& Static CMOS Sequential Circuits.10 Θεοχαρίδης, ΗΜΥ, 2018

11 Review (from CSE 210): Clocked Latch!Q Q Latch Q clock transparent mode clock clock hold mode ΗΜΥ307 Δ12-13: ynamic& Static CMOS Sequential Circuits.11 Θεοχαρίδης, ΗΜΥ, 2018

12 MUX Based Latches q Change the stored value by cutting the feedback loop feedback feedback 1 0 Q Q 0 1 Negative Latch Positive Latch Q = & Q! & transparent when the clock is low Q =! & Q & transparent when the clock is high ΗΜΥ307 Δ12-13: ynamic& Static CMOS Sequential Circuits.12 Θεοχαρίδης, ΗΜΥ, 2018

13 TG MUX Based Latch Implementation! Q input sampled (transparent mode) Latch Q! feedback (hold mode) ΗΜΥ307 Δ12-13: ynamic& Static CMOS Sequential Circuits.13 Θεοχαρίδης, ΗΜΥ, 2018

14 PT MUX Based Latch Implementation!Q Q! q Reduced clock load, but threshold drop at output of pass transistors so reduced noise margins and performance! input sampled (transparent mode) feedback (hold mode) ΗΜΥ307 Δ12-13: ynamic& Static CMOS Sequential Circuits.14 Θεοχαρίδης, ΗΜΥ, 2018

15 State Registers Latch Race Problem Combinational Logic B B B Which value of B is stored? Two-sided clock constraint T ³ t c-q + t plogic + t su T high < t c-q + t cdlogic ΗΜΥ307 Δ12-13: ynamic& Static CMOS Sequential Circuits.15 Θεοχαρίδης, ΗΜΥ, 2018

16 Master Slave Based ET Flipflop FF Q 0 1 Q 1 Q 0 M Slave Master clock = 0 transparent hold Q M = 0 1 hold transparent Q ET Edge Triggered ΗΜΥ307 Δ12-13: ynamic& Static CMOS Sequential Circuits.16 Θεοχαρίδης, ΗΜΥ, 2018

17 MS ET Implementation Master Slave I 2 T 2 I 3 I 5 T 4 I 6 Q Q M I 1 T 1 T 3 I 4 master transparent slave hold master hold slave transparent! ΗΜΥ307 Δ12-13: ynamic& Static CMOS Sequential Circuits.18 Θεοχαρίδης, ΗΜΥ, 2018

18 MS ET Timing Properties l Assume propagation delays are t pd_inv and t pd_tx, that the contamination delay is 0, and that the inverter delay to derive! is 0 l Set-up time - time before rising edge of that must be valid 3 * t pd_inv + t pd_tx l Propagation delay - time for Q M to reach Q t pd_inv + t pd_tx l Hold time - time must be stable after rising edge of zero ΗΜΥ307 Δ12-13: ynamic& Static CMOS Sequential Circuits.20 Θεοχαρίδης, ΗΜΥ, 2018

19 More Precise Setup Time ΗΜΥ307 Δ12-13: ynamic& Static CMOS Sequential Circuits.21 Θεοχαρίδης, ΗΜΥ, 2018

20 Setup/Hold Time Illustrations Circuit before clock arrival (Setup-1 case) CN TG1 1 S M Inv2 Q M Clk-Q elay Inv1 CP T Clk-Q ata Clock T Setup-1 Time T Setup-1 t=0 Time ΗΜΥ307 Δ12-13: ynamic& Static CMOS Sequential Circuits.22 Θεοχαρίδης, ΗΜΥ, 2018

21 Setup/Hold Time Illustrations Circuit before clock arrival (Setup-1 case) CN TG1 1 S M Inv2 Q M Clk-Q elay Inv1 CP T Clk-Q ata Clock T Setup-1 Time T Setup-1 t=0 Time ΗΜΥ307 Δ12-13: ynamic& Static CMOS Sequential Circuits.23 Θεοχαρίδης, ΗΜΥ, 2018

22 Setup/Hold Time Illustrations Circuit before clock arrival (Setup-1 case) CN TG1 1 S M Inv2 Q M Clk-Q elay Inv1 CP T Clk-Q ata Clock T Setup-1 Time T Setup-1 t=0 Time ΗΜΥ307 Δ12-13: ynamic& Static CMOS Sequential Circuits.24 Θεοχαρίδης, ΗΜΥ, 2018

23 Setup/Hold Time Illustrations Circuit before clock arrival (Setup-1 case) CN TG1 1 S M Inv2 Q M Clk-Q elay Inv1 T Clk-Q CP ata Clock T Setup-1 Time T Setup-1 t=0 Time ΗΜΥ307 Δ12-13: ynamic& Static CMOS Sequential Circuits.25 Θεοχαρίδης, ΗΜΥ, 2018

24 Setup/Hold Time Illustrations Circuit before clock arrival (Setup-1 case) CN TG1 1 S M Inv2 Q M Clk-Q elay T Clk-Q Inv1 CP ata Clock T Setup-1 Time T Setup-1 t=0 Time ΗΜΥ307 Δ12-13: ynamic& Static CMOS Sequential Circuits.26 Θεοχαρίδης, ΗΜΥ, 2018

25 Setup/Hold Time Illustrations Hold-1 case CN TG1 1 S M Inv2 Q M Clk-Q elay Inv1 CP 0 T Clk-Q Clock ata T Hold-1 Time T Hold-1 t=0 Time ΗΜΥ307 Δ12-13: ynamic& Static CMOS Sequential Circuits.27 Θεοχαρίδης, ΗΜΥ, 2018

26 Setup/Hold Time Illustrations Hold-1 case CN TG1 1 S M Inv2 Q M Clk-Q elay Inv1 CP 0 T Clk-Q Clock ata T Hold-1 Time T Hold-1 t=0 Time ΗΜΥ307 Δ12-13: ynamic& Static CMOS Sequential Circuits.28 Θεοχαρίδης, ΗΜΥ, 2018

27 Setup/Hold Time Illustrations Hold-1 case CN TG1 1 S M Inv2 Q M Clk-Q elay Inv1 CP 0 T Clk-Q T Hold-1 Time Clock ata T Hold-1 t=0 Time ΗΜΥ307 Δ12-13: ynamic& Static CMOS Sequential Circuits.29 Θεοχαρίδης, ΗΜΥ, 2018

28 Setup/Hold Time Illustrations Hold-1 case CN TG1 1 S M Inv2 Q M Clk-Q elay Inv1 T Clk-Q CP 0 Clock T Hold-1 ata T Hold-1 Time t=0 Time ΗΜΥ307 Δ12-13: ynamic& Static CMOS Sequential Circuits.30 Θεοχαρίδης, ΗΜΥ, 2018

29 Setup/Hold Time Illustrations Hold-1 case CN TG1 1 S M Inv2 Q M T Clk-Q Clk-Q elay Inv1 CP 0 Clock T Hold-1 ata T Hold-1 Þ Time t=0 Time ΗΜΥ307 Δ12-13: ynamic& Static CMOS Sequential Circuits.31 Θεοχαρίδης, ΗΜΥ, 2018

30 Set-up Time Simulation Q Q M t setup = 0.21 ns Volts I 2 out Time (ns) works correctly ΗΜΥ307 Δ12-13: ynamic& Static CMOS Sequential Circuits.32 Θεοχαρίδης, ΗΜΥ, 2018

31 Set-up Time Simulation Q I 2 out t setup = 0.20 ns Volts Time (ns) Q M fails ΗΜΥ307 Δ12-13: ynamic& Static CMOS Sequential Circuits.33 Θεοχαρίδης, ΗΜΥ, 2018

32 Propagation elay Simulation t c-q(lh) = 160 psec 1.5 Volts 1 t c-q(lh) t c-q(hl) t c-q(hl) = 180 psec Time (ns) ΗΜΥ307 Δ12-13: ynamic& Static CMOS Sequential Circuits.34 Θεοχαρίδης, ΗΜΥ, 2018

33 Reduced Load MS ET FF q Clock load per register is important since it directly impacts the power dissipation of the clock network. q Can reduce the clock load (at the cost of robustness) by making the circuit ratioed! T 1 I 1 Q M T 2 I 3 Q I 2 I 4! reverse conduction to switch the state of the master, T 1 must be sized to overpower I 2 to avoid reverse conduction, I 4 must be weaker than I 1 ΗΜΥ307 Δ12-13: ynamic& Static CMOS Sequential Circuits.35 Θεοχαρίδης, ΗΜΥ, 2018

34 Non-Ideal Clocks!! Ideal clocks Non-ideal clocks clock skew 1-1 overlap 0-0 overlap ΗΜΥ307 Δ12-13: ynamic& Static CMOS Sequential Circuits.36 Θεοχαρίδης, ΗΜΥ, 2018

35 Example of Clock Skew Problems X! Q P 1 A P 3 I 1 I 2 I 3 I 4!Q P 2 B P 4! Race condition direct path from to Q during the short time when both and! are high (1-1 overlap) Undefined state both B and are driving A when and! are both high ynamic storage when and! are both low (0-0 overlap) ΗΜΥ307 Δ12-13: ynamic& Static CMOS Sequential Circuits.37 Θεοχαρίδης, ΗΜΥ, 2018

36 Pseudostatic Two-Phase ET FF 1 X 2 Q P 1 A P 3 I 1 I 2 I 3 I 4!Q P 2 B P 4 master transparent slave hold t non_overlap dynamic storage 1 master hold slave transparent ΗΜΥ307 Δ12-13: ynamic& Static CMOS Sequential Circuits.38 Θεοχαρίδης, ΗΜΥ, 2018

37 Two Phase Clock Generator A 1 B 2 A B 1 2 ΗΜΥ307 Δ12-13: ynamic& Static CMOS Sequential Circuits.39 Θεοχαρίδης, ΗΜΥ, 2018

38 Power PC Flipflop! Q 0 1! master transparent slave hold master hold slave transparent! ΗΜΥ307 Δ12-13: ynamic& Static CMOS Sequential Circuits.41 Θεοχαρίδης, ΗΜΥ, 2018

39 Ratioed CMOS Clocked SR Latch 1 0!Q off on M2 on off M4 Q S off->on M6 M5 off M1 on off off->on M8 0 1 M3 off on M7 R 1 on ΗΜΥ307 Δ12-13: ynamic& Static CMOS Sequential Circuits.43 Θεοχαρίδης, ΗΜΥ, 2018

40 Sizing Issues so W/L 5and6 > 3!Q (Volts) W/L 5and6 W/L 2and4 = 1.5µm/0.25 µm W/L 1and3 = 0.5µm/0.25 µm ΗΜΥ307 Δ12-13: ynamic& Static CMOS Sequential Circuits.44 Θεοχαρίδης, ΗΜΥ, 2018

41 Transient Response 3 SET Q &!Q (Volts) 2 1 t c-!q!q t c-q Q Time (ns) ΗΜΥ307 Δ12-13: ynamic& Static CMOS Sequential Circuits.45 Θεοχαρίδης, ΗΜΥ, 2018

42 6 Transistor CMOS SR Latch R S R M5!Q M2 M4 Q M6 S M1 M3 ΗΜΥ307 Δ12-13: ynamic& Static CMOS Sequential Circuits.46 Θεοχαρίδης, ΗΜΥ, 2018

43 Review: Sequential efinitions l Static versus dynamic storage static uses a bistable element with feedback (regeneration) and thus preserves its state as long as the power is on static is preferred when updates are infrequent (clock gating) dynamic stores state on parasitic capacitors so only holds the state for a period of time (milliseconds) and requires periodic refresh dynamic is usually simpler (fewer transistors), higher speed, lower power l Latch versus flipflop latches are level sensitive with two modes: transparent - inputs are passed to Q and hold - output stable fliplflops are edge sensitive that only sample the inputs on a clock transition ΗΜΥ307 Δ12-13: ynamic& Static CMOS Sequential Circuits.47 Θεοχαρίδης, ΗΜΥ, 2018

44 ynamic ET Flipflop master slave! T master transparent slave hold! 1 C 1 Q M I 1 T I 2 Q 2! C 2 t su = t hold = t c-q = master hold slave transparent t pd_tx zero 2 t pd_inv + t pd_tx ΗΜΥ307 Δ12-13: ynamic& Static CMOS Sequential Circuits.49 Θεοχαρίδης, ΗΜΥ, 2018

45 ynamic ET FF Race Conditions! T 1 C Q M I 1 T I 2 Q 2 C 1! overlap race condition t overlap0-0 < t T1 +t I1 + t T2! 1-1 overlap race condition t overlap1-1 < t hold ΗΜΥ307 Δ12-13: ynamic& Static CMOS Sequential Circuits.50 Θεοχαρίδης, ΗΜΥ, 2018

46 ynamic Two-Phase ET FF 1 2 T 1 C Q M I 1 T I 2 Q 2 C!1 1!2 2 master transparent slave hold 1 2 t non_overlap master hold slave transparent ΗΜΥ307 Δ12-13: ynamic& Static CMOS Sequential Circuits.51 Θεοχαρίδης, ΗΜΥ, 2018

47 Pseudostatic ynamic Latch l Robustness considerations limit the use of dynamic FF s coupling between signal nets and internal storage nodes can inject significant noise and destroy the FF state leakage currents cause state to leak away with time internal dynamic nodes don t track fluctuations in V that reduces noise margins l A simple fix is to make the circuit pseudostatic! q Add above logic added to all dynamic latches ΗΜΥ307 Δ12-13: ynamic& Static CMOS Sequential Circuits.52 Θεοχαρίδης, ΗΜΥ, 2018

48 C 2 MOS (Clocked CMOS) ET Flipflop q A clock-skew insensitive FF Master Slave M 2 M 6! off off M 4 M 3 on on Q M C 1! on on M 8 M 7 off off C 2 Q M 1 M 5 master transparent slave hold! master hold slave transparent ΗΜΥ307 Δ12-13: ynamic& Static CMOS Sequential Circuits.54 Θεοχαρίδης, ΗΜΥ, 2018

49 C 2 MOS FF 0-0 Overlap Case q Clock-skew insensitive as long as the rise and fall times of the clock edges are sufficiently small M 2 M M 4 Q M C 1 M 8 C 2 Q M 1 M 5!! ΗΜΥ307 Δ12-13: ynamic& Static CMOS Sequential Circuits.55 Θεοχαρίδης, ΗΜΥ, 2018

50 C 2 MOS FF 1-1 Overlap Case M 2 M 6 Q M 1 M 3 C 1 1 M 7 C 2 Q M 1 M 5!! 1-1 overlap constraint t overlap1-1 < t hold ΗΜΥ307 Δ12-13: ynamic& Static CMOS Sequential Circuits.56 Θεοχαρίδης, ΗΜΥ, 2018

51 C 2 MOS Transient Response Q M (3) Q(3) For a 0.1 ns clock Volts Q(0.1) (0.1) (3) Time (nsec) For a 3 ns clock (race condition exists) ΗΜΥ307 Δ12-13: ynamic& Static CMOS Sequential Circuits.57 Θεοχαρίδης, ΗΜΥ, 2018

52 True Single Phase Clocked (TSPC) Latches Negative Latch Positive Latch In Q In Q hold when = 1 transparent when = 0 transparent when = 1 hold when = 0 ΗΜΥ307 Δ12-13: ynamic& Static CMOS Sequential Circuits.61 Θεοχαρίδης, ΗΜΥ, 2018

53 TSPC ET FF Master Slave on on on on Q off off Q M off off master transparent slave hold master hold slave transparent ΗΜΥ307 Δ12-13: ynamic& Static CMOS Sequential Circuits.64 Θεοχαρίδης, ΗΜΥ, 2018

54 Simplified TSPC ET FF off off M 3 Mon 6 on M 2 X! M 5 Q M 1 on M 9 off M 8 Q M 1 Moff 4 M on 7 master transparent slave hold master hold slave transparent ΗΜΥ307 Δ12-13: ynamic& Static CMOS Sequential Circuits.66 Θεοχαρίδης, ΗΜΥ, 2018

55 Sizing Issues in Simplified TSPC ET FF 3!Q mod Transistor sizing Volts 2 1 0!Q orig Q orig Q mod Time (nsec) Original width M 4, M 5 = 0.5µm M 7, M 8 = 2µm Modified width M 4, M 5 = 1µm M 7, M 8 = 1µm ΗΜΥ307 Δ12-13: ynamic& Static CMOS Sequential Circuits.67 Θεοχαρίδης, ΗΜΥ, 2018

56 Split-Output TSPC Latches Positive Latch Negative Latch In A Q In A Q transparent when = 1 hold when = 0 hold when = 1 transparent when = 0 When In = 0, A = V - V Tn When In = 1, A = V Tp ΗΜΥ307 Δ12-13: ynamic& Static CMOS Sequential Circuits.68 Θεοχαρίδης, ΗΜΥ, 2018

57 Split-Output TSPC ET FF Q M Q ΗΜΥ307 Δ12-13: ynamic& Static CMOS Sequential Circuits.69 Θεοχαρίδης, ΗΜΥ, 2018

58 Pulsed FF (AM-K6) q Pulse registers - a short pulse (glitch clock) is generated locally from the rising (or falling) edge of the system clock and is used as the clock input to the flipflop race conditions are avoided by keeping the transparent mode time very short (during the pulse only) advantage is reduced clock load; disadvantage is substantial increase in verification complexity 0 1 P ON 1 X OFF Vdd 0/Vdd P 3 Q ON/OFF 1/0 1 1/ M OFF 3 ON M ON/ 2 P 2 OFF ON M 1 ON OFF!d M OFF 6 ON M 5 M 4 ΗΜΥ307 Δ12-13: ynamic& Static CMOS Sequential Circuits.70 Θεοχαρίδης, ΗΜΥ, 2018

59 Sense Amp FF (StrongArm SA100) q Sense amplifier (circuits that accept small swing input signals and amplify them to full rail-to-rail signals) flipflops advantages are reduced clock load and that it can be used as a receiver for reduced swing differential buses M M 5 0 M 9 M Q M 1 1 M 4!Q M 3 0 M M 8 M ΗΜΥ307 Δ12-13: ynamic& Static CMOS Sequential Circuits.71 Θεοχαρίδης, ΗΜΥ, 2018

60 Flipflop Comparison Chart Name Type # ld #tr t set-up t hold t pff Mux Static 8 (-!) 20 3t pinv +t ptx 0 t pinv +t ptx PowerPC Static 8 (-!) 16 2-phase Ps-Static 8 (1-2) 16 T-gate ynamic 4 (-!) 8 t ptx t o1-1 2t pinv +t ptx C 2 MOS ynamic 4 (-!) 8 TSPC ynamic 4 () 11 t pinv t pinv 3t pinv S-O TSPC ynamic 2 () 10 AM K6 ynamic 5 () 19 SA 100 SenseAmp 3 () 20 ΗΜΥ307 Δ12-13: ynamic& Static CMOS Sequential Circuits.72 Θεοχαρίδης, ΗΜΥ, 2018

61 Choosing a Clocking Strategy l Choosing the right clocking scheme affects the functionality, speed, and power of a circuit l Two-phase designs + robust and conceptually simple - need to generate and route two clock signals - have to design to accommodate possible skew between the two clock signals l Single phase designs + only need to generate and route one clock signal + supported by most automated design methodologies + don t have to worry about skew between the two clocks - have to have guaranteed slopes on the clock edges ΗΜΥ307 Δ12-13: ynamic& Static CMOS Sequential Circuits.73 Θεοχαρίδης, ΗΜΥ, 2018

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