Lecture 8-1. Low Power Design

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1 Lecture 8 Konstantinos Masselos Department of Electrical & Electronic Engineering Imperial College London URL: Lecture 8-1

2 Based on slides/material by J. Rabaey Digital Integrated Circuits: A Design Perspective, Prentice Hall D. Harris Weste and Harris, CMOS VLSI Design: A Circuits and Systems Perspective, Addison Wesley Lecture 8-2

3 Recommended Reading J. Rabaey et. al. Digital Integrated Circuits: A Design Perspective : Chapter 5 (5.5), Chapter 11 (11.7) Weste and Harris, CMOS VLSI Design: A Circuits and Systems Perspective : Chapter 4 (4.4), Chapter 6 (6.5) Lecture 8-3

4 Why worry about power?-- Heat Dissipation source : arpa-esto microprocessor power dissipation DEC Lecture 8-4

5 Evolution in Power Dissipation Lecture 8-5

6 Why worry about power Portability BATTERY (40+ lbs) Multimedia Terminals Laptop Computers Digital Cellular Telephony Nominal Capacity (Watt-hours / lb) Rechargable Lithium Nickel-Cadium Ni-Metal Hydride Year Expected Battery Lifetime increase over next 5 years: 30-40% Lecture 8-6

7 Power and Energy Power is drawn from a voltage source attached to the V DD pin(s) of a chip. Instantaneous Power: Pt () = i () tv DD DD Energy: T E = P() t dt = i () t V dt T 0 0 DD DD Average Power: E 1 Pavg = = idd() t VDDdt T T T 0 Lecture 8-7

8 Where Does Power Go in CMOS? Dynamic Power Consumption Charging and Discharging Capacitors Short Circuit Currents Short Circuit Path between Supply Rails during Switching Leakage Leaking diodes and transistors Lecture 8-8

9 Dynamic Power Consumption Dynamic power is required to charge and discharge load capacitances when transistors switch. One cycle involves a rising and falling output. On rising output, charge Q = CV DD is required On falling output, charge is dumped to GND This repeats Tf sw times over an interval of T VDD i DD (t) f sw C Lecture 8-9

10 Dynamic Power Consumption T 1 Pdynamic = idd() t VDDdt T V = T 0 DD V = T = CV DD T 0 i [ Tf CV ] 2 DD DD f sw sw () t dt DD VDD i DD (t) f sw C Lecture 8-10

11 Activity Factor Suppose the system clock frequency = f Let f sw = αf, where α = activity factor If the signal is a clock, α = 1 If the signal switches once per cycle, α = ½ Dynamic gates: Switch either 0 or 2 times per cycle, α = ½ Static gates: Depends on design, but typically α = 0.1 Dynamic power: P = αcv f dynamic 2 DD Lecture 8-11

12 Dynamic Power Consumption Vdd Vin Vout C L Energy/transition = C L * V dd 2 Power = Energy/transition * f = C L * V dd 2 * f Not a function of transistor sizes! Need to reduce C L, V dd, and f to reduce power. Lecture 8-12

13 Dynamic Power Consumption - Revisited Power = Energy/transition * transition rate = C L * V 2 dd * f 0 1 = C L * V 2 dd * P 0 1 * f = C EFF * V 2 dd * f Power Dissipation is Data Dependent Function of Switching Activity C EFF = Effective Capacitance = C L * P 0 1 Lecture 8-13

14 Short Circuit Current When transistors switch, both nmos and pmos networks may be momentarily ON at once Leads to a blip of short circuit current. < 10% of dynamic power if rise/fall times are comparable for input and output Lecture 8-14

15 Short Circuit Currents Vdd Vin Vout C L 0.15 I VDD (ma) V in (V) Lecture 8-15

16 Impact of rise/fall times on short-circuit currents V DD V DD I SC 0 I SC I MAX V in V out V in V out C L C L Large capacitive load Small capacitive load Lecture 8-16

17 Short-circuit energy as a function of slope ratio ΔE / E V DD = 5 V V DD = 3.3 V r W/L P = 7.2μm/1.2μm W/L N = 2.4μm/1.2μm The power dissipation due to short circuit currents is minimized by matching the rise/fall times of the input and output signals. Lecture 8-17

18 Power Consumption is Data Dependent Example: Static 2 Input NOR Gate Assume: P(A=1) = 1/2 P(B=1) = 1/2 Then: C EFF = 3/16 * C L P(Out=1) = 1/4 P(0 1) = P(Out=0).P(Out=1) = 3/4 1/4 = 3/16 Lecture 8-18

19 Transition Probabilities for Basic Gates Lecture 8-19

20 Transition Probability of 2-input NOR Gate Lecture 8-20

21 Problem: Reconvergent Fanout A X B Z Reconvergence P(Z=1) = P(B=1). P(X=1 B=1) Becomes complex and intractable real fast Lecture 8-21

22 How about Dynamic Circuits? V DD φ M p Out In 1 In 2 In 3 PDN φ M e Power is Only Dissipated when Out=0! C EFF = P(Out=0).C L Lecture 8-22

23 4-input NAND Gate Example: Dynamic 2 Input NOR Gate Assume: P(A=1) = 1/2 P(B=1) = 1/2 Then: P(Out=0) = 3/4 C EFF = 3/4 * C L Switching Activity Is Always Higher in Dynamic Circuits Lecture 8-23

24 Transition Probabilities for Dynamic Gates Switching Activity for Precharged Dynamic Gates P 0 1 = P 0 Lecture 8-24

25 Glitching in Static CMOS also called: dynamic hazards A B X C Z ABC X Z Unit Delay Observe: No glitching in dynamic circuits Lecture 8-25

26 Example: Adder Circuit C in Add0 Add1 Add2 Add14 Add15 S0 S1 S2 S14 S15 Sum Output Voltage, Volts S10 Cin 5 S Time, ns S15 Lecture 8-26

27 How to Cope with Glitching? 0 0 F 1 1 F F F 1 F F 3 Equalize Lengths of Timing Paths Through Design Lecture 8-27

28 Static Power Static power is consumed even when chip is quiescent. Ratioed circuits burn power in fight between ON transistors Leakage draws power from nominally OFF devices Lecture 8-28

29 Static Power Consumption Vdd I stat V out V in =5V C L P stat = P (In=1).V dd. I stat Dominates over dynamic consumption Not a function of switching frequency Lecture 8-29

30 Leakage Vdd Vout Drain Junction Leakage Sub-Threshold Current Sub-Threshold Current Dominant Factor Lecture 8-30

31 Sub-Threshold in MOS I D V T =0.2 V T =0.6 V GS Lower Bound on Threshold to Prevent Leakage Lecture 8-31

32 Reducing V dd NORMALIZED POWER-DELAY PRODUCT quadratic dependence 51 stage ring oscillator 8-bit adder Vdd (volts) P x t d = E t = C L * V dd 2 E (Vdd=2) = E (Vdd=5) (C L ) * (2) 2 (C L ) * (5) 2 E (Vdd=2) 0.16 E (Vdd =5) Strong function of voltage (V 2 dependence). Relatively independent of logic function and style. Power Delay Product Improves with lowering V DD. Lecture 8-32

33 Lower V dd Increases Delay multiplier clock generator 2.0μm technology T d = C L * V dd I NORMALIZED DELAY adder ring oscillator adder (SPICE) microcoded DSP chip T d(vdd=2) = (2) * (5-0.7) 2 T d(vdd=5) I ~ (V dd - V t ) 2 4 (5) * (2-0.7) V dd (volts) Relatively independent of logic function and style. Lecture 8-33

34 Lowering the Threshold Delay I D 2V t V dd V t = 0 V t = 0.2 V GS Reduces the Speed Loss, But Increases Leakage Interesting Design Approach: DESIGN FOR P Leakage == P Dynamic Lecture 8-34

35 Transistor Sizing for Power Minimization Lower Capacitance Small W/L s Higher Voltage Higher Capacitance Large W/L s Lower Voltage Minimum sized devices are usually optimal for low-power. Lecture 8-35

36 Reducing Effective Capacitance Global bus architecture Local bus architecture Shared Resources incur Switching Overhead Lecture 8-36

37 Reduce dynamic power α: clock gating, sleep mode C: small transistors (esp. on clock), short wires V DD : lowest suitable voltage f: lowest suitable frequency Reduce static power Selectively use ratioed circuits Selectively use low V t devices Leakage reduction: stacked devices, body bias, low temperature Lecture 8-37

38 Summary Power Dissipation is becoming Prime Design Constraint requires Optimization at all Levels Sources of Power Dissipation are well characterized requires operation at lowest possible voltage and clock speed Lecture 8-38

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