Digital Integrated Circuits A Design Perspective


 Dortha Dawson
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1 Digital Integrated Circuits Design Perspective Jan M. Rabaey nantha Chandrakasan orivoje Nikolić Designing Combinational Logic Circuits November
2 Views / bstractions / Hierarchies ehavioral Structural device Today s view Physical Circuit Logic rchitectural D.Gajski, Silicon Compilation, ddison Wesley,
3 Design Technologies 3
4 Overview Static CMOS Conventional Static CMOS Logic Ratioed Logic Pass Transistor/Transmission Gate Logic Dynamic CMOS Logic Domino npcmos 4
5 Combinational vs. Sequential Logic In Combinational Logic Circuit Out In Combinational Logic Circuit Out State Combinational Sequential Output = f(in) Output = f(in, Previous In) 5
6 The asic Idea Voltage on the Gate controls the current through the source/drain path NChannel  NSwitches are ON when the Gate is HIGH and OFF when the Gate is LOW PChannel  PSwitches are OFF when the Gate is HIGH and ON when the Gate is LOW (ON == Circuit between Source and Drain) 6
7 Transistors as Switches N Switch G D S 0 1 Passes good zeros P Switch G D S 0 1 Passes good ones 7
8 .The Rest of the Story... Put them in series  both must be on to complete the circuit Put them in parallel  either can be on to complete the circuit Generate all sorts of Switching Functions NOT the same as oolean Functions... Its RELY logic  pin ball machines 8
9 Series Parallel Structures 1 1 G G D S S 1 1 D G G S S D D N Channel: on=closed when gate is high 9
10 NMOS Transistors in Series/Parallel Connection Transistors can be thought as a switch controlled by its gate signal NMOS switch closes when switch control input is high X Y Y = X if and X Y Y = X if OR NMOS Transistors pass a strong 0 but a weak 1 10 EE141 Digital Integrated Circuits Circuits 2nd Introduction Prentice Hall 1995 Combinational Circuits
11 Series Parallel Structures(2) 0 0 G G D S S 0 0 D G G S S D D P Channel: on=closed when gate is low 11
12 PMOS Transistors in Series/Parallel Connection PMOS switch closes when switch control input is low X Y Y = X if ND = + X Y Y = X if OR = PMOS Transistors pass a strong 1 but a weak 0 12 EE141 Digital Integrated Circuits Circuits 2nd Introduction Prentice Hall 1995 Combinational Circuits
13 That s s it! This is NonTrivial: it defines the basis for the logic abstraction which is essential for all oolean functions. Provide a path to VDD for 1 Provide a path to GND for 0 For complex functions  provide complex paths 13
14 From Switches to oolean Functions... Use the Switching Functions to provide paths to Vdd or GND Vdd is the source of all Truth (Vdd = = 1) GND is the source of all Falsehood (GND == 0) Pchannel Nchannel
15 The Inverter True to False / False to True Converter 1/0 0/1 15
16 Static CMOS Circuit t every point in time (except during the switching transients) each gate output is connected to either V DD or V ss via a lowresistive path. The outputs of the gates assume at all times the value of the oolean function, implemented by the circuit (ignoring, once again, the transient effects during switching periods). This is in contrast to the dynamic circuit class, which relies on temporary storage of signal values on the capacitance of high impedance circuit nodes. 16
17 The Exceptions Many interesting and useful circuits which are not fully complementary CMOS Pass Gates (Transmission Gates) Level shifters, etc. Even more interesting and useless circuits! New circuit styles keep being invented 17
18 Threshold Drops PUN V DD S V DD D V DD D 0 V DD V GS S 0 V DD V Tn C L C L PDN V DD 0 V DD V Tp V DD D C L V GS S C L S D 18
19 Series Parallel Structures (3) N Switch G S S D 0 1 Passes good zeros D S G S P Switch 1 Open Circuit, High Z 0 idirectional Switch Passes good ones 19
20 Static Complementary CMOS V DD In1 In2 InN In1 In2 InN PUN PDN PMOS only NMOS only F(In1,In2, InN) PUN and PDN are dual logic networks 20
21 Complementary CMOS Logic Style 21
22 Example Gate: NND 22
23 Physical Layout in MX of 2input 2 NND Gate Vdd! Cout 23
24 4input NND Gate Vdd V DD In 1 In 2 In 3 In 4 In 1 Out In 2 Out In 3 In 4 GND In1 In2 In3 In4 24 EE141 Digital Integrated Circuits Circuits 2nd Introduction Prentice Hall 1995 Combinational Circuits
25 Example Gate: NOR 25
26 Physical Layout in MX of 2input 2 NOR Gate 26
27 Constructing a Complex Gate V DD V DD C D C F SN1 D F C SN4 SN2 SN3 D F (a) pulldown network (b) Deriving the pullup network hierarchically by identifying subnets D C (c) complete gate 27
28 Complex CMOS Gate C D D C OUT = D + ( + C) 28
29 Cell Design Standard Cells General purpose logic Can be synthesized Same height, varying width Structured rray Cells Tiling structure with multiplicative parameters Programmed with vias Datapath Cells For regular, structured designs (arithmetic) Includes some wiring in the cell Fixed height and width 29
30 Standard Cell Layout Methodology 1980s Routing channel V DD signals GND 30
31 Standard Cell Layout Methodology 1990s Mirrored Cell No Routing channels V DD V DD M2 M3 GND Mirrored Cell GND 31
32 Inside out Nand / Nor Gates Which is which? 32
33 Standard Cell Layout Methodology metal1 V DD Well V SS signals Routing Channel polysilicon 33 EE141 Digital Integrated Circuits Circuits 2nd Introduction Prentice Hall 1995 Combinational Circuits
34 Standard Cells N Well V DD Cell height 12 metal tracks Metal track is approx. 3λ + 3λ Pitch = repetitive distance between objects Cell height is 12 pitch 2λ In Out Cell boundary GND Rails ~10λ 34
35 Standard Cells With minimal diffusion routing V DD With silicided diffusion V DD V DD In M 2 Out In Out In Out M 1 GND GND 35
36 Standard Cells V DD 2input NND gate V DD Out GND Note: well and substrate Contacts prevent external routing in poly 36
37 MultiFingered Transistors One finger Two fingers (folded) Less diffusion capacitance 37
38 Stick Diagrams Contains no dimensions Represents relative positions of transistors Inverter V DD NND2 V DD Out Out GND In GND 38
39 Stick Diagrams j C Logic Graph X C PUN X = C ( + ) X i V DD C i j C GND PDN 39
40 Two Versions of C ( + ) C C V DD V DD X X GND GND 40
41 Consistent Euler Path X C X i V DD j GND C 41
42 OI22 Logic Graph C X PUN D D C X = (+) (C+D) X V DD C D C D GND PDN 42
43 Example: x = ab+cd x x b c b c x V DD x V DD a d a d GND GND (a) Logic graphs for (ab+cd) (b) Euler Paths {a b c d} V DD x GND a b c d (c) stick diagram for ordering {a b c d} 43
44 CMOS Properties Full railtorail swing; high noise margins Logic levels not dependent upon the relative device sizes; ratioless lways a path to Vdd or Gnd in steady state; low output impedance Extremely high input resistance; nearly zero steadystate input current No direct path steady state between power and ground; no static power dissipation Propagation delay function of load capacitance and resistance of transistors 44
45 Complex Gate Structures ndorinvert (OI) Vdd C C Out Out = +(*C)... C How to add terms? Gnd 45
46 OI/OI Duality OrndInvert (OI) Vdd C C Demorgan s Law in ction Switch from: Out = +(*C)... Out To: C Out = *(+C)... Gnd 46
47 Demorgan s Law in ction OrndInvert (OI) Vdd C C Out = *(+C)... C Out Gnd 47
48 C Vdd Gnd Out Demorgan s Law in ction OrndInvert (OI) C C Out = *(+C)... 48
49 Demorgan s Law in ction OrndInvert (OI) C Gnd C Out = *(+C)... Out C Vdd 49
50 Demorgan s Law in ction OrndInvert (OI) Gnd C C Out = *(+C)... Out C Vdd 50
51 Demorgan s Law in ction OrndInvert (OI) Vdd C C Out = *(+C)... Out C What is the Magic command to do this? Gnd 51
52 Complex (OI/OI) Gates 52
53 Schematic Representation in SUE of OI (andor orinvert) Gate Notice 6 transistors 53
54 Physical Layout in MX of OI Gate C Vdd! OUT C OUT C 54
55 Schematic Representation in SUE of OI (orand andinvert) 55
56 Physical Layout in MX of OI Gate C OUT Vdd! C OUT C 56
57 Quiz 57
58 Step by Step Layout of XNOR Gate The equation for XNOR is: f = (a * b) + (a' * b') using DeMorgan's law on each of the two terms gives: f = (a'+ b')' + (a + b)' using DeMorgan's law on the two terms together gives: f = ((a'+ b') * (a + b))' This could be directly implemented with a single complementary CMOS gate: the equation is in a simple negated product of sums form. This form can be implemented with the standard OrndInvert (OI) style gate. 58
59 NonInverted Inputs However, using DeMorgan's law one more time on the left term gives: f = ((a * b)' * (a + b)) a b This form uses no inverted inputs and can be implemented with two gates a NND gate and an OI gate. f 59
60 Now lets lay it out Start with Vdd! and GND! power buses. Without any more information, about the use of this cell, make the power and ground lines in metal 1 sized 3 and 3 apart. Use poly as inputs and guess that C might be used. 60
61 XOR from NOR/OI 61
62 62
63 XOR Gate 63
64 Irsim 64
65 XOR GTE 65
66 3.5um x 10um 66
67 .35um x 1um 67
68 Lab 2: Full dder Sum = xor xor C Cout = + C + C expand sum Sum = C+ C + C + C (exactly 1 or 3 inputs true) use Cout to help generate Sum Sum = C + Cout (++Cin) 68
69 Full dder (4 gates) 69
70 Full dder (4 gates) 70
71 71
72 72
73 73
74 One Solution (125x136) 74
75 Is this standard cell design? 75
76 Lab 3: 8 it Ripple Carry dder 76
77 Xpanded 77
78 MS Flip Flop Is this edge triggered? Is any flip flop? I could do this with three (3) CMOS gates! (could you?) 78
79 MS Register it How many metals? How are they used? Why? 79
80 irsim Simulation 80
81 H Spice Simulation 81
82 82
83 83
84 8 x 8 Register File 84
85 Register file simulation 85
86 Properties of Complementary CMOS Gates Snapshot High noise margins: V OH and V OL are at V DD and GND, respectively. No static power consumption: There never exists a direct path between V DD and V SS (GND) in steadystate mode. Comparable rise and fall times: (under appropriate sizing conditions) 86
87 Switch Delay Model R eq R p R p R p R p R n C L R n C L R p C int NND2 R n Cint INV R n R n C L NOR2 87
88 Input Pattern Effects on Delay R p R n R n R p C L C int Delay is dependent on the pattern of inputs Low to high transition both inputs go low delay is 0.69 R p /2 C L one input goes low delay is 0.69 R p C L High to low transition both inputs go high delay is R n C L 88
89 Delay Dependence on Input Patterns Voltage [V] ==1 0 =1, =1 0 =1 0, = time [ps] Input Data Pattern Delay (psec) == =1, = = 0 1, =1 61 == =1, = = 1 0, =1 81 NMOS = 0.5μm/0.25 μm PMOS = 0.75μm/0.25 μm C L = 100 ff 89
90 Transistor Sizing R p R p R p 2 R n C L 4 R p C int 2 R n Cint 1 R n R n 1 C L 90
91 Transistor Sizing a Complex CMOS Gate 4 3 C D 4 6 OUT = D + ( + C) 2 D 1 2 C 2 91
92 FanIn Considerations C D C 3 C L Distributed RC model (Elmore delay) C D C 2 C 1 t phl = 0.69 R eqn (C 1 +2C 2 +3C 3 +4C L ) Propagation delay deteriorates rapidly as a function of fanin quadratically in the worst case. 92
93 t p as a Function of FanIn t p (psec) fanin t phl t plh t p quadratic linear Gates with a fanin greater than 4 should be avoided. 93
94 t p as a Function of FanOut t p (psec) t p NOR2 t p NND2 t p INV eff. fanout ll gates have the same drive current. Slope is a function of driving strength 94
95 t p as a Function of FanIn and FanOut Fanin: quadratic due to increasing resistance and capacitance Fanout: each additional fanout gate adds two gate capacitances to C L t p = a 1 FI + a 2 FI 2 + a 3 FO 95
96 Fast Complex Gates: Design Technique 1 Transistor sizing as long as fanout capacitance dominates Progressive sizing In N MN C L Distributed RC line In 3 M3 C 3 M1 > M2 > M3 > > MN (the fet closest to the output is the smallest) In 2 In 1 M2 M1 C 2 C 1 Can reduce delay by more than 20%; decreasing gains as technology shrinks 96
97 Fast Complex Gates: Design Technique 2 Transistor ordering critical path critical path In 3 1 In 2 1 In charged 0 1 In M3 C 1 L M3 charged C L In 1 M2 C 2 2 charged M2 C2 discharged M1 charged In 3 1 M1 C discharged 1 C 1 delay determined by time to discharge C L, C 1 and C 2 delay determined by time to discharge C L 97
98 Fast Complex Gates: Design Technique 3 lternative logic structures F = CDEFGH 98
99 Fast Complex Gates: Design Technique 4 Isolating fanin from fanout using buffer insertion C L C L 99
100 Fast Complex Gates: Design Technique 5 Reducing the voltage swing t phl = 0.69 (3/4 (C L V DD )/ I DSTn ) = 0.69 (3/4 (C L V swing )/ I DSTn ) linear reduction in delay also reduces power consumption ut the following gate is much slower! Or requires use of sense amplifiers on the receiving end to restore the signal level (memory design) 100
101 Sizing Logic Paths for Speed Frequently, input capacitance of a logic path is constrained Logic also has to drive some capacitance Example: LU load in an Intel s microprocessor is 0.5pF How do we size the LU datapath to achieve maximum speed? We have already solved this for the inverter chain can we generalize it for any type of logic? 101
102 uffer Example In Out 1 2 N C L Delay = N ( pi + gi fi ) i= 1 (in units of τ inv ) For given N: C i+1 /C i = C i /C i1 To find N: C i+1 /C i ~ 4 How to generalize this to any logic path? 102
103 Logical Effort Delay = τ = k R ( p + g f ) unit C unit 1 + C γc p intrinsic delay (3kR unit C unit γ)  gate parameter f(w) g logical effort (kr unit C unit ) gate parameter f(w) f effective fanout Normalize everything to an inverter: g inv =1, p inv = 1 L in Divide everything by τ inv (everything is measured in unit delays τ inv ) ssume γ =
104 Delay in a Logic Gate Gate delay: d = h + p effort delay intrinsic delay Effort delay: h = g f logical effort effective fanout = C out /C in Logical effort is a function of topology, independent of sizing Effective fanout (electrical effort) is a function of load/gate size 104
105 Logical Effort Inverter has the smallest logical effort and intrinsic delay of all static CMOS gates Logical effort of a gate presents the ratio of its input capacitance to the inverter capacitance when sized to deliver the same current Logical effort increases with the gate complexity 105
106 Logical Effort Logical effort is the ratio of input capacitance of a gate to the input capacitance of an inverter with the same output current V DD V DD V DD F 2 F 4 F Inverter 2input NND 2input NOR g = 1 g = 4/3 g = 5/3 106
107 Logical Effort of Gates Normalized delay (d) g = p = d = t pnnd t g = p = d = pinv F(Fanin) Fanout (h) 107
108 Logical Effort of Gates Normalized delay (d) g = 4/3 p = 2 d = (4/3)h+2 t pnnd t pinv g = 1 p = 1 d = h+1 F(Fanin) Fanout (h) 108
109 Logical Effort of Gates Normalized Delay Inverter: g = 1; p = 1 2input NND: g = 4/3; p = 2 Effort Delay 1 Intrinsic Delay Fanout f 109
110 dd ranching Effort ranching effort: b = C on path + C C off on path path 110
111 Multistage Networks Delay = N ( pi + gi fi ) i= 1 Stage effort: h i = g i f i Path electrical effort: F = C out /C in Path logical effort: G = g 1 g 2 g N ranching effort: = b 1 b 2 b N Path effort: H = GF Path delay D = Σd i = Σp i + Σh i 111
112 Optimum Effort per Stage When each stage bears the same effort: h N = H h = N H Stage efforts: g 1 f 1 = g 2 f 2 = = g N f N Effective fanout of each stage: f i = h g i Minimum path delay Dˆ = ( ) 1/ N g f + p = NH P i i i + 112
113 Optimal Number of Stages For a given load, and given input capacitance of the first gate Find optimal number of stages and optimal sizing D N = H 1/ N D = NH + 1/ N Np inv 1/ N ln( ) 1/ N H + H + p = 0 inv Substitute best stage effort h = H 1/ Nˆ 113
114 Logical Effort From Sutherland, Sproull 114
115 Example: Optimize Path 1 a b c 5 g = 1 f = a g = 5/3 f = b/a g = 5/3 f = c/b g = 1 f = 5/c Effective fanout, F = G = H = h = a = b = 115
116 Example: Optimize Path 1 a b c 5 g = 1 f = a g = 5/3 f = b/a g = 5/3 f = c/b g = 1 f = 5/c Effective fanout, F = 5 G = 25/9 H = 125/9 = 13.9 h = 1.93 a = 1.93 b = ha/g 2 = 2.23 c = hb/g 3 = 5g 4 /f =
117 Example: Optimize Path 1 a b c 5 g 1 = 1 g 2 = 5/3 g 3 = 5/3 g 4 = 1 Effective fanout, H = 5 G = 25/9 F = 125/9 = 13.9 f = 1.93 a = 1.93 b = fa/g 2 = 2.23 c = fb/g 3 = 5g 4 /f =
118 Example 8input ND 118
119 Method of Logical Effort Compute the path effort: F = GH Find the best number of stages N ~ log 4 F Compute the stage effort f = F 1/N Sketch the path with this number of stages Work either from either end, find sizes: C in = C out *g/f Reference: Sutherland, Sproull, Harris, Logical Effort, MorganKaufmann
120 Summary Sutherland, Sproull Harris 120
121 Ratioed Logic 121
122 Ratioed Logic V DD V DD V DD Resistive Load R L Depletion Load V T < 0 PMOS Load F F V SS F In 1 In 2 In 3 PDN In 1 In 2 In 3 PDN In 1 In 2 In 3 PDN V SS V SS V SS (a) resistive load (b) depletion load NMOS (c) pseudonmos Goal: to reduce the number of devices over complementary CMOS 122
123 Ratioed Logic V DD Resistive Load R L N transistors + Load V OH = V DD F V OL = R PN R PN + R L In 1 In 2 In 3 PDN ssymetrical response Static power consumption V SS t pl = 0.69 R L C L 123
124 ctive Loads V DD V DD Depletion Load V T < 0 PMOS Load F V SS F In 1 In 2 In 3 PDN In 1 In 2 In 3 PDN V SS V SS depletion load NMOS pseudonmos 124
125 PseudoNMOS V DD C D F C L V OH = V DD (similar to complementary CMOS) V2 k n ( V OL k DD V Tn )V p OL = ( V 2 2 DD V Tp ) 2 V = V V OL ( DD T ) 1 1 k p (assuming that V = V = V ) k T Tn Tp n SMLLER RE & LOD UT STTIC POWER DISSIPTION!!! 125
126 PseudoNMOS VTC W/L p = 4 V ou t [V] W/L p = W/L p = 0.5 W/L p = 0.25 W/L p = V in [V] 126
127 Improved Loads V DD Enable M1 M2 M1 >> M2 F C D C L daptive Load 127
128 Improved Loads (2) V DD V DD M1 M2 Out Out PDN1 PDN2 V SS V SS Differential Cascode Voltage Switch Logic (DCVSL) 128
129 DCVSL Example Out Out XORNXOR gate 129
130 DCVSL Transient Response 2.5 Volta ge [V] ,, Time [ns] 130
131 PassTransistor Logic 131
132 PassTransistor Logic Inputs Switch Network Out Out N transistors No static consumption 132
133 Example: ND Gate F = 0 133
134 NMOSOnly Only Logic V DD In x 0.5μm/0.25μm 1.5μm/ 0.25μm 0.5 μm/ 0.25μm Out Voltage [V] Out x In Time [ns] 134
135 NMOSonly Switch C = 2.5V C = 2.5 V = 2.5 V = 2.5 V M 2 M n C L M 1 V does not pull up to 2.5V, but 2.5V V TN Threshold voltage loss causes static power consumption NMOS has higher threshold than PMOS (body effect) 135
136 NMOS Only Logic: Level Restoring Transistor V DD Level Restorer V DD M r M 2 M n X Out M 1 dvantage: Full Swing Restorer adds capacitance, takes away pull down current at X Ratio problem 136
137 Restorer Sizing Voltage [V] W/L r =1.75/0.25 W/L r =1.50/0.25 W/L r =1.0/0.25 W/L r =1.25/0.25 Upper limit on restorer size Passtransistor pulldown can have several transistors in stack Time [ps] 137
138 Solution 2: Single Transistor Pass Gate with V T =0 V DD 0V 2.5V V DD V DD 0V Out 2.5V WTCH OUT FOR LEKGE CURRENTS 138
139 Complementary Pass Transistor Logic PassTransistor Network F (a) Inverse PassTransistor Network F F= F=+ F= ΒÝ (b) F= F=+ F= ΒÝ ND/NND OR/NOR EXOR/NEXOR 139
140 Solution 3: Transmission Gate C C C C C = 2.5 V = 2.5 V C L C = 0 V 140
141 Resistance of Transmission Gate 30 R n 2.5 V Rn Resistance, ohms R p R n R p 2.5 V 0 V R p V ou t V ou t, V 141
142 PassTransistor ased Multiplexer S S V DD S V DD M 2 S F M 1 S GND In 1 S S In 2 142
143 Transmission Gate XOR M2 M1 F M3/M4 143
144 Delay in Transmission Gate Networks In V 1 V i1 V i V i+1 V n1 V n C 0 0 C 0 C C 0 C (a) In R eq R V eq R eq R 1 V i V i+1 V eq n1 V n C C C C C m (b) R eq R eq R eq R eq R eq R eq In C C C C C C C C (c) 144
145 Delay Optimization 145
146 Transmission Gate Full dder P V DD V DD P C i C i P S Sum Generation V DD P P P V DD C o Carry Generation C i C i Setup C i P Similar delays for sum and carry 146
147 Dynamic Logic 147
148 Dynamic CMOS In static circuits at every point in time (except when switching) the output is connected to either GND or V DD via a low resistance path. fanin of n requires 2n (n Ntype + n Ptype) devices Dynamic circuits rely on the temporary storage of signal values on the capacitance of high impedance nodes. requires on n + 2 (n+1 Ntype + 1 Ptype) transistors 148
149 Dynamic Gate Clk M p Out Clk M p off on 1 Out In 1 In 2 In 3 PDN C L (()+C) C Clk M e Two phase operation Precharge (Clk = 0) Evaluate (Clk = 1) Clk M e off on 149
150 Conditions on Output Once the output of a dynamic gate is discharged, it cannot be charged again until the next precharge operation. Inputs to the gate can make at most one transition during evaluation. Output can be in the high impedance state during and after evaluation (PDN off), state is stored on C L 150
151 Properties of Dynamic Gates Logic function is implemented by the PDN only number of transistors is N + 2 (versus 2N for static complementary CMOS) Full swing outputs (V OL = GND and V OH = V DD ) Nonratioed  sizing of the devices does not affect the logic levels Faster switching speeds reduced load capacitance due to lower input capacitance (C in ) reduced load capacitance due to smaller output loading (Cout) no I sc, so all the current provided by PDN goes into discharging C L 151
152 Properties of Dynamic Gates Overall power dissipation usually higher than static CMOS no static current path ever exists between V DD and GND (including P sc ) no glitching higher transition probabilities extra load on Clk PDN starts to work as soon as the input signals exceed V Tn, so V M, V IH and V IL equal to V Tn low noise margin (NM L ) Needs a precharge/evaluate clock 152
153 Issues in Dynamic Design 1: Charge Leakage CLK Clk M p Out C L Clk M e V Out Evaluate Precharge Leakage sources Dominant component is subthreshold current 153
154 Solution to Charge Leakage Keeper Clk M p M kp C L Out Clk M e Same approach as level restorer for passtransistor logic 154
155 Issues in Dynamic Design 2: Charge Sharing Clk M p C L Out Charge stored originally on C L is redistributed (shared) over C L and C leading to reduced robustness =0 Clk M e C C 155
156 Charge Sharing Example Clk Out C L =50fF C a =15fF! C b =15fF C c =15fF C C C d =10fF Clk 156
157 Charge Sharing V DD case 1) if ΔV out < V Tn Clk M p Out C L V DD = C L V out ( t) + C a ( V DD V Tn ( V X )) M a X C L ΔV out or = V out ( t) V DD = C a V ( C DD V Tn ( V X )) L = 0 M b C a case 2) if ΔV out > V Tn Clk M e C b C a ΔV out V = DD C a + C L 157
158 Solution to Charge Redistribution Clk M p M kp Out Clk Clk M e Precharge internal nodes using a clockdriven transistor (at the cost of increased area and power) 158
159 Issues in Dynamic Design 3: ackgate Coupling Clk =0 M p C L1 Out1 =1 C L2 Out2 =0 In =0 Clk M e Dynamic NND Static NND 159
160 ackgate Coupling Effect 3 Voltage 2 1 Clk Out1 0 In Out Time, ns
161 Issues in Dynamic Design 4: Clock Feedthrough Clk Clk M p M e C L Out Coupling between Out and Clk input of the precharge device due to the gate to drain capacitance. So voltage of Out can rise above V DD. The fast rising (and falling edges) of the clock couple to Out. 161
162 Voltage Clock Feedthrough Clk Out 2.5 Clock feedthrough In 1 In In 3 In 4 Clk In & Clk Out Time, ns 1 Clock feedthrough 162
163 Other Effects Capacitive coupling Substrate coupling Minority charge injection Supply noise (ground bounce) 163
164 Cascading Dynamic Gates V Clk In M p Clk Out1 M p Out2 Clk In Clk M e Clk M e Out1 V Tn Out2 ΔV t Only 0 1 transitions allowed at inputs! 164
165 Domino Logic Clk In 1 In 2 M p PDN Out1 Clk In 4 M p M kp PDN Out2 In 3 In 5 Clk M e Clk M e 165
166 Why Domino? Clk In i In j Clk PDN In i PDN In i PDN In i PDN In j In j In j Like falling dominos! 166
167 Properties of Domino Logic Only noninverting logic can be implemented Very high speed static inverter can be skewed, only LH transition Input capacitance reduced smaller logical effort 167
168 Designing with Domino Logic V DD V DD V DD Clk M p Out1 Clk M p M r Out2 In 1 In 2 PDN In 4 PDN In 3 Can be eliminated! Clk M e Clk M e Inputs = 0 during precharge 168
169 Footless Domino V DD V DD V DD Clk M p Out 1 Clk M p Out 2 Clk M p Out n In In In 3 In n The first gate in the chain needs a foot switch Precharge is rippling shortcircuit current solution is to delay the clock for each stage 169
170 Differential (Dual Rail) Domino Out = Clk off on M p M kp M kp M p Clk !! Out = Clk M e Solves the problem of noninverting logic 170
171 npcmos Clk In 1 M p Out1 Clk In 4 M e PUN In 2 In 3 Clk PDN M e In 5 Clk M p Out2 (to PDN) Only 0 1 transitions allowed at inputs of PDN Only 1 0 transitions allowed at inputs of PUN 171
172 NOR Logic Clk In 1 M p Out1 Clk In 4 M e PUN In 2 In 3 Clk PDN M e In 5 Clk M p Out2 (to PDN) to other PDN s to other PUN s WRNING: Very sensitive to noise! 172
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