EECS 427 Lecture 11: Power and Energy Reading: EECS 427 F09 Lecture Reminders

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1 EECS 47 Lecture 11: Power and Energy Reading: 5.55 [Adapted from Irwin and Narayanan] 1 Reminders CAD5 is due Wednesday 10/8 You can submit it by Thursday 10/9 at noon Lecture on 11/ will be taught by Wei-Hsiang Topic: ultra-low-power charge-recovering circuits HW4 (detailed proposal) is due 11/16 You should be working on your project concurrently 1

2 Overview Quiz 1 recap Power and energy Dynamic, short-circuit, and leakage 3 Why Power Matters Packaging costs Power supply rail design Chip and system cooling costs Noise immunity and system reliability Battery life (in portable systems) Environmental concerns Office equipment accounted for 5% of total US commercial energy usage in

3 Power Dissipation 100 Power (Watts) P6 Pentium Year Power delivery and dissipation will be prohibitive Source: Borkar, De Intel 5 Power Density Sun s Surface Po ower Density (W/cm) Nuclear Reactor 8086 Hot Plate Rocket Nozzle P6 Pentium Year chips might become hot Source: Borkar, De Intel 6 3

4 Standby Power Year Power supply V dd (V) Threshold V T (V) Drain leakage will increase as V T decreases to maintain i noise margins and meet frequency demands, leading to excessive battery draining standby power consumption. 50% 40% 1.7KW 8KW and phones leaky! Standby Pow wer 30% 0% 10% 1W 88W 400W 0% Source: Borkar, De Intel Battery Size/Weight 50 Rechargable Lithium Battery (40+ lbs) Nominal Capacity (W-h hr/lb) Nickel-Cadmium Ni-Metal Hydride Year Expected battery lifetime increase over the next 5 years: 30 to 40% From Rabaey,

5 Power and Energy Power consumption in Watts determines battery life in hours Peak power determines power ground wiring designs sets packaging limits impacts signal noise margin and reliability analysis Energy in Joules Energy =power* delay Joules = Watts * seconds lower energy number means less power to perform a computation at the same frequency 9 Power versus Energy Watts Power is height of curve Lower power design could simply be slower Approach h1 Approach Watts time Energy is area under curve Two approaches require the same energy Approach 1 Approach time 10 5

6 Where Does Power Go in CMOS? Dynamic Power Consumption Charging and Discharging Capacitors Short Circuit Currents Short Circuit Path between Supply Rails during Switching Leakage Leaking diodes and transistors 11 Dynamic Power Consumption Vdd Vin Vout C L Energy/transition = C L * V DD * P 0 1 f 0 1 P dyn = Energy/transition * f = C L * V DD * P 0 1 * f dyn gy L DD 0 1 P dyn = C EFF * V DD * f where C EFF = P 0 1 C L Not a function of transistor sizes! Data dependent - a function of switching activity! 1 6

7 Modification for Circuits with Reduced Swing V dd V dd V dd -V t C L E 0 1 = C L V dd V dd V t Can exploit reduced swing to lower power (e.g., reduced bit-line swing in memory) 13 Adiabatic Charging 14 7

8 Adiabatic Charging 15 PDP and EDP Power-delay product (PDP) = P av * t p = (C L V DD )/ PDP is the average energy consumed per switching event (Watts * sec = Joule) lower power design could simply be a slower design Energy-delay product (EDP) = PDP * t p = P av * t p EDP is the average energy consumed multiplied by the computation time required takes into account that one can trade increased delay for lower energy/operation (e.g., via supply voltage scaling that increases delay, but decreases energy consumption) la y (n o rm a liz e d ) E n e r g y - D e energy-delay energy delay Vdd (V) 16 8

9 Lowering Dynamic Power Capacitance: Function of fan-out, wire length, transistor sizes Supply Voltage: Has been dropping with successive generations P dyn = C L V DD P 0 1 f Activity factor: How often, on average, do wires switch? Clock frequency: Increasing 17 Short Circuit Power Consumption Vin I sc Vout C L Finite slope of the input signal causes a direct current path between V DD and GND for a short period of time during switching when both the NMOS and PMOS transistors are conducting. 18 9

10 Short Circuit Currents P sc = t sc V DD I peak f Duration and slope of the input signal, t sc I peak determined by the saturation current of the P and N transistors which depend on their sizes, process technology, temperature, etc. strong function of the ratio between input and output t slopes a function of C L 19 Impact of C L on P sc I sc 0 I sc I max Vin Vout Vin Vout C L C L Large capacitive load Small capacitive load Output fall time significantly larger than input rise time. Output fall time substantially smaller than the input rise time. 0 10

11 I peak as a Function of C L.5 x 10-4 C L = 0 ff When load capacitance is small, I peak is large C L = 100 ff 0.5 C L = 500 ff x time (sec) 500 psec input slope Short circuit dissipation is minimized by matching the rise/fall times of the input and output signals - slope engineering. P sc as a Function of Rise/Fall Times V DD = 3.3 V V DD =.5 V 1 V DD =15V 1.5V 0 0 t sin /t sout 4 W/L p = 1.15 m/0.5 m W/L n = m/0.5 m C L = 30 ff normalized wrt zero input rise-time dissipation When load capacitance is small (t sin /t sout > for V DD > V) the power is dominated by P sc If V DD < V Tn + V Tp then P sc is eliminated since both devices are never on at the same time. 11

12 Leakage Power V DD I leakage Vout Drain junction leakage Gate leakage Sub-threshold current Sub-threshold current is the dominant factor. 3 Leakage as a Function of V T 10 - ID (A ) 10-7 VT=0.4V VT=0.1V An 90mV/decade V T roll-off - so each 90mV increase in V T gives 1 order of magnitude reduction in leakage (but adversely affects performance) VGS (V) 1

13 TSMC Processes Leakage and V T CL018 G CL018 LP CL018 ULP CL018 HS CL015 HS CL013 HS V dd 18V V V 1.8 V 15V 1.5 1V 1. T ox (effective) 4 Å 4 Å 4 Å 4 Å 9 Å 4 Å L gate 0.16 m 0.16 m 0.18 m 0.13 m 0.11 m 0.08 m I DSat (n/p) ( A/ m) 600/60 500/180 30/ / /370 90/400 I off (leakage) (pa/ m) ,800 13,000 V Tn 04V V V V V V 0.5 FET Perf. (GHz) From MPR, 000 Exponential Increase in Leakage Currents I leakage (na/ m) Temp(C) From De,

14 Power and Energy Design Space Constant Throughput/Latency Variable Throughput/Latency Energy Design Time Non-active Modules Run Time Active Logic Design Reduced V dd Sizing Clock Gating Multi-V dd Leakage + Multi-V T Multi-V dd Sleep Transistors Variable V T DFS, DVS (Dynamic Freq, Voltage Scaling) + Variable V T 7 Summary Power and energy Power (energy consumption per second) matters in package design, cooling, power rail design, and noise immunity etc. Energy matters in battery-powered, portable devices Dynamic power Due to switching reduce VDD, lower capacitance, reduce switching probability Leakage power Mainly due to subthreshold currents increase V T, sleep Short-circuit current Both pull-up and pull-down are on at the same time control input/output slopes, less important now at lower VDD 8 14