Topics. Dynamic CMOS Sequential Design Memory and Control. John A. Chandy Dept. of Electrical and Computer Engineering University of Connecticut


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1 Topics Dynamic CMOS Sequential Design Memory and Control
2 Dynamic CMOS In static circuits at every point in time (except when switching) the output is connected to either GND or V DD via a low resistance path. fanin of n requires 2n (n Ntype + n Ptype) devices Dynamic circuits rely on the temporary storage of signal values on the capacitance of high impedance nodes. requires only n+2 (n+1 Ntype + 1 Ptype) transistors
3 Dynamic CMOS nmos logic structure with precharged pullup INPUTS N logic Precharge to VDD when clock is low Evaluate when clock is high
4 Dynamic Gate M p Out M p on off 1 Out In 1 In 2 In 3 PDN C L A B ((AB)+C) C M e Two phase operation M e off on Precharge ( = 0) Evaluate ( = 1)
5 Conditions on Output Once the output of a dynamic gate is discharged, it cannot be charged again until the next precharge operation. Inputs to the gate can make at most one transition during evaluation. Output can be in the high impedance state during and after evaluation (PDN off), state is stored on C L
6 Properties of Dynamic Gates Logic function is implemented by the PDN only number of transistors is N + 2 (versus 2N for static complementary CMOS) Full swing outputs (V OL = GND and V OH = V DD Nonratioed  sizing of the devices does not affect the logic levels Faster switching speeds DD ) reduced load capacitance due to lower input capacitance (C( in ) reduced load capacitance due to smaller output loading (Cout( Cout) no I sc, so all the current provided by PDN goes into discharging C L
7 Properties of Dynamic Gates Overall power dissipation usually higher than static CMOS no static current path ever exists between V DD and GND (including P sc ) no glitching higher transition probabilities extra load on PDN starts to work as soon as the input signals exceed V Tn, so V M, V IH and V IL equal to V Tn low noise margin (NM L ) Needs a precharge/evaluate clock
8 Dynamic CMOS Advantages Fewer transistors than CMOS  on the same order as pseudonmos Smaller load capacitances  faster speed Disadvantages Inputs must be stable during evaluate phase Can not be cascaded Charge sharing
9 Issues in Dynamic Design 1: Charge Leakage M p Out A C L M e V Out Evaluate Precharge Leakage sources Dominant component is subthreshold current
10 Solution to Charge Leakage Keeper M p M kp A B C L Out M e Same approach as level restorer for passtransistor logic Increase size of inverter to increase capacitance
11 Issues in Dynamic Design 2: Charge Sharing A M p C L Out Charge stored originally on C L is redistributed (shared) over C L and C A leading to reduced robustness B=0 M e C A C B
12 Dynamic CMOS Charge Sharing C o C i C i C i Assume that the internal capacitances have been discharged In the precharge phase, the output capacitance gets charged During evaluation, if all the inputs are high except the bottom one, the output capacitance gets distributed to the internal capacitance The output voltage will drop to C o + 2C i This could be low enough to trigger the inverter, causing a wrong value on the output V DD C o C i
13 Solution to Charge Redistribution A M p M kp Out B M e Precharge internal nodes using a clockdriven transistor (at the cost of increased area and power)
14 Dynamic CMOS Cascade problem INPUTS N logic N logic Since the evaluation from the first stage takes some time, the second stage will start evaluating with the precharged input rather than the evaluated input
15 Cascading Dynamic Gates V In M p Out1 M p Out2 In M e M e Out1 V Tn Out2 ΔV t Only 0 1 transitions allowed at inputs!
16 Domino Logic Solves cascade problem INPUTS N logic N logic Since the precharged output from the first stage is 0, it will never activate the pulldown network in the second stage until the first stage evaluation has completed.
17 NP Domino (Zipper) CMOS INPUTS N logic P logic Since the second stage is build from plogic, the precharged output from the first stage will not activate the inputs of the second stage
18 Sequential Logic In our text: a latch is level sensitive a register is edgetriggered a flipflop is bistable There are many different naming conventions For instance, many books call edgetriggered registers flipflops as well
19 Latch versus Register Latch stores data when clock is low Register stores data when clock rises D Q D Q D Q D Q
20 Latches Positive Latch Negative Latch In D Q Out In D Q Out G G clk clk In Out In Out Out stable Out follows In Out stable Out follows In
21 LatchBased Design N latch is transparent when φ = 0 φ P latch is transparent when φ = 1 N Latch Logic P Latch Logic
22 Timing Definitions t su t hold t D Register Q D DATA STABLE t t c 2 q Q DATA STABLE t
23 Characterizing Timing t D 2 Q D Q D Q t C 2 Q t C 2 Q Register Latch
24 Maximum Clock Frequency φ s F LOGIC t p,comb t clkq + t p,comb + t setup = T Also: t cdreg + t cdlogic > t hold t cd : contamination delay = minimum delay
25 Positive Feedback: BiStability V i 1 V o1 = V i 2 V o2 V o1 V i2 V o2 = V i 1 V i1 V o2 A V i2 = V o1 C B V i1 = V o2
26 MetaStability A A C C B B V i 1 5 V o2 Gain should be larger than 1 in the transition region V i1 5 V o2
27 Writing into a Static Latch Use the clock as a decoupling signal, that distinguishes between the transparent and opaque states Q D D D Converting into a MUX Forcing the state (can implement as NMOSonly)
28 MuxBased Latches Negative latch (transparent when = 0) Positive latch (transparent when = 1) 1 Q 0 Q D 0 D 1 Q = Q + In Q = Q + In
29 MuxBased Latch Q D
30 MuxBased Latch Q M Q M NMOS only Nonoverlapping clocks
31 MasterSlave (EdgeTriggered) Register Slave Master 0 Q D D 1 0 Q M 1 Q M Q Two opposite latches trigger on edge Also called masterslave latch pair
32 MasterSlave Register Multiplexerbased latch pair I 2 T 2 I 3 I 5 T 4 I 6 Q D I 1 T 1 Q M I 4 T 3
33 Semiconductor Memory Classification ReadWrite Memory NonVolatile ReadWrite Memory ReadOnly Memory Random Access NonRandom Access EPROM E 2 PROM MaskProgrammed Programmable (PROM) SRAM FIFO FLASH DRAM LIFO Shift Register CAM
34 Memory Design Random Access Memory Row decoder 2 m+k memory cells wide n1:k k1:0 Column Decoder n bit address Sense Amplifier m bit data word
35 Memory Design Static RAM Cell Word select bit bit
36 Memory Design Reads are straightforward May need precharge circuitry to pull up bit line Writes are trickier Use driver transistors that will pullup or pull down bit line as necessary
37 Memory Design Static RAM Cell with precharge precharge Word select bit bit
38 Memory Design Static RAM Cell write circuitry precharge Word select Write enable Write data
39 3Transistor DRAM Cell BL 1 BL2 WWL RWL WWL M 3 RWL M 1 X M 2 X V DD 2 V T C S BL 1 V DD BL 2 V DD 2 V T DV No constraints on device ratios Reads are nondestructive Value stored at node X when writing a 1 = V WWL V Tn
40 3TDRAM Layout BL2 BL1 GND RWL M3 M2 WWL M1
41 1Transistor DRAM Cell BL WL Write 1 Read 1 WL M 1 X GND V DD 2 V T C S BL V DD /2 V DD V sensing C BL Write: C S is charged or discharged by asserting WL and BL. Read: Charge redistribution takes places between bit line and storage capacitance ΔV = VBL V PRE = V BIT V PRE C S C S + C BL Voltage swing is small; typically around 250 mv.
42 DRAM Cell Observations 1T DRAM requires a sense amplifier for each bit line, due to charge redistribution readout. DRAM memory cells are single ended in contrast to SRAM cells. The readout of the 1T DRAM cell is destructive; read and refresh operations are necessary for correct operation. Unlike 3T cell, 1T cell requires presence of an extra capacitance that must be explicitly included in the design. When writing a 1 into a DRAM cell, a threshold voltage is lost. This charge loss can be circumvented by bootstrapping the word lines to a higher value than V DD
43 Sense Amp Operation V BL V(1) V PRE DV(1) Sense amp activated Word line activated V(0) t
44 1T DRAM Cell Capacitor Metal word line Poly n + n + Inversion layer Poly induced by plate bias Crosssection SiO 2 Field Oxide Diffused bit line Polysilicon gate Layout Polysilicon plate M 1 word line Uses PolysiliconDiffusion Capacitance Expensive in Area
45 Memory Design RAMs Static RAM is faster, does not need to be refreshed Dynamic RAM is more compact
46 Next class More about memory Control logic
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