# ESE570 Spring University of Pennsylvania Department of Electrical and System Engineering Digital Integrated Cicruits AND VLSI Fundamentals

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1 University of Pennsylvania Department of Electrical and System Engineering Digital Integrated Cicruits AND VLSI Fundamentals ESE570, Spring 017 Final Wednesday, May 3 4 Problems with point weightings shown. All 4 problems must be completed. Calculators allowed. Closed book = No text or notes allowed. Clearly label all final answers. Name: Answers Grade: Q1 Q Q3 Q4 Total Mean: 58, Standard Deviation: 16 1

2 University of Pennsylvania Department of Electrical and System Engineering Digital Integrated Cicruits AND VLSI Fundamentals ESE570, Spring 017 Formulas and Data Friday, May 6th Physical Constants: n i = intrinsic concentration (undoped) silicon = cm 300 K k = Boltzman s constant = J/ K q = electronic charge = C 1 angstrom = 10 8 cm ɛ Si = permittivity of Si = F/cm ɛ SiO = ɛ ox = permittivity of SiO = F/cm MOS Transistor IV Characteristics: nmos: pmos: V GS V DS Mode I DS ) V GS V T h e nkt /q ( 1 e V DS kt /q ) (1 + λv DS ) V T h Subthreshold ( I W S L > V T h < V GS V T h Resistive k n ((V GS V T h )V DS VDS)(1 + λv DS ) V GS V T h Saturation k n (V GS V T h ) (1 + λv DS ) k n = µ n C ox W n L n V GS V DS Mode I DS ) V GS V T h e nkt /q ( 1 e V DS kt /q ) (1 + λv DS ) V T h Subthreshold ( I W S L < V T h > V GS V T h Resistive k n ((V GS V T h )V DS VDS)(1 + λv DS ) V GS V T h Saturation k n (V GS V T h ) (1 + λv DS ) k p = µ p C ox W p L p Threshold Voltage: V T h = V T 0 + γ ( φ F + V SB φ F ) (p-sub) φ F = kt ln n i q N A γ = ɛ Si qn A C ox and (n-sub) φ F = kt q ln N D ni

3 CMOS Capacitors: C ox = ɛox t ox C O = C GSO = C GDO = C ox W L D MOS Gate Capacitance: MOS Diffusion Capacitance: C diff = C db = A D C j0 + P D C j0sw A D = Area of diffusion region P D = Perimeter of diffusion region Static/Dynamic Characteristics of Gates: V 50% = 1 (V OL + V OH ) τ P HL = time for output voltage to fall from V OH to V 50% τ P LH = time for output voltage to rise from V OL to V 50% τ P = τ P HL+τ P LH Average Current Delay Model: τ P HL = C load V HL I avg,hl = C load(v OH V 50% ) I avg,hl τ P LH = C load V LH I avg,lh = C load(v 50% V OL ) I avg,lh First-order RC Delay Model: τ P HL = 0.69 C load R P D τ P LH = 0.69 C load R P U Power Equations: P tot = P dyn + P SC + P stat P dyn = dynamic power = a ( ) 1 Cload V f P SC = short circuit power = ac SC V f P stat = static power = V I stat where a=acitivity factor, f=switching frequency 3

4 For this first question: µ n =400 cm /(V s), µ p =00 cm /(V s), V Tp = V Tn R un =resistance of W n = 1 NMOS transistor C g = gate capacitance of W n = 1 transistor C diff =C SB =C SD =0.5 C g We will use the following circuit implementations (for which you will determine transistor sizing). Inverter Nand Tristate Tristate Mux 4

5 1. (30 points) You will size each of the following circuits for minimum delay from the data inputs (assume the select inputs are not switching they are set once before the circuit operates and does not change during operation). Identify the delay of the optimized circuit. You should size each labeled instance of a gate independently. Assume: input drivers with strength R un that do not fan out to anything else. output load of 48C g There are many parameters, so a brute-force search of possible widths will likely be too time consuming. You will need to apply insights to solve this problem efficiently. Begin first by identifying the critical path and writing the delay expression. Then simplify and make assumptions to minimize the delay. Hint: Think derivatives to minimize... (a) Tristate Mux4 Symbolic Delay Expression: R un (T 0.W P 4 + T 0.W N4) C g + ( R un T 0.W N4 + Assuming WP4=WN4; WP3=WN3 Gate Trans. Size I0 WP0 WN0 1 N0 WP1 WP WN1 1 WN 1 I1 WP0 WN0 1 T0 WP3 40 WP4 8 WN3 0 WN4 4 Delay 8.τ R ) ( un T 0.W P 4+T 0.W N4 T 0.W N ) C g 5

6 Since select occurs once before the circuit operates, the control path gates (I0, N0, I1) are not critical. Therefore we size them as minimum sized. Nor is the charging of T0.WP3 and T0.WN3 critical. The delay simply decreases with increasing T0.WP3 and T0.WN3, so we can set these large. Maybe we want to set them large enough so their impact is only some fraction of the impact of T0.WN4, T0.WP4? So, maybe we set them to be 5 the size of T0.WN4, T0.WP4, so their impact is only 0% on delay. Couple that with our :1 P to N ratio because of the ratio of mobilities, and we have: or: ( ) ( 1 R un C g (3T 0.W N4 + T 0.W N T 0.W N4 5T 0.W N4 τ ( ( )) 6 3T 0.W N4 3T 0.W N T 0.W N4 )) + 48 To minimize, we take the derivative with respect to T0.WN4 and set to zero. 3 6 ( ) 1 (48) = 0 5 T 0.W N4 3 = 6 ( ) 1 (48) 5 T 0.W N4 16 = 5 (T 0.W N4) 6 T 0.W N4 = We likely round this to 4. 6

7 (b) Tristate Mux tree Symbolic Delay Expression: R un (M0.T 0.W P 4 + M0.T 0.W N4) C g + ( R un M0.T 0.W N4 + ) ( R un M0.T 0.W P 4+M0.T 0.W N4 M0.T 0.W N3 + ( R un M1.T 0.W N4 + R un M1.T 0.W N3 Assuming WP4=WN4; WP3=WN3 Gate Trans. Size M0.I0 WP0 WN0 1 M0.T0 WP3 30 WP4 6 WN3 15 WN4 3 M1.I0 WP0 WN0 1 M1.T0 WP3 70 WP4 14 WN3 35 WN4 7 Delay 9.τ + M1.T 0.W P 4 + M1.T 0.W N4 ) C g ) ( M1.T 0.W P 4+M1.T 0.W N ) C g 7

8 This is similar to the previous with two stages instead of one. Inverters are off the critical path for data transitions, so their sizing is not important. Making similar assumptions (T0.WN3=5T0.WN4) for the two cases, we are left with two variables. Pulling out the τ = R un C g, we have: ( (( ) ) M0.T 0.W N4 + M0.T 0.W N4 + 3M1.T 0.W N4 5) M0.T 0.W N4 ( (( ) ) M1.T 0.W N ) M1.T 0.W N4 Let M0.T 0.W N4 = x and M1.T 0.W N4 = y, so we can simplify to ( ) 6 1 3x + 5 x (( ) ( ) (( ) x + 3y + y + 48 ) 5 y ) x + 18y 5x y Taking the partial derivative with respect to x and solving for zero: y 5 ( x ) = 0 y = 5x 6 Substituting this back into the delay expression yields: x x 5x 6 5x x x Taking the derivative with respect to x and solving for zero: ( x 3 ) = 0 x = 6 5 x.8 So, we try M0.T 0.W N4 = 3 which implies M0.T 0.W N4 = 7.5. Trying both 7 and 8 delay is mostly same. Smallest with M0.T 0.W N4 = 7. 8

9 For the rest of the exam the following technology parameters should be used: Parameter NMOS PMOS V T 0 0.8V -0.8V µc ox 300µA/V 100µA/V γ, λ 0 V 1/ 0 V 1/ W min 1µm 1µm L min 1µm 1µm V DD 5V 5V. (5 points) The following level sensitive latch circuit with transistor sizes is designed as shown below (a) Is this circuit a static or dynamic sequential circuit? Justify your answer. Static. Q is actively driven with cross-coupled inverter pair during hold. (b) Is this a positive or negative latch? I.e. For which clock phase is the output equal to the input? Justify your answer. This is a positive latch. When CLK is high Q follows D and the feedback path is disabled. 9

10 (c) The delay through the latch is determined by the rise and fall times at internal node X. Suppose C x = 5fF. Assume C x >> C g and C x >> C diff. Using the switch RC model for the transistors, calculate the rise and fall times of node X assuming simultaneous ideal steps on D and CLK or CLK and that the initial resistance remains unchanged throughout the transition. The rise time can be calculated with τ r =.RC However, neglecting the. coefficient was also accepted. R pu = V DS I dp = = µ pc ox 100µA/V = Ω V DD W ( V L GS V T p ) 5V 6(5V 0.8V ) τ r =.(1889.6Ω)(5fF ) = 103.8ps τ f = τ r since the devices are sized such that R pu = R pd using their mobility ratio. 10

11 (d) Briefly describe a set of conditions on CLK and CLK which could cause the latch to operate incorrectly. If CLK and CLK overlap and are both high or low simultaneously; if the CLK rise and fall times are much larger than the rise and fall times of the latch 11

12 3. (5 points) For this problem, assume all transistor widths and lengths are 1µm, unless otherwise specified. Below is shown an eight transistor memory cell. The inverters are CMOS inverters. (a) What type of memory cell is shown above (I.e SRAM, DRAM, ROM, etc.)? Justify your answer SRAM. There is a cross-coupled inverter pair actively driving the stored data. (b) Label the figure (fill in the boxes) to clearly indicate the storage (data) node Q, the write word line W W L, the read word line RW L, the write bit line W BL, and the read bit line RBL. Also label the complements of any signals if necessary. 1

13 (c) Assume Node 1 is a storage node and NMOS M1 connects to a bidirectional bit line. If Node 1 stores a logic 0 and the bit line is held at V DD, write an equation which can be solved for the voltage V 1 at Node 1. State any reasonable assumptions you make. Simplify the equation but you do not need to solve for V 1. During write, WWL high and V 1 charged through current path through M1 and nmos in inverter in cell; call it M. Assume V 1 < V DD V T n M in linear mode since V GS = V DD, V DS = V 1 M1: V DS = V DD V 1 and V GS = V DD V 1 M1 in saturation µ n C ox (V DD V 1 V T n ) = µ nc ox I d1 = I d ((V DD V T n )V 1 V 1 ) (V DD V 1 V T n ) = (V DD V T n ) V 1 (d) Under the same assumptions as in part (c), if Node 1 stores a logic 1 and the bit line is held at 0V, write an equation which can be solved for the voltage V 1 at Node 1. State any reasonable assumptions you make. Simplify the equation but you do not need to solve for V 1. During write, WWL high and V 1 discharged through current path through M1 and pmos in inverter in cell; call it M. Assume V 1 > V DD V T n M in linear mode since V GS = V DD, V DS = V DD V 1 M1: V DS = V 1 and V GS = V DD M1 in saturation µ n C ox I d1 = I d (V DD V T n ) = µ pc ox ((V DD V T p )(V DD V 1 ) (V DD V 1 ) ) 13

14 (e) What is the principal advantage of the 8T memory cell over a conventional 6T SRAM cell? The cell decouples transistor sizing for writes from sizing for reads. 14

15 4. (0 pts) Short Answer Questions: Answer the questions briefly. Include diagrams and equations as needed. Be clear in your explanation and handwriting. A Draw the IV relationships between drain current and the drain-to-source voltage and gate-to-source voltage (I d vs. V GS and I d vs. V DS ) Label all relevant features. B What is short circuit power and how can you estimate it? The short circuit power is dissipated during switching when both the pull-up and pull down networks are operating above threshold and there is a short circuit current from power to ground. It can be estimated by approximating the peak current during switching and the time when short circuit current is present during switching. C What is a standard cell? A standard cell is a logic gate with a layout that follows a specified height and spacing requirements such that they align when cascaded together. 15

16 D What is crosstalk and how can it affect the performance of your design? Crosstalk is capacitive coupling between signal paths caused by the parasitic capacitance between the signal wires. It can increase delay in switching. E What affect does glitching have on energy consumption of a design? Be specific how/why it affects the energy. Glitching would increase energy consumption by increasing switching energy because of erroneous switching causing capacitve loads to go through a charge discharge cycle unnecessarily. 16

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