EE 330 Lecture 37. Digital Circuits. Other Logic Families. Propagation Delay basic characterization Device Sizing (Inverter and multipleinput gates)


 Aubrie Stevenson
 2 years ago
 Views:
Transcription
1 EE 330 Lecture 37 Digital Circuits Other Logic Families Static Power Dissipation Propagation Delay basic characterization Device Sizing (Inverter and multipleinput gates)
2 Review from Last Time Inverter Transfer Characteristics of Inverter Pair for THIS Logic Family V OUT V OUT VDD 1 VDD VTp VTp VTn VTRIP VDD VTn VTRIP VDD VDD+VTp VDD+VTp V H = and V L =0 V Tp Note this is independent of device sizing for THIS logic family!! V L V Tn +V Tp V TRIP V H
3 Review from Last Time Sizing of the Basic CMOS Inverter The characteristic that device sizes do not need to be used to establish V H and V L logic levels is a major advantage of this type of logic How should and be sized? How many degrees of freedom are there in the design of the inverter?
4 Review from Last Time How should and be sized? pick L 1 =L 2 =L min One popular sizing strategy: 1. Pick W 1 =W MIN to minimize area of 2. Pick W 2 to set trippoint at /2 Typically V Tn =0.2, V Tp =0.2 \ V TRIP V Tn V +V DD Tp 1 μ W L μ W L p 2 1 n 1 2 μ W L μ W L 0.2V V 0.2V VDD 2 μ W 1 μ W DD DD DD p 2 n 1 p 2 1 n 1 2 μ W μ W p 2 n 1 Solving this equation for W 2, obtain μ W W μ n 2 1 Other sizing strategies are used as well and will be discussed later! p
5 Extension of Basic CMOS Inverter to MultipleInput Gates A M 4 B M 3 Y A B Y Truth Table Performs as a 2input NOR Gate Can be easily extended to an ninput NOR Gate A B Y V H = and V L =0 (inherited from inverter analysis)
6 Extension of Basic CMOS Inverter to MultipleInput Gates A M 3 M 4 B Y A B Y Truth Table Performs as a 2input NAND Gate Can be easily extended to an ninput NAND Gate V H = and V L =0 (inherited from inverter analysis) A B Y
7 Static CMOS Logic Family Pullup Network PUN Pulldown Network PDN Observe PUN is pchannel, PDN is nchannel V H = and V L =0 (inherited from inverter analysis)
8 Static CMOS Logic Family M 4 M 3 M 4 A M 3 Y A Y B B M 4 M 3 M 4 A M 3 Y Y A B B nchannel PDN and pchannel PUN V H =, V L =0V (same as for inverter!)
9 General Logic Family PUN PUN PDN PDN Compound Gate in CMOS Process pchannel PUN nchannel PDN V H =, V L =0V (same as for inverter!) Arbitrary PUN and PDN
10 Other MOS Logic Families Enhancement Load NMOS Enhancement Load PseudoNMOS Depletion Load NMOS
11 Digital Circuit Design Hierarchical Design Basic Logic Gates Properties of Logic Families Characterization of CMOS Inverter Static CMOS Logic Gates Ratio Logic Propagation Delay Simple analytical models Elmore Delay Sizing of Gates Propagation Delay with Multiple Levels of Logic Optimal driving of Large Capacitive Loads Power Dissipation in Logic Circuits Other Logic Styles Array Logic Ring Oscillators done partial
12 Question:????? Why is V Tp V Tn /5 in many processes?????
13 Other CMOS/MOS Logic Families V Tn Enhancement Load NMOS
14 NMOS example VTH 1 W1/L1 4 W2/L2 1 VDD 5 File: Inv Char.xls Enhancement Load NMOS
15 NMOS example VTH 1 W1/L1 4 W2/L2 1 VDD 5 V H Enhancement Load NMOS V L V TRIP V H =4V V L =0.55V V TRIP =2V
16 Other CMOS/MOS Logic Families V Tn Enhancement Load NMOS High and low swings are reduced Response time is slow on LH output transitions Static Power Dissipation Large when is low Very economical process Termed ratio logic (because logic values dependent on device dimensions DOF!) May not work for some device sizes Compact layout (no wells!)
17 Other CMOS/MOS Logic Families A k k A 1 1 A 2 2 A k k A 1 2 Enhancement Load NMOS kinput NOR A 1 1 Multipleinput gates require single transistor for each additional input kinput NAND Still useful if many inputs are required (static power does not increase with k
18 Other CMOS/MOS Logic Families +V TP Enhancement Load PseudoNMOS High and low swings are reduced Response time is slow on LH output transitions Static Power Dissipation Large when is low Multipleinput gates require single transistor for each additional input Termed ratio logic
19 Other CMOS/MOS Logic Families Depletion Load NMOS V TD <0 Low swing is reduced Static Power Dissipation Large when is low Very economical process Termed ratio logic Compact layout (no wells!) Response time slow on LH output transitions Dominant MOS logic until about 1985 Depletion device not available in most processes today
20 Other CMOS/MOS Logic Families V Tn V OUT V OUT Enhancement Load NMOS V Tp V Tp Reduced V H V L Device sizing critical for even basic operation Shallow slope at V TRIP V Tn V Tn
21 Other CMOS/MOS Logic Families +V TP V OUT V OUT Enhancement Load PseudoNMOS V Tp V Tp Reduced V H V L Device sizing critical for even basic operation (DOF) Shallow slope at V TRIP V Tn V Tn
22 Other CMOS/MOS Logic Families V TD <0 V OUT V OUT Depletion Load NMOS Reduced V H V L Device sizing critical for even basic operation Shallow slope at V TRIP V Tp V Tn V Tn V Tp
23 Other CMOS/MOS Logic Families V TD <0 V OUT V OUT Depletion Load NMOS Reduced V H V L Device sizing critical for even basic operation Shallow slope at V TRIP V Tp V Tn V Tn V Tp
24 Static Power Dissipation in Static CMOS Family When is Low, I D1 =0 When is High, I D2 =0 Thus, P STATIC =0 This is a key property of the static CMOS Logic Family and is the major reason Static CMOS Logic is so dominant PUN PDN It can be shown that this zero static power dissipation property can be preserved if the PUN is comprised of pchannel devices, the PDN is comprised of nchannel devices and they are never both driven into the conducting states at the same time Compound Gate in CMOS Process
25 Static Power Dissipation in Ratio Logic Families Example: Assume =5V V T =1V, μc OX =104 A/V 2, W 1 /L 1 =1 and sized so that V L =V Tn Observe: V H = V Tn If =V H, =V L so Enhancement Load NMOS I I D1 D1 μc L 104 OX 1 W 1 V GS1 V T V 2 DS1 V mA 2 P L =(5V)(0.25mA)=1.25mW DS1
26 Static Power Dissipation in Ratio Logic Families Example: Assume =5V V T =1V, μc OX =104 A/V 2, W 1 /L 1 =1 and sized so that V L =V Tn P L =(5V)(0.25mA)=1.25mW If a circuit has 100,000 gates and half of them are in the =V L state, the static power dissipation will be Enhancement Load NMOS
27 Static Power Dissipation in Ratio Logic Families Example: Assume =5V V T =1V, μc OX =104 A/V 2, W 1 /L 1 =1 and sized so that V L =V Tn P L =(5V)(0.25mA)=1.25mW If a circuit has 100,000 gates and half of them are in the =V L state, the static power dissipation will be Enhancement Load NMOS 1 5 P STATIC mW W This power dissipation is way too high and would be even larger in circuits with 100 million or more gates the level of integration common in SoC circuits today
28 Propagation Delay in Static CMOS Family S R SWp V G C GSp G G D D R SWn C GSn V G S Switchlevel model of Static CMOS inverter (neglecting diffusion parasitics)
29 Propagation Delay in Static CMOS Family VDD S RSWp G VG D CGSp G CGSn RSWn VG D R PU S V G C IN R PD V G Switchlevel model of Static CMOS inverter (neglecting diffusion parasitics)
30 Propagation Delay in Static CMOS Family R PU V G Since operating in triode through most of transition: C IN R PD V G μcox W VDS ID VGS VT V L 2 VDS L1 RPD I μ C W V V D n OX 1 DD Tn DS μcox W L V GS V T V DS I D R μcox W V L PU C GS V T V 2 DS V DS μcox W L VDS L2 I μ C W V V IN D p OX 2 DD Tp C OX W L 1 1 W 2 L 2 V GS V T V DS
31 Propagation Delay in Static CMOS Family R PU V G R PD μ n C OX L1 W V 1 DD V Tn C IN R PD R PU μ p C OX L2 W V 2 DD V Tp V G C IN C OX W L 1 1 W 2 L 2 Example: Minimumsized and If u n C OX =100μAV 2, C OX =4 ffμ 2, V Tn = /5, V TP = /5, μ n /μ p =3, L 1 =W 1 =L, MIN L 2 =W 2 =L MIN, L MIN =0.5μ and =5V (Note: This C OX is somewhat larger than that in the 0.5u ON process) R PD V 2.5K 4 DD C IN L 2 MIN 2fF R PU 1 7.5K VDD 3
32 Propagation Delay in Static CMOS Family X Y R PU V G C IN R PD V G In typical process with Minimumsized and : R 2.5K PD R 3R 7.5K C PU IN PD 2fF
33 Propagation Delay in Static CMOS Family In typical process with Minimumsized and : X Y R 2.5K PD R 3R 7.5K C PU IN PD 2fF X C IN R PU V G R PD V G Y C IN R PU V G R PD V G Z How long does it take for a signal to propagate from x to y?
34 Propagation Delay in Static CMOS Family Consider: For HL output transition, C L charged to C L Ideally: t t=0 t t=0
35 Propagation Delay in Static CMOS Family For HL output transition, C L charged to C L Actually: t t=0 t t=0 What is the transition time t HL?
36 Propagation Delay in Static CMOS Family C L R PU V G C IN R PD V G C L
37 Propagation Delay in Static CMOS Family C L For HL output transition, C L charged to R PD C L t V G t=0 e 1 t V OUT V e DD t=0 t 1 t t R PD L t F I Fe 0 V 0e C V DD e t1 R C PD L DD t R 1 PDCL If V TRIP is close to /2, t HL is close to t 1
38 Propagation Delay in Static CMOS Family C L For HL output transition, C L charged to R PU C L t=0 t V G (1e 1 ) V TRIP t=0 t 2 t t t =R C LH 2 PU L Summary: tlh RPUCL t R C HL PD L For V TRIP close to /2
39 Propagation Delay in Static CMOS Family X Y C L In typical process with Minimumsized and : t R C 2.5K 2fF=5ps HL LH PD L t R C 7.5K 2fF=15ps PU L (Note: This C OX is somewhat larger than that in the 0.5u ON process) Note: LH transition is much slower than HL transition
40 Propagation Delay in Static CMOS Family Defn: The Propagation Delay of a gate is defined to be the sum of t HL and t LH, that is, t PROP =t HL +t LH t t +t C R R PROP HL LH L PU PD Propagation delay represents a fundamental limit on the speed a gate can be clocked For basic twoinverter cascade in static CMOS logic X Y In typical process with minimumsized and : t t +t 20 psec PROP HL LH
41 Propagation Delay in Static CMOS Family A F The propagation delay through k levels of logic is approximately the sum of the individual delays in the same path
42 Propagation Delay in Static CMOS Family Example: A Stage 1 Stage 2 Stage 3 Stage 4 F t HL =t HL4 +t LH3 +t HL2 +t LH1 t LH =t LH4 +t HL3 +t LH2 +t HL1 t PROP =t LH +t HL =(t LH4 +t HL3 +t LH2 +t HL1 )+ (t HL4 +t LH3 +t HL2 +t LH1 ) t PROP =t LH +t HL =(t LH4 +t HL4 )+(t LH3 +t HL3 )+ (t LH2 +t HL2 )+(t LH1 +t HL1 ) t PROP =t PROP4 +t PROP3 +t PROP2 +t PROP1
43 Propagation Delay in Static CMOS Family A F Propagation through k levels of logic t t + t + t + + t HL HLk LH(k1) HL k2 XY1 t t + t + t + + t LH LHk HL(k1) LH k2 YX1 where x=h and Y=L if k odd and X=L and Y=h if k even t PROP k i1 t PROPk Will return to propagation delay after we discuss device sizing
44 End of Lecture 37
EE 434 Lecture 33. Logic Design
EE 434 Lecture 33 Logic Design Review from last time: Ask the inverter how it will interpret logic levels V IN V OUT V H =? V L =? V LARGE V H V L V H Review from last time: The twoinverter loop X Y X
More informationEE 434 Lecture 34. Logic Design
EE 434 ecture 34 ogic Design Review from last time: Transfer characteristics of the static CMOS inverter (Neglect λ effects) Case 5 M cutoff, M triode V V > V V V Tp V < V Tn V V V Tp Transfer characteristics
More informationEE 330 Lecture 39. Digital Circuits. Propagation Delay basic characterization Device Sizing (Inverter and multipleinput gates)
EE 330 Lecture 39 Digital ircuits Propagation Delay basic characterization Device Sizing (Inverter and multipleinput gates) Review from last lecture Other MOS Logic Families Enhancement Load NMOS Enhancement
More informationEE 330 Lecture 36. Digital Circuits. Transfer Characteristics of the Inverter Pair One device sizing strategy Multipleinput gates
EE 330 Lecture 36 Digital Circuits Transfer Characteristics of the Inverter Pair One device sizing strategy Multipleinput gates Review from Last Time The basic logic gates It suffices to characterize
More informationEE 330 Lecture 17. MOSFET Modeling CMOS Process Flow
EE 330 Lecture 17 MOSFET Modeling CMOS Process Flow Review from Last Lecture Limitations of Existing Models V DD V OUT V OUT V DD?? V IN V OUT V IN V IN V DD SwitchLevel Models V DD Simple squarelaw
More informationEE 330 Lecture 18. Smallsignal Model (very preliminary) Bulk CMOS Process Flow
EE 330 Lecture 18 Smallsignal Model (very preliminary) Bulk CMOS Process Flow Review from Last Lecture How many models of the MOSFET do we have? Switchlevel model (2) Squarelaw model Squarelaw model
More informationECE 546 Lecture 10 MOS Transistors
ECE 546 Lecture 10 MOS Transistors Spring 2018 Jose E. SchuttAine Electrical & Computer Engineering University of Illinois jesa@illinois.edu NMOS Transistor NMOS Transistor NChannel MOSFET Built on ptype
More informationEE 330 Lecture 16. Devices in Semiconductor Processes. MOS Transistors
EE 330 Lecture 16 Devices in Semiconductor Processes MOS Transistors Review from Last Time Model Summary I D I V DS V S I B V BS = 0 0 VS VT W VDS ID = μcox VS VT VDS VS V VDS VS VT L T < W μc ( V V )
More informationEE 330 Lecture 16. MOS Device Modeling pchannel nchannel comparisons Model consistency and relationships CMOS Process Flow
EE 330 Lecture 16 MOS Device Modeling pchannel nchannel comparisons Model consistency and relationships CMOS Process Flow Review from Last Time Operation Regions by Applications Id I D 300 250 200 150
More informationEE 330 Lecture 16. MOSFET Modeling CMOS Process Flow
EE 330 Lecture 16 MOSFET Modeling CMOS Process Flow Model Extensions 300 Id 250 200 150 100 50 300 0 0 1 2 3 4 5 Vds Existing Model 250 200 Id 150 100 50 Slope is not 0 0 0 1 2 3 4 Actual Device Vds Model
More informationEE 230 Lecture 31. THE MOS TRANSISTOR Model Simplifcations THE Bipolar Junction TRANSISTOR
EE 23 Lecture 3 THE MOS TRANSISTOR Model Simplifcations THE Bipolar Junction TRANSISTOR Quiz 3 Determine I X. Assume W=u, L=2u, V T =V, uc OX =  4 A/V 2, λ= And the number is? 3 8 5 2? 6 4 9 7 Quiz 3
More informationProperties of CMOS Gates Snapshot
MOS logic 1 Properties of MOS Gates Snapshot High noise margins: V OH and V OL are at V DD and GND, respectively. No static power consumption: There never exists a direct path between V DD and V SS (GND)
More informationEE5780 Advanced VLSI CAD
EE5780 Advanced VLSI CAD Lecture 4 DC and Transient Responses, Circuit Delays Zhuo Feng 4.1 Outline Pass Transistors DC Response Logic Levels and Noise Margins Transient Response RC Delay Models Delay
More informationLecture 5: DC & Transient Response
Lecture 5: DC & Transient Response Outline q Pass Transistors q DC Response q Logic Levels and Noise Margins q Transient Response q RC Delay Models q Delay Estimation 2 Activity 1) If the width of a transistor
More informationFig. 1 CMOS Transistor Circuits (a) Inverter Out = NOT In, (b) NORgate C = NOT (A or B)
1 Introduction to TransistorLevel Logic Circuits 1 By Prawat Nagvajara At the transistor level of logic circuits, transistors operate as switches with the logic variables controlling the open or closed
More informationEE 330 Lecture 16. MOSFET Modeling CMOS Process Flow
EE 330 Lecture 16 MOFET Modeling CMO Process Flow Review from Last Lecture Limitations of Existing Models V V OUT V OUT V?? V IN V OUT V IN V IN V witchlevel Models V imple squarelaw Model Logic ate
More informationCHAPTER 15 CMOS DIGITAL LOGIC CIRCUITS
CHAPTER 5 CMOS DIGITAL LOGIC CIRCUITS Chapter Outline 5. CMOS Logic Gate Circuits 5. Digital Logic Inverters 5.3 The CMOS Inverter 5.4 Dynamic Operation of the CMOS Inverter 5.5 Transistor Sizing 5.6 Power
More informationExam 2 Fall How does the total propagation delay (T HL +T LH ) for an inverter sized for equal
EE 434 Exam 2 Fall 2006 Name Instructions. Students may bring 2 pages of notes to this exam. There are 10 questions and 5 problems. The questions are worth 2 points each and the problems are all worth
More informationLecture 6: DC & Transient Response
Lecture 6: DC & Transient Response Slides courtesy of Deming Chen Slides based on the initial set from David Harris CMOS VLSI Design Outline Pass Transistors DC Response Logic Levels and Noise Margins
More information9/18/2008 GMU, ECE 680 Physical VLSI Design
ECE680: Physical VLSI Design Chapter III CMOS Device, Inverter, Combinational circuit Logic and Layout Part 3 Combinational Logic Gates (textbook chapter 6) 9/18/2008 GMU, ECE 680 Physical VLSI Design
More informationEE 330 Lecture 6. Improved SwitchLevel Model Propagation Delay Stick Diagrams Technology Files
EE 330 Lecture 6 Improved witchlevel Model Propagation elay tick iagrams Technology Files Review from Last Time MO Transistor Qualitative iscussion of nchannel Operation Bulk ource Gate rain rain G Gate
More informationLecture 5: DC & Transient Response
Lecture 5: DC & Transient Response Outline Pass Transistors DC Response Logic Levels and Noise Margins Transient Response RC Delay Models Delay Estimation 2 Pass Transistors We have assumed source is grounded
More informationDC and Transient Responses (i.e. delay) (some comments on power too!)
DC and Transient Responses (i.e. delay) (some comments on power too!) Michael Niemier (Some slides based on lecture notes by David Harris) 1 Lecture 02  CMOS Transistor Theory & the Effects of Scaling
More informationEEE 421 VLSI Circuits
EEE 421 CMOS Properties Full railtorail swing high noise margins» Logic levels not dependent upon the relative device sizes transistors can be minimum size ratioless Always a path to V dd or GND in steady
More informationECE 342 Electronic Circuits. Lecture 34 CMOS Logic
ECE 34 Electronic Circuits Lecture 34 CMOS Logic Jose E. SchuttAine Electrical & Computer Engineering University of Illinois jesa@illinois.edu 1 De Morgan s Law Digital Logic  Generalization ABC... ABC...
More informationDigital Integrated Circuits A Design Perspective
igital Integrated Circuits esign Perspective esigning Combinational Logic Circuits 1 Combinational vs. Sequential Logic In Combinational Logic Circuit Out In Combinational Logic Circuit Out State Combinational
More informationECE 342 Solid State Devices & Circuits 4. CMOS
ECE 34 Solid State Devices & Circuits 4. CMOS Jose E. SchuttAine Electrical & Computer Engineering University of Illinois jschutt@emlab.uiuc.edu ECE 34 Jose Schutt Aine 1 Digital Circuits V IH : Input
More informationPower Dissipation. Where Does Power Go in CMOS?
Power Dissipation [Adapted from Chapter 5 of Digital Integrated Circuits, 2003, J. Rabaey et al.] Where Does Power Go in CMOS? Dynamic Power Consumption Charging and Discharging Capacitors Short Circuit
More informationEE141Microelettronica. CMOS Logic
Microelettronica CMOS Logic CMOS logic Power consumption in CMOS logic gates Where Does Power Go in CMOS? Dynamic Power Consumption Charging and Discharging Capacitors Short Circuit Currents Short Circuit
More informationName: Grade: Q1 Q2 Q3 Q4 Q5 Total. ESE370 Fall 2015
University of Pennsylvania Department of Electrical and System Engineering CircuitLevel Modeling, Design, and Optimization for Digital Systems ESE370, Fall 205 Midterm Wednesday, November 4 Point values
More informationMOS Transistor Theory
MOS Transistor Theory So far, we have viewed a MOS transistor as an ideal switch (digital operation) Reality: less than ideal EE 261 Krish Chakrabarty 1 Introduction So far, we have treated transistors
More informationECE 438: Digital Integrated Circuits Assignment #4 Solution The Inverter
ECE 438: Digital Integrated Circuits Assignment #4 The Inverter Text: Chapter 5, Digital Integrated Circuits 2 nd Ed, Rabaey 1) Consider the CMOS inverter circuit in Figure P1 with the following parameters.
More informationCMPEN 411 VLSI Digital Circuits. Lecture 04: CMOS Inverter (static view)
CMPEN 411 VLSI Digital Circuits Lecture 04: CMOS Inverter (static view) Kyusun Choi [Adapted from Rabaey s Digital Integrated Circuits, Second Edition, 2003 J. Rabaey, A. Chandrakasan, B. Nikolic] CMPEN
More informationHightoLow Propagation Delay t PHL
HightoLow Propagation Delay t PHL V IN switches instantly from low to high. Driver transistor (nchannel) immediately switches from cutoff to saturation; the pchannel pullup switches from triode to
More informationDigital Microelectronic Circuits ( ) Ratioed Logic. Lecture 8: Presented by: Mr. Adam Teman
Digital Microelectronic ircuits (36113021 ) Presented by: Mr. Adam Teman Lecture 8: atioed Logic 1 Motivation In the previous lecture, we learned about Standard MOS Digital Logic design. MOS is unquestionably
More informationESE570 Spring University of Pennsylvania Department of Electrical and System Engineering Digital Integrated Cicruits AND VLSI Fundamentals
University of Pennsylvania Department of Electrical and System Engineering Digital Integrated Cicruits AND VLSI Fundamentals ESE570, Spring 017 Final Wednesday, May 3 4 Problems with point weightings shown.
More information2007 Fall: Electronic Circuits 2 CHAPTER 10. DeogKyoon Jeong School of Electrical Engineering
007 Fall: Electronic Circuits CHAPTER 10 Digital CMOS Logic Circuits DeogKyoon Jeong dkjeong@snu.ac.kr k School of Electrical Engineering Seoul lnational luniversity it Introduction In this chapter, we
More informationEE 230 Lecture 33. Nonlinear Circuits and Nonlinear Devices. Diode BJT MOSFET
EE 230 Lecture 33 Nonlinear Circuits and Nonlinear Devices Diode BJT MOSFET Review from Last Time: nchannel MOSFET Source Gate L Drain W L EFF Poly Gate oxide nactive psub depletion region (electrically
More informationEE 466/586 VLSI Design. Partha Pande School of EECS Washington State University
EE 466/586 VLSI Design Partha Pande School of EECS Washington State University pande@eecs.wsu.edu Lecture 8 Power Dissipation in CMOS Gates Power in CMOS gates Dynamic Power Capacitance switching Crowbar
More informationDigital Integrated Circuits
Chapter 6 The CMOS Inverter 1 Contents Introduction (MOST models) 0, 1 st, 2 nd order The CMOS inverter : The static behavior: o DC transfer characteristics, o Shortcircuit current The CMOS inverter :
More informationIntegrated Circuits & Systems
Federal University of Santa Catarina Center for Technology Computer Science & Electronics Engineering Integrated Circuits & Systems INE 5442 Lecture 16 CMOS Combinational Circuits  2 guntzel@inf.ufsc.br
More informationCARNEGIE MELLON UNIVERSITY DEPARTMENT OF ELECTRICAL AND COMPUTER ENGINEERING DIGITAL INTEGRATED CIRCUITS FALL 2002
CARNEGIE MELLON UNIVERSITY DEPARTMENT OF ELECTRICAL AND COMPUTER ENGINEERING 18322 DIGITAL INTEGRATED CIRCUITS FALL 2002 Final Examination, Monday Dec. 16, 2002 NAME: SECTION: Time: 180 minutes Closed
More informationEE141Fall 2011 Digital Integrated Circuits
EE4Fall 20 Digital Integrated Circuits Lecture 5 Memory decoders Administrative Stuff Homework #6 due today Project posted Phase due next Friday Project done in pairs 2 Last Lecture Last lecture Logical
More information! Charge Leakage/Charge Sharing. " Domino Logic Design Considerations. ! Logic Comparisons. ! Memory. " Classification. " ROM Memories.
ESE 57: Digital Integrated Circuits and VLSI Fundamentals Lec 9: March 9, 8 Memory Overview, Memory Core Cells Today! Charge Leakage/ " Domino Logic Design Considerations! Logic Comparisons! Memory " Classification
More informationTHE INVERTER. Inverter
THE INVERTER DIGITAL GATES Fundamental Parameters Functionality Reliability, Robustness Area Performance» Speed (delay)» Power Consumption» Energy Noise in Digital Integrated Circuits v(t) V DD i(t) (a)
More informationECE 342 Electronic Circuits. Lecture 35 CMOS Delay Model
ECE 34 Electronic Circuits Lecture 35 CMOS Delay Model Jose E. SchuttAine Electrical & Computer Engineering University of Illinois jesa@illinois.edu ECE 34 Jose Schutt Aine 1 Digital Circuits V IH : Input
More informationAnnouncements. EE141 Fall 2002 Lecture 7. MOS Capacitances Inverter Delay Power
 Fall 2002 Lecture 7 MOS Capacitances Inverter Delay Power Announcements Wednesday 123pm lab cancelled Lab 4 this week Homework 2 due today at 5pm Homework 3 posted tonight Today s lecture MOS capacitances
More informationMOS Transistor Theory
CHAPTER 3 MOS Transistor Theory Outline 2 1. Introduction 2. Ideal IV Characteristics 3. Nonideal IV Effects 4. CV Characteristics 5. DC Transfer Characteristics 6. Switchlevel RC Delay Models MOS
More informationLecture 4: DC & Transient Response
Introduction to CMOS VLSI Design Lecture 4: DC & Transient Response David Harris Harvey Mudd College Spring 004 Outline DC Response Logic Levels and Noise Margins Transient Response Delay Estimation Slide
More informationECE321 Electronics I
ECE31 Electronics Lecture 1: CMOS nverter: Noise Margin & Delay Model Payman ZarkeshHa Office: ECE Bldg. 30B Office hours: Tuesday :003:00PM or by appointment Email: payman@ece.unm.edu Slide: 1 CMOS
More informationENGR890 Digital VLSI Design Fall Lecture 4: CMOS Inverter (static view)
ENGR89 Digital VLSI Design Fall 5 Lecture 4: CMOS Inverter (static view) [Adapted from Chapter 5 of Digital Integrated Circuits, 3, J. Rabaey et al.] [Also borrowed from Vijay Narayanan and Mary Jane Irwin]
More informationCPE/EE 427, CPE 527 VLSI Design I Delay Estimation. Department of Electrical and Computer Engineering University of Alabama in Huntsville
CPE/EE 47, CPE 57 VLSI Design I Delay Estimation Department of Electrical and Computer Engineering University of labama in Huntsville leksandar Milenkovic ( www.ece.uah.edu/~milenka ) Review: CMOS Circuit
More informationESE 570: Digital Integrated Circuits and VLSI Fundamentals
ESE 570: Digital Integrated Circuits and VLSI Fundamentals Lec 15: March 15, 2018 Euler Paths, Energy Basics and Optimization Midterm! Midterm " Mean: 89.7 " Standard Dev: 8.12 2 Lecture Outline! Euler
More informationDC and Transient. Courtesy of Dr. Daehyun Dr. Dr. Shmuel and Dr.
DC and Transient Courtesy of Dr. Daehyun Lim@WSU, Dr. Harris@HMC, Dr. Shmuel Wimer@BIU and Dr. Choi@PSU http://csce.uark.edu +1 (479) 575604 yrpeng@uark.edu Pass Transistors We have assumed source is
More informationVery Large Scale Integration (VLSI)
Very Large Scale Integration (VLSI) Lecture 4 Dr. Ahmed H. Madian Ah_madian@hotmail.com Dr. Ahmed H. MadianVLSI Contents Delay estimation Simple RC model PenfieldRubenstein Model Logical effort Delay
More informationLecture 12 Digital Circuits (II) MOS INVERTER CIRCUITS
Lecture 12 Digital Circuits (II) MOS INVERTER CIRCUITS Outline NMOS inverter with resistor pullup The inverter NMOS inverter with currentsource pullup Complementary MOS (CMOS) inverter Static analysis
More informationCMOS INVERTER. Last Lecture. Metrics for qualifying digital circuits. »Cost» Reliability» Speed (delay)»performance
CMOS INVERTER Last Lecture Metrics for qualifying digital circuits»cost» Reliability» Speed (delay)»performance 1 Today s lecture The CMOS inverter at a glance An MOS transistor model for manual analysis
More informationEE 330 Class Seating
1 2 3 4 5 6 EE 330 Class Seating 1 2 3 4 5 6 7 8 Zechariah Daniel Liuchang Andrew Brian Difeng Aimee Julien Di Pettit Borgerding Li Mun Crist Liu Salt Tria Erik Nick Bijan Wing Yi Pangzhou Travis Wentai
More informationDigital Integrated Circuits A Design Perspective
Digital Integrated Circuits Design Perspective Jan M. Rabaey nantha Chandrakasan orivoje Nikolić Designing Combinational Logic Circuits November 2002. 1 Combinational vs. Sequential Logic In Combinational
More informationMidterm. ESE 570: Digital Integrated Circuits and VLSI Fundamentals. Lecture Outline. Pass Transistor Logic. Restore Output.
ESE 570: Digital Integrated Circuits and VLSI Fundamentals Lec 16: March 21, 2017 Transmission Gates, Euler Paths, Energy Basics Review Midterm! Midterm " Mean: 79.5 " Standard Dev: 14.5 2 Lecture Outline!
More informationSpiral 2 7. Capacitance, Delay and Sizing. Mark Redekopp
27.1 Spiral 2 7 Capacitance, Delay and Sizing Mark Redekopp 27.2 Learning Outcomes I understand the sources of capacitance in CMOS circuits I understand how delay scales with resistance, capacitance
More informationEECS 141: FALL 05 MIDTERM 1
University of California College of Engineering Department of Electrical Engineering and Computer Sciences D. Markovic TuTh 111:3 Thursday, October 6, 6:38:pm EECS 141: FALL 5 MIDTERM 1 NAME Last SOLUTION
More informationCMOS Inverter (static view)
Review: Design Abstraction Levels SYSTEM CMOS Inverter (static view) + MODULE GATE [Adapted from Chapter 5. 5.3 CIRCUIT of G DEVICE Rabaey s Digital Integrated Circuits,, J. Rabaey et al.] S D Review:
More informationEE115C Digital Electronic Circuits Homework #4
EE115 Digital Electronic ircuits Homework #4 Problem 1 Power Dissipation Solution Vdd =1.0V onsider the source follower circuit used to drive a load L =20fF shown above. M1 and M2 are both NMOS transistors
More informationUniversity of Toronto. Final Exam
University of Toronto Final Exam Date  Apr 18, 011 Duration:.5 hrs ECE334 Digital Electronics Lecturer  D. Johns ANSWER QUESTIONS ON THESE SHEETS USING BACKS IF NECESSARY 1. Equation sheet is on last
More informationESE 570: Digital Integrated Circuits and VLSI Fundamentals
ESE 570: Digital Integrated Circuits and VLSI Fundamentals Lec 19: March 29, 2018 Memory Overview, Memory Core Cells Today! Charge Leakage/Charge Sharing " Domino Logic Design Considerations! Logic Comparisons!
More informationChapter 11. Inverter. DC AC, Switching. Layout. Sizing PASS GATES (CHPT 10) Other Inverters. Baker Ch. 11 The Inverter. Introduction to VLSI
Chapter 11 Inverter DC AC, Switching Ring Oscillator Dynamic Power Dissipation Layout LATCHUP Sizing PASS GATES (CHPT 10) Other Inverters Joseph A. Elias, Ph.D. Adjunct Professor, University of Kentucky;
More information5. CMOS Gate Characteristics CS755
5. CMOS Gate Characteristics Last module: CMOS Transistor theory This module: DC Response Logic Levels and Noise Margins Transient Response Delay Estimation Transistor ehavior 1) If the width of a transistor
More informationEECS 141: SPRING 09 MIDTERM 2
University of California College of Engineering Department of Electrical Engineering and Computer Sciences J. Rabaey WeFr 23:30pm We, April 22, 2:003:30pm EECS 141: SPRING 09 MIDTERM 2 NAME Last First
More informationDigital Integrated Circuits A Design Perspective
Designing ombinational Logic ircuits dapted from hapter 6 of Digital Integrated ircuits Design Perspective Jan M. Rabaey et al. opyright 2003 Prentice Hall/Pearson 1 ombinational vs. Sequential Logic In
More informationThe Physical Structure (NMOS)
The Physical Structure (NMOS) Al SiO2 Field Oxide Gate oxide S n+ Polysilicon Gate Al SiO2 SiO2 D n+ L channel P Substrate Field Oxide contact Metal (S) n+ (G) L W n+ (D) Poly 1 Transistor Resistance Two
More informationEE 466/586 VLSI Design. Partha Pande School of EECS Washington State University
EE 466/586 VLSI Design Partha Pande School of EECS Washington State University pande@eecs.wsu.edu Lecture 9 Propagation delay Power and delay Tradeoffs Follow board notes Propagation Delay Switching Time
More informationLecture 12 Circuits numériques (II)
Lecture 12 Circuits numériques (II) Circuits inverseurs MOS Outline NMOS inverter with resistor pullup The inverter NMOS inverter with currentsource pullup Complementary MOS (CMOS) inverter Static analysis
More informationCMOS Digital Integrated Circuits Lec 10 Combinational CMOS Logic Circuits
Lec 10 Combinational CMOS Logic Circuits 1 Combinational vs. Sequential Logic In Combinational Logic circuit Out In Combinational Logic circuit Out State Combinational The output is determined only by
More informationDigital Integrated Circuits A Design Perspective
Digital Integrated Circuits Design Perspective Designing Combinational Logic Circuits Fuyuzhuo School of Microelectronics,SJTU Introduction Digital IC Dynamic Logic Introduction Digital IC 2 EE141 Dynamic
More informationESE 570 MOS INVERTERS STATIC (DC Steady State) CHARACTERISTICS. Kenneth R. Laker, University of Pennsylvania, updated 12Feb15
ESE 570 MOS INVERTERS STATIC (DC Steady State) CHARACTERISTICS 1 VDD Vout Vin Ideal VTC Logic 0 = 0 V Logic 1 = VDD 0 2 VOH VDD VOL 0 o.c. Cout For DC steadystate Cout is open circuit. VDD 0 VDD VOL VT0n
More informationL ECE 4211 UConn F. Jain Scaling Laws for NanoFETs Chapter 10 Logic Gate Scaling
L13 04202017 ECE 4211 UConn F. Jain Scaling Laws for NanoFETs Chapter 10 Logic Gate Scaling Scaling laws: Generalized scaling (GS) p. 610 Design steps p.613 Nanotransistor issues (page 626) Degradation
More informationENEE 359a Digital VLSI Design
SLIDE 1 ENEE 359a Digital VLSI Design Prof. blj@eng.umd.edu Credit where credit is due: Slides contain original artwork ( Jacob 2004) as well as material taken liberally from Irwin & Vijay s CSE477 slides
More informationCOMP 103. Lecture 16. Dynamic Logic
COMP 03 Lecture 6 Dynamic Logic Reading: 6.3, 6.4 [ll lecture notes are adapted from Mary Jane Irwin, Penn State, which were adapted from Rabaey s Digital Integrated Circuits, 2002, J. Rabaey et al.] COMP03
More information2. (2pts) What is the major difference between an epitaxial layer and a polysilicon layer?
EE 330 Exam 1 Spring 2017 Name Instructions: Students may bring 1 page of notes (front and back) to this exam and a calculator but the use of any device that has wireless communication capability is prohibited.
More informationCPE/EE 427, CPE 527 VLSI Design I L06: CMOS Inverter, CMOS Logic Gates. Course Administration. CMOS Inverter: A First Look
CPE/EE 47, CPE 57 VLSI esign I L6: CMOS Inverter, CMOS Logic Gates epartment of Electrical and Computer Engineering University of labama in Huntsville leksandar Milenkovic ( www.ece.uah.edu/~milenka )
More informationECE 342 Electronic Circuits. 3. MOS Transistors
ECE 342 Electronic Circuits 3. MOS Transistors Jose E. SchuttAine Electrical & Computer Engineering University of Illinois jschutt@emlab.uiuc.edu 1 NMOS Transistor Typically L = 0.1 to 3 m, W = 0.2 to
More informationCOMBINATIONAL LOGIC. Combinational Logic
COMINTIONL LOGIC Overview Static CMOS Conventional Static CMOS Logic Ratioed Logic Pass Transistor/Transmission Gate Logic Dynamic CMOS Logic Domino npcmos Combinational vs. Sequential Logic In Logic
More information3. Design a stick diagram for the PMOS logic shown below [16] Y = (A + B).C. 4. Design a layout diagram for the CMOS logic shown below [16]
Code No: RR420203 Set No. 1 1. (a) Find g m and r ds for an nchannel transistor with V GS = 1.2V; V tn = 0.8V; W/L = 10; µncox = 92 µa/v 2 and V DS = Veff + 0.5V The out put impedance constant. λ = 95.3
More information4.10 The CMOS Digital Logic Inverter
11/11/2004 section 4_10 The CMOS Digital Inverter blank.doc 1/1 4.10 The CMOS Digital Logic Inverter Reading Assignment: pp. 336346 Complementary MOSFET (CMOS) is the predominant technology for constructing
More informationToday s lecture. EE141 Spring 2003 Lecture 4. Design Rules CMOS Inverter MOS Transistor Model
 Spring 003 Lecture 4 Design Rules CMOS Inverter MOS Transistor Model Today s lecture Design Rules The CMOS inverter at a glance An MOS transistor model for manual analysis Important! Labs start next
More informationPMOS Device and CMOS Inverters
Lecture 23 PMOS Device and CMOS Inverters A) PMOS Device Structure and Oeration B) Relation of Current to t OX, µ V LIMIT C) CMOS Device Equations and Use D) CMOS Inverter V OUT vs. V IN E) CMOS Short
More informationPASSTRANSISTOR LOGIC. INEL Fall 2014
PASSTRANSISTOR LOGIC INEL 4207  Fall 2014 Figure 15.5 Conceptual passtransistor logic gates. (a) Two switches, controlled by the input variables B and C, when connected in series in the path between
More informationCircuit A. Circuit B
UNIVERSITY OF CALIFORNIA College of Engineering Department of Electrical Engineering and Computer Sciences Last modified on November 19, 2006 by Karl Skucha (kskucha@eecs) Borivoje Nikolić Homework #9
More informationLecture 14  Digital Circuits (III) CMOS. April 1, 2003
6.12  Microelectronic Devices and Circuits  Spring 23 Lecture 141 Lecture 14  Digital Circuits (III) CMOS April 1, 23 Contents: 1. Complementary MOS (CMOS) inverter: introduction 2. CMOS inverter:
More informationCMOS Inverter: CPE/EE 427, CPE 527 VLSI Design I L06: CMOS Inverter, CMOS Logic Gates. Course Administration. CMOS Properties.
CMOS Inverter: Steady State Response CPE/EE 47, CPE 57 VLSI esign I L6: CMOS Inverter, CMOS Logic Gates R p V OL = V OH = V M = f(r n, R p ) epartment of Electrical and Computer Engineering University
More informationEE213, Spr 2017 HW#3 Due: May 17 th, in class. Figure 1
RULES: Please try to work on your own. Discussion is permissible, but identical submissions are unacceptable! Please show all intermediate steps: a correct solution without an explanation will get zero
More informationS No. Questions Bloom s Taxonomy Level UNITI
GROUPA (SHORT ANSWER QUESTIONS) S No. Questions Bloom s UNITI 1 Define oxidation & Classify different types of oxidation Remember 1 2 Explain about Ion implantation Understand 1 3 Describe lithography
More informationLecture 13  Digital Circuits (II) MOS Inverter Circuits. March 20, 2003
6.012 Microelectronic Devices and Circuits Spring 2003 Lecture 131 Lecture 13 Digital Circuits (II) MOS Inverter Circuits March 20, 2003 Contents: 1. NMOS inverter with resistor pullup (cont.) 2. NMOS
More informationDigital Microelectronic Circuits ( ) The CMOS Inverter. Lecture 4: Presented by: Adam Teman
Digital Microelectronic Circuits (3611301 ) Presented by: Adam Teman Lecture 4: The CMOS Inverter 1 Last Lectures Moore s Law Terminology» Static Properties» Dynamic Properties» Power The MOSFET Transistor»
More informationESE 570: Digital Integrated Circuits and VLSI Fundamentals
ESE 570: Digital Integrated Circuits and VLSI Fundamentals Lec 18: March 27, 2018 Dynamic Logic, Charge Injection Lecture Outline! Sequential MOS Logic " DLatch " Timing Constraints! Dynamic Logic " Domino
More informationCMOS Digital Integrated Circuits Lec 13 Semiconductor Memories
Lec 13 Semiconductor Memories 1 Semiconductor Memory Types Semiconductor Memories Read/Write (R/W) Memory or Random Access Memory (RAM) ReadOnly Memory (ROM) Dynamic RAM (DRAM) Static RAM (SRAM) 1. Mask
More informationEE105  Fall 2006 Microelectronic Devices and Circuits
EE105  Fall 2006 Microelectronic Devices and Circuits Prof. Jan M. Rabaey (jan@eecs) Lecture 7: MOS Transistor Some Administrative Issues Lab 2 this week Hw 2 due on We Hw 3 will be posted same day MIDTERM
More informationMOS Transistor IV Characteristics and Parasitics
ECEN454 Digital Integrated Circuit Design MOS Transistor IV Characteristics and Parasitics ECEN 454 Facts about Transistors So far, we have treated transistors as ideal switches An ON transistor passes
More informationCMPEN 411 VLSI Digital Circuits Spring 2011 Lecture 07: Pass Transistor Logic
CMPEN 411 VLSI Digital Circuits Spring 2011 Lecture 07: Pass Transistor Logic [dapted from Rabaey s Digital Integrated Circuits, Second Edition, 2003 J. Rabaey,. Chandrakasan,. Nikolic] Sp11 CMPEN 411
More information