EE 330 Lecture 37. Digital Circuits. Other Logic Families. Propagation Delay basic characterization Device Sizing (Inverter and multiple-input gates)

Transcription

1 EE 330 Lecture 37 Digital Circuits Other Logic Families Static Power Dissipation Propagation Delay basic characterization Device Sizing (Inverter and multiple-input gates)

2 Review from Last Time Inverter Transfer Characteristics of Inverter Pair for THIS Logic Family V OUT V OUT VDD 1 VDD VTp -VTp -VTn VTRIP VDD -VTn VTRIP VDD VDD+VTp VDD+VTp V H = and V L =0 -V Tp Note this is independent of device sizing for THIS logic family!! V L -V Tn +V Tp V TRIP V H

3 Review from Last Time Sizing of the Basic CMOS Inverter The characteristic that device sizes do not need to be used to establish V H and V L logic levels is a major advantage of this type of logic How should and be sized? How many degrees of freedom are there in the design of the inverter?

4 Review from Last Time How should and be sized? pick L 1 =L 2 =L min One popular sizing strategy: 1. Pick W 1 =W MIN to minimize area of 2. Pick W 2 to set trip-point at /2 Typically V Tn =0.2, V Tp =0.2 \ V TRIP V Tn V +V DD Tp 1 μ W L μ W L p 2 1 n 1 2 μ W L μ W L 0.2V V -0.2V VDD 2 μ W 1 μ W DD DD DD p 2 n 1 p 2 1 n 1 2 μ W μ W p 2 n 1 Solving this equation for W 2, obtain μ W W μ n 2 1 Other sizing strategies are used as well and will be discussed later! p

5 Extension of Basic CMOS Inverter to Multiple-Input Gates A M 4 B M 3 Y A B Y Truth Table Performs as a 2-input NOR Gate Can be easily extended to an n-input NOR Gate A B Y V H = and V L =0 (inherited from inverter analysis)

6 Extension of Basic CMOS Inverter to Multiple-Input Gates A M 3 M 4 B Y A B Y Truth Table Performs as a 2-input NAND Gate Can be easily extended to an n-input NAND Gate V H = and V L =0 (inherited from inverter analysis) A B Y

7 Static CMOS Logic Family Pull-up Network PUN Pull-down Network PDN Observe PUN is p-channel, PDN is n-channel V H = and V L =0 (inherited from inverter analysis)

8 Static CMOS Logic Family M 4 M 3 M 4 A M 3 Y A Y B B M 4 M 3 M 4 A M 3 Y Y A B B n-channel PDN and p-channel PUN V H =, V L =0V (same as for inverter!)

9 General Logic Family PUN PUN PDN PDN Compound Gate in CMOS Process p-channel PUN n-channel PDN V H =, V L =0V (same as for inverter!) Arbitrary PUN and PDN

10 Other MOS Logic Families Enhancement Load NMOS Enhancement Load Pseudo-NMOS Depletion Load NMOS

11 Digital Circuit Design Hierarchical Design Basic Logic Gates Properties of Logic Families Characterization of CMOS Inverter Static CMOS Logic Gates Ratio Logic Propagation Delay Simple analytical models Elmore Delay Sizing of Gates Propagation Delay with Multiple Levels of Logic Optimal driving of Large Capacitive Loads Power Dissipation in Logic Circuits Other Logic Styles Array Logic Ring Oscillators done partial

12 Question:????? Why is V Tp V Tn /5 in many processes?????

13 Other CMOS/MOS Logic Families -V Tn Enhancement Load NMOS

14 NMOS example VTH 1 W1/L1 4 W2/L2 1 VDD 5 File: Inv Char.xls Enhancement Load NMOS

15 NMOS example VTH 1 W1/L1 4 W2/L2 1 VDD 5 V H Enhancement Load NMOS V L V TRIP V H =4V V L =0.55V V TRIP =2V

16 Other CMOS/MOS Logic Families -V Tn Enhancement Load NMOS High and low swings are reduced Response time is slow on LH output transitions Static Power Dissipation Large when is low Very economical process Termed ratio logic (because logic values dependent on device dimensions DOF!) May not work for some device sizes Compact layout (no wells!)

17 Other CMOS/MOS Logic Families A k k A 1 1 A 2 2 A k k A 1 2 Enhancement Load NMOS k-input NOR A 1 1 Multiple-input gates require single transistor for each additional input k-input NAND Still useful if many inputs are required (static power does not increase with k

18 Other CMOS/MOS Logic Families +V TP Enhancement Load Pseudo-NMOS High and low swings are reduced Response time is slow on LH output transitions Static Power Dissipation Large when is low Multiple-input gates require single transistor for each additional input Termed ratio logic

19 Other CMOS/MOS Logic Families Depletion Load NMOS V TD <0 Low swing is reduced Static Power Dissipation Large when is low Very economical process Termed ratio logic Compact layout (no wells!) Response time slow on L-H output transitions Dominant MOS logic until about 1985 Depletion device not available in most processes today

20 Other CMOS/MOS Logic Families -V Tn V OUT V OUT Enhancement Load NMOS -V Tp -V Tp Reduced V H -V L Device sizing critical for even basic operation Shallow slope at V TRIP -V Tn -V Tn

21 Other CMOS/MOS Logic Families +V TP V OUT V OUT Enhancement Load Pseudo-NMOS -V Tp -V Tp Reduced V H -V L Device sizing critical for even basic operation (DOF) Shallow slope at V TRIP -V Tn -V Tn

22 Other CMOS/MOS Logic Families V TD <0 V OUT V OUT Depletion Load NMOS Reduced V H -V L Device sizing critical for even basic operation Shallow slope at V TRIP -V Tp -V Tn -V Tn -V Tp

23 Other CMOS/MOS Logic Families V TD <0 V OUT V OUT Depletion Load NMOS Reduced V H -V L Device sizing critical for even basic operation Shallow slope at V TRIP -V Tp -V Tn -V Tn -V Tp

24 Static Power Dissipation in Static CMOS Family When is Low, I D1 =0 When is High, I D2 =0 Thus, P STATIC =0 This is a key property of the static CMOS Logic Family and is the major reason Static CMOS Logic is so dominant PUN PDN It can be shown that this zero static power dissipation property can be preserved if the PUN is comprised of p-channel devices, the PDN is comprised of n-channel devices and they are never both driven into the conducting states at the same time Compound Gate in CMOS Process

25 Static Power Dissipation in Ratio Logic Families Example: Assume =5V V T =1V, μc OX =10-4 A/V 2, W 1 /L 1 =1 and sized so that V L =V Tn Observe: V H = -V Tn If =V H, =V L so Enhancement Load NMOS I I D1 D1 μc L 10-4 OX 1 W 1 V GS1 V T V 2 DS1 V mA 2 P L =(5V)(0.25mA)=1.25mW DS1

26 Static Power Dissipation in Ratio Logic Families Example: Assume =5V V T =1V, μc OX =10-4 A/V 2, W 1 /L 1 =1 and sized so that V L =V Tn P L =(5V)(0.25mA)=1.25mW If a circuit has 100,000 gates and half of them are in the =V L state, the static power dissipation will be Enhancement Load NMOS

27 Static Power Dissipation in Ratio Logic Families Example: Assume =5V V T =1V, μc OX =10-4 A/V 2, W 1 /L 1 =1 and sized so that V L =V Tn P L =(5V)(0.25mA)=1.25mW If a circuit has 100,000 gates and half of them are in the =V L state, the static power dissipation will be Enhancement Load NMOS 1 5 P STATIC mW W This power dissipation is way too high and would be even larger in circuits with 100 million or more gates the level of integration common in SoC circuits today

28 Propagation Delay in Static CMOS Family S R SWp V G C GSp G G D D R SWn C GSn V G S Switch-level model of Static CMOS inverter (neglecting diffusion parasitics)

29 Propagation Delay in Static CMOS Family VDD S RSWp G VG D CGSp G CGSn RSWn VG D R PU S V G C IN R PD V G Switch-level model of Static CMOS inverter (neglecting diffusion parasitics)

30 Propagation Delay in Static CMOS Family R PU V G Since operating in triode through most of transition: C IN R PD V G μcox W VDS ID VGS VT V L 2 VDS L1 RPD I μ C W V V D n OX 1 DD Tn DS μcox W L V GS V T V DS I D R μcox W V L PU C GS V T V 2 DS V DS μcox W L VDS L2 I μ C W V V IN D p OX 2 DD Tp C OX W L 1 1 W 2 L 2 V GS V T V DS

31 Propagation Delay in Static CMOS Family R PU V G R PD μ n C OX L1 W V 1 DD V Tn C IN R PD R PU μ p C OX L2 W V 2 DD V Tp V G C IN C OX W L 1 1 W 2 L 2 Example: Minimum-sized and If u n C OX =100μAV -2, C OX =4 ffμ -2, V Tn = /5, V TP =- /5, μ n /μ p =3, L 1 =W 1 =L, MIN L 2 =W 2 =L MIN, L MIN =0.5μ and =5V (Note: This C OX is somewhat larger than that in the 0.5u ON process) R PD V 2.5K -4 DD C IN L 2 MIN 2fF R PU 1 7.5K VDD 3

32 Propagation Delay in Static CMOS Family X Y R PU V G C IN R PD V G In typical process with Minimum-sized and : R 2.5K PD R 3R 7.5K C PU IN PD 2fF

33 Propagation Delay in Static CMOS Family In typical process with Minimum-sized and : X Y R 2.5K PD R 3R 7.5K C PU IN PD 2fF X C IN R PU V G R PD V G Y C IN R PU V G R PD V G Z How long does it take for a signal to propagate from x to y?

34 Propagation Delay in Static CMOS Family Consider: For HL output transition, C L charged to C L Ideally: t t=0 t t=0

35 Propagation Delay in Static CMOS Family For HL output transition, C L charged to C L Actually: t t=0 t t=0 What is the transition time t HL?

36 Propagation Delay in Static CMOS Family C L R PU V G C IN R PD V G C L

37 Propagation Delay in Static CMOS Family C L For HL output transition, C L charged to R PD C L t V G t=0 e -1 t V OUT V e DD t=0 t 1 t t R PD L t F I Fe 0 V 0e C V DD e t1 R C PD L DD t R 1 PDCL If V TRIP is close to /2, t HL is close to t 1

38 Propagation Delay in Static CMOS Family C L For HL output transition, C L charged to R PU C L t=0 t V G (1-e -1 ) V TRIP t=0 t 2 t t t =R C LH 2 PU L Summary: tlh RPUCL t R C HL PD L For V TRIP close to /2

39 Propagation Delay in Static CMOS Family X Y C L In typical process with Minimum-sized and : t R C 2.5K 2fF=5ps HL LH PD L t R C 7.5K 2fF=15ps PU L (Note: This C OX is somewhat larger than that in the 0.5u ON process) Note: LH transition is much slower than HL transition

40 Propagation Delay in Static CMOS Family Defn: The Propagation Delay of a gate is defined to be the sum of t HL and t LH, that is, t PROP =t HL +t LH t t +t C R R PROP HL LH L PU PD Propagation delay represents a fundamental limit on the speed a gate can be clocked For basic two-inverter cascade in static CMOS logic X Y In typical process with minimum-sized and : t t +t 20 psec PROP HL LH

41 Propagation Delay in Static CMOS Family A F The propagation delay through k levels of logic is approximately the sum of the individual delays in the same path

42 Propagation Delay in Static CMOS Family Example: A Stage 1 Stage 2 Stage 3 Stage 4 F t HL =t HL4 +t LH3 +t HL2 +t LH1 t LH =t LH4 +t HL3 +t LH2 +t HL1 t PROP =t LH +t HL =(t LH4 +t HL3 +t LH2 +t HL1 )+ (t HL4 +t LH3 +t HL2 +t LH1 ) t PROP =t LH +t HL =(t LH4 +t HL4 )+(t LH3 +t HL3 )+ (t LH2 +t HL2 )+(t LH1 +t HL1 ) t PROP =t PROP4 +t PROP3 +t PROP2 +t PROP1

43 Propagation Delay in Static CMOS Family A F Propagation through k levels of logic t t + t + t + + t HL HLk LH(k-1) HL k-2 XY1 t t + t + t + + t LH LHk HL(k-1) LH k-2 YX1 where x=h and Y=L if k odd and X=L and Y=h if k even t PROP k i1 t PROPk Will return to propagation delay after we discuss device sizing

44 End of Lecture 37