# ESE 570: Digital Integrated Circuits and VLSI Fundamentals

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1 ESE 570: Digital Integrated Circuits and VLSI Fundamentals Lec 10: February 15, 2018 MOS Inverter: Dynamic Characteristics Penn ESE 570 Spring 2018 Khanna

2 Lecture Outline! Inverter Power! Dynamic Characteristics " Delay Penn ESE 570 Spring 2018 Khanna 3

3 Inverter Power Penn ESE 570 Spring 2018 Khanna

4 Power! P = I V! Tricky part: " Understanding I " (pairing with correct V) Penn ESE 570 Spring 2018 Khanna 5

5 Static Current! P = I static V DD Penn ESE 570 Spring 2018 Khanna 6

6 Switching Currents! Dynamic current flow:! If both transistor on: " Current path from V dd to Gnd " Short circuit current Penn ESE 570 Spring 2018 Khanna 7

7 Currents Summary! I changes over time! At least two components " I static no switching " I switch when switching " I dyn and I sc CLK φ ramp_enable V RAMP Penn ESE 570 Spring 2018 Khanna 8

8 Switching Dynamic Power Penn ESE 570 Spring Khanna 9

9 Switching Currents! I total (t) = I static (t)+i switch (t)! I switch (t) = I sc (t) + I dyn (t) I dyn I static I sc Penn ESE 570 Spring Khanna 10

10 Charging! I dyn (t) why is it changing? " I ds = f(v ds,v gs ) " and V gs, V ds changing I DS ν sat C OX W V GS V T V DSAT ' & 2 I DS = µ n C OX " \$ # W L ( * ) ) ' ( V & GS V T )V DS V 2 DS + * 2,. - Penn ESE 570 Spring Khanna 11

11 Switching Energy focus on I dyn (t) I dyn I static I sc Penn ESE 570 Spring Khanna 12

12 Switching Energy focus on I dyn (t) I dyn E = P(t)dt = I(t)V dd dt = V dd I(t)dt Penn ESE 570 Spring Khanna 13

13 Switching Energy! Do we know what this is? I dyn (t)dt I dyn E = P(t)dt = I(t)V dd dt = V dd I(t)dt Penn ESE 570 Spring Khanna 14

14 Switching Energy! Do we know what this is? Q = I dyn (t)dt I dyn E = P(t)dt = I(t)V dd dt = V dd I(t)dt Penn ESE 570 Spring Khanna 15

15 Switching Energy! Do we know what this is? Q = I dyn (t)dt! What is Q? I dyn E = P(t)dt = I(t)V dd dt = V dd I(t)dt Penn ESE 570 Spring Khanna 16

16 Switching Energy! Do we know what this is? Q = I dyn (t)dt! What is Q? I dyn E = P(t)dt Q = CV = I(t)dt = I(t)V dd dt = V dd I(t)dt Penn ESE 570 Spring Khanna 17

17 Switching Energy! Do we know what this is? Q = I dyn (t)dt! What is Q? I dyn E = P(t)dt Q = CV = I(t)dt = I(t)V dd dt = V dd I(t)dt E = CV dd 2 Capacitor charging energy Penn ESE 570 Spring Khanna 18

18 Switching Power! Every time output switches 0#1 pay: " E = CV 2! P dyn = (# 0#1 trans) CV 2 / time! # 0#1 trans = ½ # of transitions! P dyn = (# trans) ½CV 2 / time Penn ESE 570 Spring Khanna 19

19 Switching Short Circuit Power Penn ESE 570 Spring Khanna 20

20 Short Circuit Power! Between V TN and V dd - V TP " Both N and P devices conducting Penn ESE 570 Spring Khanna 21

21 Short Circuit Power! Between V TN and V dd - V TP " Both N and P devices conducting! Roughly: I sc Vin Vdd-Vthp Vthn time Vdd Vdd Isc Penn ESE 570 Spring Khanna Vout tsc tsc time 22

22 Peak Current! I peak around V dd /2 " If V TN = V TP and sized equal rise/fall I DS ν sat C OX W V GS V T V DSAT ' & 2 ( * ) Vin Vdd-Vthp Vthn time Vdd Vdd Isc Penn ESE 570 Spring Khanna Vout tsc tsc time 23

23 Peak Current! I peak around V dd /2 " If V TN = V TP and sized equal rise/fall I DS ν sat C OX W V GS V T V DSAT ' & 2 I(t)dt I t ' 1( peak sc & 2 * ) ( * ) Vin Vdd-Vthp Vthn time Vdd Vdd Isc Penn ESE 570 Spring Khanna Vout tsc tsc time 24

24 Peak Current! I peak around V dd /2 " If V TN = V TP and sized equal rise/fall I DS ν sat C OX W V GS V T V ( DSAT ' * & 2 ) I(t)dt I t ' 1( peak sc & 2 * ) # E = V dd I peak t sc 1& ( \$ 2' Vin Vdd-Vthp Vthn Vdd Isc Vdd time Penn ESE 570 Spring Khanna Vout tsc tsc time 25

25 Short Circuit Energy! Make it look like a capacitance, C SC " Q=I t " Q=CV " " E = V dd I peak t sc 1 \$ \$ '' # # 2 && E = V dd Q SC E = V dd (C SC V dd ) = C SC V 2 dd Penn ESE 570 Spring Khanna C SC = I peak t sc 2V dd 26

26 Short Circuit Energy! Every time switch (0#1 and 1#0) " Also dissipate short-circuit energy: E = CV 2 " Different C = C sc " C cs fake capacitance (for accounting) Penn ESE 570 Spring Khanna 27

27 Dynamic Characteristics Penn ESE 570 Spring 2018 Khanna 28

28 Inverter Delay! Caused by charging and discharging the capacitive load " What is the load? Penn ESE 570 Spring 2018 Khanna 29

29 Inverter Delay Penn ESE 570 Spring 2018 Khanna 30

30 Inverter Delay Penn ESE 570 Spring 2018 Khanna 31

31 Inverter Delay C gb = C gbn + C gbp C load = C # dbn + C# dbp + C# gdn + C# gdp + C int + C gb Penn ESE 570 Spring 2018 Khanna 32

32 Inverter Delay Usually C db >> C gd C sb >> C gs C load C # dbn + C# dbp + C int + C gb Penn ESE 570 Spring 2018 Khanna 33

33 Inverter Delay n = fan-out 1 C load C dbn + C dbp + C int + nc gb Penn ESE 570 Spring 2018 Khanna 34

34 Propogation Delay Definitions V DD 0 t V DD 0 Penn ESE 570 Spring 2018 Khanna V 50 = V DD /2 35

35 Propogation Delay Definitions t Penn ESE 570 Spring 2018 Khanna 36

36 Propogation Delay Definitions Penn ESE 570 Spring 2018 Khanna 37

37 Rise/Fall Times Penn ESE 570 Spring 2018 Khanna 38

38 MOS Inverter Dynamic Performance! ANALYSIS (OR SIMULATION): For a given MOS inverter schematic and C load, estimate (or measure) the propagation delays! DESIGN: For given specs for the propagation delays and C load*, determine the MOS inverter schematic METHODS: 1. Average Current Model C load ΔV HL I avg,hl = C load V OH V 50 I avg,hl τ PLH C load ΔV LH I avg,lh = C load V 50 V OL I avg,lh Assume V in ideal Penn ESE 570 Spring 2018 Khanna 39

39 MOS Inverter Dynamic Performance! ANALYSIS (OR SIMULATION): For a given MOS inverter schematic and C load, estimate (or measure) the propagation delays! DESIGN: For given specs for the propagation delays and C load*, determine the MOS inverter schematic METHODS: 2. Differential Equation Model i C = C load dv out dt dv dt = C out load i C dt or τ PLH Assume V in ideal Penn ESE 570 Spring 2018 Khanna 40

40 MOS Inverter Dynamic Performance! ANALYSIS (OR SIMULATION): For a given MOS inverter schematic and C load, estimate (or measure) the propagation delays! DESIGN: For given specs for the propagation delays and C load*, determine the MOS inverter schematic METHODS: 3. 1 st Order RC delay Model 0.69 C load R n τ PLH 0.69 C load R p Assume V in ideal Penn ESE 570 Spring 2018 Khanna 41

41 Method 1 Average Current Model Penn ESE 570 Spring 2018 Khanna

42 Calculation of Propagation Delays C load ΔV HL I avg,hl = C load V OH V 50 I avg,hl τ PLH C load ΔV LH I avg,lh = C load V 50 V OL I avg,lh Penn ESE 570 Spring 2018 Khanna 43

43 Calculation of Propagation Delays C load ΔV HL I avg,hl = C load V OH V 50 I avg,hl τ PLH C load ΔV LH I avg,lh = C load V 50 V OL I avg,lh Penn ESE 570 Spring 2018 Khanna 44

44 Calculation of Propagation Delays C load ΔV HL I avg,hl = C load V OH V 50 I avg,hl τ PLH C load ΔV LH I avg,lh = C load V 50 V OL I avg,lh Penn ESE 570 Spring 2018 Khanna 45

45 Calculation of Rise/Fall Times τ fall C load ΔV I avg,90 10 = C load V 90 V 10 I avg,90 10 τ rise C load ΔV I avg,10 90 = C load V 90 V 10 I avg,10 90 Penn ESE 570 Spring 2018 Khanna 46

46 Calculation of Rise/Fall Times τ fall C load ΔV I avg,90 10 = C load V 90 V 10 I avg,90 10 τ rise C load ΔV I avg,10 90 = C load V 90 V 10 I avg,10 90 Penn ESE 570 Spring 2018 Khanna 47

47 Calculation of Rise/Fall Times τ fall C load ΔV I avg,90 10 = C load V 90 V 10 I avg,90 10 τ rise C load ΔV I avg,10 90 = C load V 90 V 10 I avg,10 90 Penn ESE 570 Spring 2018 Khanna 48

48 Method 2 Differential Equation Model Penn ESE 570 Spring 2018 Khanna

49 Calculating Propagation Delays Assume V in is an ideal pulse-input Two Cases 1. V in abruptly rises => V out falls => 2. V in abruptly falls => V out rises => τ PLH i DP - i Dn Penn ESE 570 Spring 2018 Khanna 50

50 Case 1: V in Abruptly Rises - Penn ESE 570 Spring 2018 Khanna 51

51 Case 1: V in Abruptly Rises - Penn ESE 570 Spring 2018 Khanna 52

52 Case 1: V in Abruptly Rises - Penn ESE 570 Spring 2018 Khanna 53

53 Case 1: V in Abruptly Rises - Penn ESE 570 Spring 2018 Khanna 54

54 Case 1: V in Abruptly Rises - V out = V DD V T0n Penn ESE 570 Spring 2018 Khanna 55

55 Case 1: V in Abruptly Rises - C load dv out dt i Dn = =C load dv dt = C out load i Dn t=t 50 V out =V DD /2\$ 1' dt = C t=t load & ) 0 V out =V DD ( i Dn dv out V DD V T 0 n \$ 1' V DD /2 \$ 1' & ) dv V out + C load & DD ) V ( DD V T 0 n ( i Dn Penn ESE 570 Spring 2018 Khanna i Dn dv out V out = V DD V T0n 56

56 Case 1: V in Abruptly Rises - C load dv out dt i Dn = =C load dv dt = C out load i Dn t=t 50 V out =V DD /2\$ 1' dt = C t=t load & ) 0 V out =V DD ( i Dn dv out V DD V T 0 n \$ 1' V DD /2 \$ 1' & ) dv V out + C load & DD ) V ( DD V T 0 n ( i Dn t 0 #t 1 t 1 #t 50 Penn ESE 570 Spring 2018 Khanna i Dn dv out V out = V DD V T0n 57

57 Case 1: V in Abruptly Rises - saturation linear =C load t 0 #t 1 t 1 #t 50 V DD V T 0 n " 1 V DD /2 " 1 \$ ' dv V out + C load \$ DD ' V # & DD V T 0 n # & i Dn i Dn dv out V out = V DD V T0n saturation: i Dn = k n 2 (V in )2,sat = C load,sat = V DD V T 0 n V DD " \$ \$ \$ # C load 1 k n 2 (V DD ) 2 ' ' ' & dv k n 2 (V V V out DD DD T 0n )2 V DD V T 0 n dv out Penn ESE 570 Spring 2018 Khanna,sat = 2C load V T 0n k n (V DD ) 2 58

58 Case 1: V in Abruptly Rises - saturation linear =C load t 0 #t 1 t 1 #t 50 V DD V T 0 n " 1 V DD /2 " 1 \$ ' dv V out + C load \$ DD ' V # & DD V T 0 n # & i Dn i Dn dv out V out = V DD V T0n ( ) linear: i Dn = k n 2 (V V )V V 2 in T 0n out out " V DD /2 \$ 1,lin = C load \$ V DD V T 0 n \$ k n 2 2(V DD )V out V 2 out #,lin = 2C " V load DD /2 1 V k n \$ # 2(V DD )V out V 2 DD V T 0 n out,lin = 2C load k n Penn ESE 570 Spring 2018 Khanna ( ) ( ) 1 2(V DD ) ln " V out \$ # 2(V DD ) V out ( ) ' ' ' & ' & ' & dv out dv out V out =V DD /2 V out =V DD V T 0 n 59

59 Case 1: V in Abruptly Rises -,lin = 2C load k n,lin = 1 2(V DD ) ln # V out \$ 2(V DD ) V out ( ) # C load k n (V DD ) ln 2(V DD ) V DD 2 V DD 2 \$ & ( ' V out =V DD /2 V out =V DD V T 0 n & ( ' Penn ESE 570 Spring 2018 Khanna 60

60 Case 1: V in Abruptly Rises - saturation linear =C load t 0 #t 1 t 1 #t 50 V DD V T 0 n " 1 V DD /2 " 1 \$ ' dv V out + C load \$ DD ' V # & DD V T 0 n # & i Dn i Dn dv out V out = V DD V T0n,sat = 2C load V T 0n k n (V DD ) 2,lin = = 2C load V T 0n k n (V DD ) 2 + " C load k n (V DD ) ln 2(V DD ) V DD 2 \$ V DD 2 " # C load k n (V DD ) ln 2(V DD ) V DD 2 \$ V DD 2 # ' & ' & Penn ESE 570 Spring 2018 Khanna 61

61 Case 1: V in Abruptly Rises - saturation linear =C load t 0 #t 1 t 1 #t 50 V DD V T 0 n " 1 V DD /2 " 1 \$ ' dv V out + C load \$ DD ' V # & DD V T 0 n # & i Dn i Dn dv out V out = V DD V T0n,sat = 2C load V T 0n k n (V DD ) 2,lin = " C load k n (V DD ) ln 2(V DD ) V DD 2 \$ V DD 2 # ' & = Penn ESE 570 Spring 2018 Khanna 2C load V T 0n k n (V DD ) 2 + " C load k n (V DD ) ln 2(V DD ) V DD 2 \$ V DD 2 1 ) 2V =C load T 0n k n (V DD ) (V DD ) + ln # 2(V V ) &, DD T 0n + 1(. * \$ V DD 2 '- # ' & R n 62

62 Case 1: V in Abruptly Rises - 1 ) 2V =C load T 0n k n (V DD ) (V DD ) + ln # 2(V V ) &, DD T 0n + 1(. * \$ V DD 2 '- Recall from static CMOS Inverter: V th = V T 0n + 1 k R 1+ ( V DD +V T 0 p ) 1 k R " k R = V DD +V T 0 p V th \$ # V th ' & 2 DESIGN: (1) V th k R ; (2) k n ; (3) k R & k n k p Penn ESE 570 Spring 2018 Khanna 63

63 Case 1: V in Abruptly Rises - 1 ) 2V =C load T 0n k n (V DD ) (V DD ) + ln # 2(V V ) &, DD T 0n + 1(. * \$ V DD 2 '- Recall from static CMOS Inverter: V th = V T 0n + 1 k R 1+ ( V DD +V T 0 p ) 1 k R " k R = V DD +V T 0 p V th \$ # V th ' & 2 DESIGN: (1) V th k R ; (2) k n ; (3) k R & k n k p (1) V th k R ; (2) τ PLH k p ; (3) k R & k p k n Penn ESE 570 Spring 2018 Khanna 64

64 Differential Model Approximation 1 ) 2V =C load T 0n k n (V DD ) (V DD ) + ln # 2(V V ) &, DD T 0n + 1(. * \$ V DD 2 '- saturation linear =C load t 0 #t 1 t 1 #t 50 V DD V T 0 n " 1 V DD /2 " 1 \$ ' dv V out + C load \$ DD ' V # & DD V T 0 n # & i Dn i Dn dv out Approximate by assuming in saturation: # & V DD /2# 1 & V DD /2 C ( C load V DD \$ i ( dv out = load ( V Dn,sat ' DD k n 2 (V DD ) 2 ( \$ ' C load V DD k n (V DD ) R nc 2 load dv out Penn ESE 570 Spring 2017 Khanna Δ is less than 10 65

65 Differential Model Approximation 1 ) 2V =C load T 0n k n (V DD ) (V DD ) + ln # 2(V V ) &, DD T 0n + 1(. * \$ V DD 2 '- saturation linear Δ is less than 10 Penn ESE 570 Spring 2017 Khanna =C load C load t 0 #t 1 t 1 #t 50 V DD V T 0 n " 1 V DD /2 " 1 \$ ' dv V out + C load \$ DD ' V # & DD V T 0 n # & = V DD /2 V DD V DD /2 V DD i Dn # \$ 1 i Dn,vsat & ( ' dv out # & ( C load * v sat C OX W V DD V ( - dsat +, 2. /( \$ ' dv out C load V DD 2v sat C OX W V DD V R # & n C load dsat ( \$ 2 ' i Dn dv out Approximate by assuming in velocity saturation: V dsat Lv sat µ n 66

66 Example 1:! Consider a CMOS inverter with C load =1pF and V DD =5V. The nmos transistor has V T0n =1V and k n =625uA/V 2.! Assume V in is an ideal step pulse with instant rise/ fall times. Calculate the delay time necessary for the inverter output to fall from its initial value of 5V to 2.5V. 1 ) 2V =C load T 0n k n (V DD ) (V DD ) + ln # 2(V V ) &, DD T 0n + 1(. * \$ V DD 2 '- Penn ESE 570 Spring 2017 Khanna 67

67 Example 1:! Consider a CMOS inverter with C load =1pF and V DD =5V. The nmos transistor has V T0n =1V and k n =625uA/V 2.! Assume V in is an ideal step pulse with instant rise/ fall times. Calculate the delay time necessary for the inverter output to fall from its initial value of 5V to 2.5V. 1 ) 2V = C load T 0n k n (V DD ) (V DD ) + ln # 2(V DD ) &, + 1(. * \$ V DD 2 '- = ) 2 # 2(5 1) &, + ln 1 ( (. )(5 1) *(5 1) \$ 2.5 '- = 0.52ns Penn ESE 570 Spring 2017 Khanna 68

68 Example 1: 1 ) 2V = C load T 0n k n (V DD ) (V DD ) + ln # 2(V DD ) &, + 1(. * \$ V DD 2 '- = ) 2 # 2(5 1) &, + ln 1 ( (. )(5 1) *(5 1) \$ 2.5 '- = 0.52ns Approximate by assuming in saturation: C load V DD k n (V DD ) 2 R n C load Penn ESE 570 Spring 2017 Khanna 69

69 Example 1: 1 ) 2V = C load T 0n k n (V DD ) (V DD ) + ln # 2(V DD ) &, + 1(. * \$ V DD 2 '- = ) 2 # 2(5 1) &, + ln 1 ( (. )(5 1) *(5 1) \$ 2.5 '- = 0.52ns Approximate by assuming in saturation: C load V DD k n (V DD ) 2 R nc load (5) (5 1) 2 = 0.5ns Δ < 3 Penn ESE 570 Spring 2017 Khanna 70

70 Example 2:! Consider a CMOS inverter with C load =1pF and V DD =5V. The nmos transistor has V T0n =1V, k n =20uA/V 2, and W/L=10.! Use the average current method to calculate the fall time. Assume V OH =V DD, and V OL =0V. Usefull equations: τ fall C load ΔV I avg,90 10 = C load V 90 V 10 I avg,90 10 I D,sat = k ' n 2 I D,lin = k ' n 2 W ( L V GS ) 2 W L 2 ( V GS )V DS V 2 DS ( ) Penn ESE 570 Spring 2017 Khanna 71

71 Example 2:! Consider a CMOS inverter with C load =1pF and V DD =5V. The nmos transistor has V T0n =1V, k n =20uA/V 2, and W/L=10.! Use the average current method to calculate the fall time. Assume V OH =V DD, and V OL =0V. I avg, fall = 1 [ 2 i (V = V,V = V )+ i (V = V,V = V ) c in OH out 90 c in OH out 10 ] I avg, fall = 1 [ 2 i (V = 5V,V = 4.5V )+ i (V = 5V,V = 0.5V ) c in out c in out ] I avg, fall = 1 " k ' n 2 # \$ 2 I avg, fall = 1 " \$ 2 # 2 Penn ESE 570 Spring 2017 Khanna W ( L V in ) 2 + k ' n 2 (10)( 5 1) I avg, fall = 0.988mA W L 2 ( V in )V out V 2 out ( ) & ' ( ) (10) 2( 5 1)(0.5) (0.5) 2 ' & 72

72 Example 2:! Consider a CMOS inverter with C load =1pF and V DD =5V. The nmos transistor has V T0n =1V, k n =20uA/V 2, and W/L=10.! Use the average current method to calculate the fall time. Assume V OH =V DD, and V OL =0V. I avg, fall = 1 [ 2 i (V = V,V = V )+ i (V = V,V = V ) c in OH out 90 c in OH out 10 ] I avg, fall = 1 [ 2 i (V = 5V,V = 4.5V )+ i (V = 5V,V = 0.5V ) c in out c in out ] I avg, fall = 1 " k ' n 2 # \$ 2 I avg, fall = 1 " \$ 2 # 2 Penn ESE 570 Spring 2017 Khanna W ( L V in ) 2 + k ' n 2 (10)( 5 1) I avg, fall = 0.988mA W L 2 ( V in )V out V 2 out ( ) & ' ( ) (10) 2( 5 1)(0.5) (0.5) 2 ' & 73

73 Example 2:! Consider a CMOS inverter with C load =1pF and V DD =5V. The nmos transistor has V T0n =1V, k n =20uA/V 2, and W/L=10.! Use the average current method to calculate the fall time. Assume V OH =V DD, and V OL =0V. I avg, fall = 0.988mA τ fall C load ΔV I avg,90 10 = C load V 90 V 10 I avg,90 10 τ fall = 4ns Penn ESE 570 Spring 2017 Khanna 74

74 Example 2:! Consider a CMOS inverter with C load =1pF and V DD =5V. The nmos transistor has V T0n =1V, k n =20uA/V 2, and W/L=10.! Use the differential equation method to calculate the fall time. Assume V OH =V DD, and V OL =0V. Usefull equations: i C = C load dv out dt dv dt = C out load i C i d,sat = 1 2 k ' n i d,lin = 1 2 k ' n W ( L V V GS T 0n) 2 ( ) W L 2(V GS )V DS V 2 DS Penn ESE 570 Spring 2017 Khanna 75

75 Example 2:! Consider a CMOS inverter with C load =1pF and V DD =5V. The nmos transistor has V T0n =1V, k n =20uA/V 2, and W/L=10.! Use the differential equation method to calculate the fall time. Assume V OH =V DD, and V OL =0V. i C = C load dv out dt = 1 2 k ' n W ( L V V in T 0n) 2 dt = k ' n W L 2C load ( )( V DD ) dv 2 out dt = t=t sat t=t 90 V out =4.0 V out =4.5 ( )( 5 1) dv = 2 out dv out dt = dv out = 0.313ns Penn ESE 570 Spring 2017 Khanna 76

76 Example 2:! Consider a CMOS inverter with C load =1pF and V DD =5V. The nmos transistor has V T0n =1V, k n =20uA/V 2, and W/ L=10.! Use the differential equation method to calculate the fall time. Assume V OH =V DD, and V OL =0V. i C = C load dv out dt dt = k ' n t=t 10 = 1 2 k ' n 2C load W L 2(V in )V out V 2 out ( ) ( ) dv out ( W L) 2(V DD )V out V 2 out dt = 2C load k ' n W L t=t sat t=t 10 dt = k ' n t=t sat t=t 10 dt = t=t sat C load ( ) V out =0.5 V out =4 1 ( 2(V DD )V out V 2 out ) dv out ( W L) 1 \$ ln 2(V in ) V 10 ' & ) V in V 10 ( ( 10) \$ 2(5 1) 0.5' ln& ) = 3.39ns 0.5 ( t 90 t sat = 0.313ns 77

77 Example 2:! Consider a CMOS inverter with C load =1pF and V DD =5V. The nmos transistor has V T0n =1V, k n =20uA/V 2, and W/ L=10.! Use the differential equation method to calculate the fall time. Assume V OH =V DD, and V OL =0V. i C = C load dv out dt dt = k ' n t=t 10 = 1 2 k ' n 2C load W L 2(V in )V out V 2 out ( ) ( ) dv out ( W L) 2(V DD )V out V 2 out dt = 2C load k ' n W L t=t sat t=t 10 dt = k ' n t=t sat t=t 10 dt = t=t sat C load ( ) V out =0.5 V out =4 1 ( 2(V DD )V out V 2 out ) dv out ( W L) 1 \$ ln 2(V in ) V 10 ' & ) V in V 10 ( ( 10) \$ 2(5 1) 0.5' ln& ) = 3.39ns 0.5 ( t 90 t sat = 0.313ns t 90 t 10 = 3.7ns Avg method: 4ns 78

78 Case 2: V in Abruptly Falls - τ PLH saturation linear t 0 #t 1 t 1 #t 50 V T 0 p! 1 \$ V 50! 1 τ PLH =C load # 0 " i & dv out + C load V # Dp T 0 p " i Dp \$ & dv out 1 ) 2 V τ PLH =C load T 0 p k p (V DD V T 0 p ) (V DD V T 0 p ) + ln # 2(V DD V T 0 p ) &, + 1(. * + \$ V DD 2 '-. Penn ESE 570 Spring 2017 Khanna 79

79 Case 2: V in Abruptly Falls - τ PLH saturation linear t 0 #t 1 t 1 #t 50 V T 0 p! 1 \$ V 50! 1 τ PLH =C load # 0 " i & dv out + C load V # Dp T 0 p " i Dp \$ & dv out 1 ) 2 V τ PLH =C load T 0 p k p (V DD V T 0 p ) (V DD V T 0 p ) + ln # 2(V DD V T 0 p ) &, + 1(. * + \$ V DD 2 '-. R p τ PLH C load V DD k p (V DD V T 0 p ) 2 R p C load Penn ESE 570 Spring 2017 Khanna 80

80 Differential Equation Model 1 ) 2V =C load T 0n k n (V DD ) (V DD ) + ln # 2(V V ) &, DD T 0n + 1(. * \$ V DD 2 '- 1 ) 2 V τ PLH =C load T 0 p k p (V DD V T 0 p ) (V DD V T 0 p ) + ln # 2(V DD V T 0 p ) &, + 1(. * + \$ V DD 2 '-. CONDITIONS for Balanced CMOS Propagation Delays, i.e. #! # " W L \$ & p = µ! n W # µ p " L \$ & n Penn ESE 570 Spring 2017 Khanna 81

81 Delay Observations 1 ) 2V =C load T 0n k n (V DD ) (V DD ) + ln # 2(V V ) &, DD T 0n + 1(. * \$ V DD 2 '- 1 ) 2 V τ PLH =C load T 0 p k p (V DD V T 0 p ) (V DD V T 0 p ) + ln # 2(V DD V T 0 p ) &, + 1(. * + \$ V DD 2 '-. Penn ESE 570 Spring 2017 Khanna 82

82 Delay Design Equations 1 ) 2V =C load T 0n k n (V DD ) (V DD ) + ln # 2(V V ) &, DD T 0n + 1(. * \$ V DD 2 '- 1 ) 2 V τ PLH =C load T 0 p k p (V DD V T 0 p ) (V DD V T 0 p ) + ln # 2(V DD V T 0 p ) &, + 1(. * + \$ V DD 2 '-. Penn ESE 570 Spring 2017 Khanna 83

83 Delay Design Equations w/ Saturation Approximation C load V DD k n (V DD ) 2! # " W L \$ & n C load V DD µ n C ox (V DD ) 2 τ PLH C load V DD k p (V DD V T 0 p ) 2! # " W L \$ & p C load V DD τ PLH µ p C ox (V DD V T 0 p ) 2 Penn ESE 570 Spring 2017 Khanna 84

84 Design for Delays with More Realistic Model for C load C load i i C dbn + C dbp + C int + C gb i i C load C dbn (W n ) + C dbp (W p ) + C int + C gb Penn ESE 570 Spring 2017 Khanna 85

85 Design for Delays with More Realistic Model for C load C dbn (W n ) = [W n (Y + x j )] C j0n K eqn + (W n + 2Y) C jswn K eqn (sw) C dbp (W p ) = [W p (Y + x j )] C j0p K eqp + (W p + 2Y) C jswp K eqp (sw) 86

86 Design for Delays with More Realistic Model for C load C dbn (W n ) = [W n (Y + x j )] C j0n K eqn + (W n + 2Y) C jswn K eqn (sw) C dbp (W p ) = [W p (Y + x j )] C j0p K eqp + (W p + 2Y) C jswp K eqp (sw) C load = α 0 + α n W n + α p W p α 0 = 2YC jswn K eqn + 2YC jswp K eqp + C int + C gb α n = (Y + x j )C j0n K eqn + C jswn K eqn α p = (Y + x j )C j0p K eqp + C jswp K eqp 87

87 Design for Delays with More Realistic Model for C load 1 ) 2V =C load T 0n k n (V DD ) (V DD ) + ln # 2(V V ) &, DD T 0n + 1(. * \$ V DD 2 '- 1 ) 2 V τ PLH =C load T 0 p k p (V DD V T 0 p ) (V DD V T 0 p ) + ln # 2(V DD V T 0 p ) &, + 1(. * + \$ V DD 2 '-. = Γ n C load W n and = Γ p C load W p Penn ESE 570 Spring 2017 Khanna 88

88 Design for Delays with More Realistic Model for C load 1 ) 2V =C load T 0n k n (V DD ) (V DD ) + ln # 2(V V ) &, DD T 0n + 1(. * \$ V DD 2 '- 1 ) 2 V τ PLH =C load T 0 p k p (V DD V T 0 p ) (V DD V T 0 p ) + ln # 2(V DD V T 0 p ) &, + 1(. * + \$ V DD 2 '-. = Γ n C load W n and = Γ p C load W p Γ n and Γ P are set largely by process parameters and V DD const. Penn ESE 570 Spring 2017 Khanna 89

89 Design for Delays with More Realistic Model for C load = Γ n C load W n = Γ p C load W p C load = α 0 + α n W n + α p W p C load = α 0 + α n W n + (α p W p /W n )W n C load = α 0 + [α n + α p R]W n C load = α 0 + α n W n + α p W p C load = α 0 + (α n W n /W p )W p + α p W p C load = α 0 + [α n /R + α p ]W p where R = W p /W n = constant Penn ESE 570 Spring 2017 Khanna 90

90 Design for Delays with More Realistic Model for C load = Γ n C load W n = Γ p C load W p C load = α 0 + α n W n + α p W p C load = α 0 + α n W n + (α p W p /W n )W n C load = α 0 + [α n + α p R]W n C load = α 0 + α n W n + α p W p C load = α 0 + (α n W n /W p )W p + α p W p C load = α 0 + [α n /R + α p ]W p where R = W p /W n = constant (Recall: V th = 1 = µ pw p when L p =L n ) k R µ n W n = Γ n α 0 + [α n + α p R]W n W n τ PLH = Γ p α 0 + [α n /R + α p ]W p W p Penn ESE 570 Spring 2017 Khanna 91

91 Design for Delays with More Realistic Model for C load = Γ n α 0 + [α n + α p R]W n W n τ PLH = Γ p α 0 + [α n /R + α p ]W p W p where R (constant) = aspect ratio = W p /W n Hence increasing W n and W p will have diminishing influence on and τ PLH as they become large, i.e. τ PLH = limit = Γ n [α n + α p R] W n large = limit τ PLH = Γ p [α n /R + α p ] W p large absolute minimum delays Penn ESE 570 Spring 2017 Khanna 92

92 Design for Delays with More Realistic Model for C load Penn ESE 570 Spring 2017 Khanna 93

93 Design for Delays with More Realistic Model for C load Penn ESE 570 Spring 2017 Khanna 94

94 Taking Into Account Non-Ideal Input Waveform ideal V in non-ideal V in V out to ideal V in V out to non-ideal V in Penn ESE 570 Spring 2017 Khanna 95

95 MOS Inverter Dynamic Performance! ANALYSIS (OR SIMULATION): For a given MOS inverter schematic and C load, estimate (or measure) the propagation delays! DESIGN: For given specs for the propagation delays and C load*, determine the MOS inverter schematic METHODS: 1. Average Current Model C load 2. Differential Equation Model i C = C load dv out dt ΔV HL I avg,hl = C load V OH V 50 I avg,hl dv dt = C out load dt or τ PLH 3. 1 st Order RC delay Model i C Assume V in ideal 0.69 C load R n Penn ESE 570 Spring 2017 Khanna 96

96 Idea! P tot = P static + P dyn + P sc " Can t ignore Static Power (aka. Leakage power)! Propogation Delay " Average Current Model " Differential Equation Model " 1 st Order Model " More next time Penn ESE 570 Spring 2018 Khanna 97

97 Admin! HW 4 due today! HW 5 posted today " Due 3/1! Quiz next week Thursday 2/22 Penn ESE 570 Spring 2018 Khanna 98

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