MODULE 5 Chapter 7. Clocked Storage Elements


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1 MODULE 5 Chapter 7 Clocked Storage Elements 3/9/2015 1
2 Outline Background Clocked Storage Elements Timing, terminology, classification Static CSEs Latches Registers Dynamic CSEs Latches Registers 3/9/2015 2
3 FSM with Positive Edge Triggered Registers 7.1 CSEs/Flipflops provide memory/state VLSI uses predominantly Dtype flipflops 3/9/2015 3
4 Memory elements Store a temporary value, remember a state Separate the past, current, future Typically controlled by clock. May have load signal, etc. In CMOS, memory is created by: capacitance (dynamic); feedback (static). Also see 3/9/2015 4
5 Variations in memory elements Form of required clock signal. How behavior of data input around clock affects the stored value. When the stored value is presented to the output. Whether there is ever a combinational path from input to output. Noise sensitivity on input and output 3/9/2015 5
6 DLatch [Taskin, Kourtev & Friedman, The VLSI Handbook] 3/9/2015 6
7 DRegister (more commonly known as DFlipFlop) [Taskin, Kourtev & Friedman, The VLSI Handbook] 3/9/2015 7
8 Latches vs. Registers Terminology of book Latch Levelsensitive Transparent when clock is active Clock active high: positive latch Clock active low: negative latch Faster, smaller Register Edgetriggered Input and output isolated Sampling on 0 1 clock: positive edge triggered Sampling on 1 0 clock: negative edge triggered Safer 3/9/2015 8
9 Timing Metrics Reminder t cq t su t hold t plogic t cd T : delay from clock (edge) to : setup time : hold time : worst case propagation delay of logic : best case propagation delay (contamination delay) T t cq + t plogic + t su : clock period t cdregister + t cdlogic t hold 3/9/2015 9
10 Static vs. Dynamic Memory Elements Static Operate through positive feedback Preserve state as long as power is on Can work when clock is off More robust Dynamic Store charge on (parasitic) capacitor Charge leaks away (in milliseconds) Clock must be kept running (for periodic refresh) Faster, smaller 3/9/
11 Static CSEs / Flipflops Latches Registers Large part of literature talks about Clocked Storage Elements Are called FlipFlops in book 3/9/
12 Positive Feedback: BiStability V i1 V o1 =V i2 V o2 V o1 V i2 = V o1 Loopgain in A,B <<1 V i1 V o2 A,B: stable points V i2 = V o1 A C Loopgain in C >> 1 C: metastable point B V i1 = V o2 3/9/
13 MetaStability V i2 = V o1 V i2 = V o1 B C δ V i1 = V o2 δ V i1 = V o2 Gain should be larger than 1 in the transition region Smaller than 1 in stable region 3/9/
14 3/9/ SRLatch S R S R S R S R S R > 1 > 1 R S D S R forbidden forbidden S R S R & & Construction of Dlatch Dlatch most common in VLSI 7.2.5
15 Clocked SRLatch S > 1 S R > 1 R S CK R R S & & & & Naïve implementation 16 transistors D latch requires 9xN, 9xP Masterslave Dregister needs 18xN, 18xP Larger area, cost, power 3/9/
16 CMOS Clocked SRLatch VDD CK R S & & & & S M2 M6 M1 M5 M4 M8 M3 M7 R = CK Save 6 PMOS, 2 NMOS transistors Dlatch requires 7 x N, 3 x P (instead of 9xN, 9xP) {TPS}: Is this a ratioed design or not? Does it consume static power? YES NO 3/9/
17 Sizing for Set Action M 3 M 4 form conventional inverter Model M 5 M 6 as one equivalent (double length) transistor M 56 Assume = 0 M 1 is off, M 2 is on M 2 M 56 operate like ratioed pseudo NMOS inverter Latch switches when M 56 pulls input of M 3 M 4 below their switching threshold (assume V DD /2) Positive feedback amplifies switching M 2 and M 56 both in velocity saturation around V = V DD /2 S M2 M6 M1 M5 VDD M4 M8 M3 M7 R k ' n W L 2 2 V ' W V DD Tn DSATn p DD Tp DSATp L 2 2 ( ) DSATn DSATp V V V = k ( V V ) V 3/9/
18 Sizing for Set Action 3/9/
19 SR Latch Timing V DD M2 M4 M6 M1 M8 M3 S M5 M7 R 3/9/
20 MultiplexerBased Latches CLK IN Restoration CLK Multiplexer Muxbased latches much more common in modern dig. IC s 3/9/
21 Recirculating latch uasistatic, static on one phase Feedback restores value Requires 4 x N, 4 x P, minimum size (compare 7 x N, 3 x P, nonminimum size) 1 and 2 inverse but should be nonoverlapping Definitely not ideal, because {TPS} 2 Let s explore TG/PG based latch designs 3/9/
22 Latch Design Pass Transistor Latch Tiny Low clock load V t drop nonrestoring backdriving output noise sensitivity dynamic diffusion input D Used in 1970 s [ Latch Design slides based on Weste & Harris], 3/9/
23 Latch Design Transmission gate No V t drop Requires inverted clock D 3/9/
24 Latch Design Inverting buffer / Basic Dynamic Latch Restoring No backdriving Fixes either Output noise sensitivity Or diffusion input Inverted output 3/9/
25 Dynamic Latch Storage capacitance comes primarily from inverter gate capacitance. Setup and hold times determined by transmission gate must ensure that value stored on transmission gate is solid. Stored charge leaks away Duration of stored value being good depends on technology Worst conditions during burnin (High VDD, high Temp). Modern technologies (almost) mandate static latches. 3/9/
26 Noise Sensitivity Diffusion Input Noise Sensitivity Noise on input can drop node below V T TG NMOS turns on, and X can discharge if it was a 1 Similar problems for V in > V DD 0 Coupling Noise and Supply Noise < V T X Output Noise Sensitivity State node X is exposed Noise spike on output can corrupt the state X 3/9/
27 Latch Design Tristate feedback Static Backdriving risk D X Static latches are now essential because of leakage If only during burnin high VDD, T) = 3/9/
28 Latch Design Buffered input Fixes diffusion input Noninverting D X 3/9/
29 Latch Design Buffered output Widely used in standard cells No backdriving Very robust (most important) D X Rather large Rather slow (1.5 2 FO4 delays) High clock loading 3/9/
30 Latch Design Datapath latch (only use in noisecontrolled environments) Smaller Faster Unbuffered input D X 3/9/
31 Latch Designs can Suffer from Race Problems t loop t D t 1 Signal can race around during = /9/
32 ****Registers Not transparent use multiple storage elements to isolate output from input. Masterslave, edge triggered principle master slave D 3/9/
33 Masterslave operation D master slave = 0: master latch is disabled; slave latch is enabled, but master latch output is stable, so output does not change. = 1: master latch is enabled, loading value from input; slave latch is disabled, maintaining old output value. = 1 0: Slave latch copies current value of master, and master stops changing 3/9/
34 clickable 3/9/
35 Transistor Level Master Slave Positive Edge Triggered Register Robust Design Can eliminate I 1 and I 4, however, they make design more robust (avoid charge sharing, robust input) (see next) High Clock Load (8 x) 3/9/
36 Setup Time Simulation Slightly smaller delay between D and CLK 3/9/
37 Ratioed Reduced Clock Load Register I 2 and I 4 are small, even long Lower clock load Increased design complexity Reduced robustness (reverse conduction / backdriving) 3/9/
38 Simple MasterSlave Register Clock phase overlap is important design problem CK 1 CK 2 CK 1 =1 CK 2 =1 Similar problem for 00 overlap 3/9/
39 Dynamic Edge Triggered Register t su t hold t cq t T1 approximately zero t I1 + t T2 + t I3 t overlap 00 < t T1 + t I1 + t T2 Prevent race through T 1, I 1, T 2 t hold > t overlap 11 Enforce holdtime constraint 3/9/
40 Clocking and CSE problems Clock overlap with multiple phases great problem in view of clock skew Power in some cases, around 50% of total power Delay setup time, clkto,.. Robustness Noisesensitivity of element, specifically for dynamic elements Next: advanced CSEs to combat some of the above 3/9/
41 Other Latches/Registers: C 2 MOS Clocked CMOS Register insensitive to overlap V DD V DD M 2 M 6 D CLK M 4 X CLK M 8 CLK M 3 C L1 CLK M 7 C L2 M 1 M 5 Master Stage Slave Stage Keepers can be added to make circuit pseudostatic 3/9/
42 C 2 MOS Latch Clocked CMOS Latch V DD M 2 CLK M 4 = = CLK M 3 M 1 Slightly Slightly Slower Smaller 3/9/
43 Insensitive to ClockOverlap V DD V DD V DD V DD M 2 M 6 M 2 M 6 D CLK CLK 0 M 4 0 X M 8 D X 1 M 3 1 M 7 M 1 M 5 M 1 M 5 (a) (00) overlap (b) (11) overlap Output always decoupled from input, even with overlap 3/9/
44 Other Latches/Registers: TSPC True Single Phase Clocking V DD V DD V DD V DD X Out In CLK CLK In CLK CLK Out Positive latch (transparent when CLK= 1) Negative latch (transparent when CLK= 0) TSPC register: positive and negative latch in cascade 3/9/
45 Including Logic in TSPC V DD V DD V DD V DD PUN In 1 In 2 In CLK CLK CLK CLK PDN In 1 In 2 Example: logic inside the latch AND latch 3/9/
46 Alternative TSPC Register V DD V DD V DD M 3 CLK M 6 M 9 Y D CLK M 2 X M 5 CLK M 8 M 1 CLK M 4 M 7 Clk = 0 D sampled on X Precharge Y to VDD Y doesn t make Clk Evaluate based on X Clk = 1 Falling X can t charge Y Y is stable Y sampled on 3/9/
47 PulseTriggered Latches An Alternative Approach Remember: Use registers to avoid racearound problem. Two latches in cascade: masterslave Alternative: Pulse triggered latches Data L1 L2 L Data D D D Clk Clk Clk Clk Clk MasterSlave Latches PulseTriggered Latch 3/9/
48 Pulsed Latches V DD V DD M 3 M 6 CLK V DD D CLKG M 2 CLKG M 5 M P X CLKG M 1 M 4 M N (a) register (b) glitch generation CLK CLKG (c) glitch clock 3/9/
49 Pulsed Latches Hybrid Latch Flipflop (HLFF), AMD K6 and K7 : CLK P 1 x P 3 M 3 M 6 D M 2 VDD P 2 M 5 M 1 CLKD M 4 3/9/
50 Hybrid LatchFF Timing D Volts CLK CLKD time (ns) 3/9/
51 More Topics Reset and enable inputs Scanenabled CSEs Senseamplifier based CSEs Doubleedge triggered Lowleakage sleep mode (Ultra) Low voltage Softerror / SEU tolerance Timing of CSEs 3/9/
52 Summary Background Timing, terminology, classification Static CSEs Latches Registers Dynamic CSEs Latches Registers 3/9/
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