MODULE 5 Chapter 7. Clocked Storage Elements

Size: px
Start display at page:

Download "MODULE 5 Chapter 7. Clocked Storage Elements"

Transcription

1 MODULE 5 Chapter 7 Clocked Storage Elements 3/9/2015 1

2 Outline Background Clocked Storage Elements Timing, terminology, classification Static CSEs Latches Registers Dynamic CSEs Latches Registers 3/9/2015 2

3 FSM with Positive Edge Triggered Registers 7.1 CSEs/Flip-flops provide memory/state VLSI uses predominantly D-type flip-flops 3/9/2015 3

4 Memory elements Store a temporary value, remember a state Separate the past, current, future Typically controlled by clock. May have load signal, etc. In CMOS, memory is created by: capacitance (dynamic); feedback (static). Also see 3/9/2015 4

5 Variations in memory elements Form of required clock signal. How behavior of data input around clock affects the stored value. When the stored value is presented to the output. Whether there is ever a combinational path from input to output. Noise sensitivity on input and output 3/9/2015 5

6 D-Latch [Taskin, Kourtev & Friedman, The VLSI Handbook] 3/9/2015 6

7 D-Register (more commonly known as D-Flip-Flop) [Taskin, Kourtev & Friedman, The VLSI Handbook] 3/9/2015 7

8 Latches vs. Registers Terminology of book Latch Level-sensitive Transparent when clock is active Clock active high: positive latch Clock active low: negative latch Faster, smaller Register Edge-triggered Input and output isolated Sampling on 0 1 clock: positive edge triggered Sampling on 1 0 clock: negative edge triggered Safer 3/9/2015 8

9 Timing Metrics Reminder t c-q t su t hold t plogic t cd T : delay from clock (edge) to : setup time : hold time : worst case propagation delay of logic : best case propagation delay (contamination delay) T t c-q + t plogic + t su : clock period t cdregister + t cdlogic t hold 3/9/2015 9

10 Static vs. Dynamic Memory Elements Static Operate through positive feedback Preserve state as long as power is on Can work when clock is off More robust Dynamic Store charge on (parasitic) capacitor Charge leaks away (in milliseconds) Clock must be kept running (for periodic refresh) Faster, smaller 3/9/

11 Static CSEs / Flipflops Latches Registers Large part of literature talks about Clocked Storage Elements Are called Flip-Flops in book 3/9/

12 Positive Feedback: Bi-Stability V i1 V o1 =V i2 V o2 V o1 V i2 = V o1 Loop-gain in A,B <<1 V i1 V o2 A,B: stable points V i2 = V o1 A C Loop-gain in C >> 1 C: meta-stable point B V i1 = V o2 3/9/

13 Meta-Stability V i2 = V o1 V i2 = V o1 B C δ V i1 = V o2 δ V i1 = V o2 Gain should be larger than 1 in the transition region Smaller than 1 in stable region 3/9/

14 3/9/ SR-Latch S R S R S R S R S R > 1 > 1 R S D S R forbidden forbidden S R S R & & Construction of D-latch D-latch most common in VLSI 7.2.5

15 Clocked SR-Latch S > 1 S R > 1 R S CK R R S & & & & Naïve implementation 16 transistors D latch requires 9xN, 9xP Master-slave D-register needs 18xN, 18xP Larger area, cost, power 3/9/

16 CMOS Clocked SR-Latch VDD CK R S & & & & S M2 M6 M1 M5 M4 M8 M3 M7 R = CK Save 6 PMOS, 2 NMOS transistors D-latch requires 7 x N, 3 x P (instead of 9xN, 9xP) {TPS}: Is this a ratioed design or not? Does it consume static power? YES NO 3/9/

17 Sizing for Set Action M 3 -M 4 form conventional inverter Model M 5 -M 6 as one equivalent (double length) transistor M 56 Assume = 0 M 1 is off, M 2 is on M 2 -M 56 operate like ratioed pseudo NMOS inverter Latch switches when M 56 pulls input of M 3 -M 4 below their switching threshold (assume V DD /2) Positive feedback amplifies switching M 2 and M 56 both in velocity saturation around V = V DD /2 S M2 M6 M1 M5 VDD M4 M8 M3 M7 R k ' n W L 2 2 V ' W V DD Tn DSATn p DD Tp DSATp L 2 2 ( ) DSATn DSATp V V V = k ( V V ) V 3/9/

18 Sizing for Set Action 3/9/

19 SR Latch Timing V DD M2 M4 M6 M1 M8 M3 S M5 M7 R 3/9/

20 Multiplexer-Based Latches CLK IN Restoration CLK Multiplexer Mux-based latches much more common in modern dig. IC s 3/9/

21 Recirculating latch uasi-static, static on one phase Feedback restores value Requires 4 x N, 4 x P, minimum size (compare 7 x N, 3 x P, non-minimum size) 1 and 2 inverse but should be non-overlapping Definitely not ideal, because {TPS} 2 Let s explore TG/PG based latch designs 3/9/

22 Latch Design Pass Transistor Latch Tiny Low clock load V t drop nonrestoring backdriving output noise sensitivity dynamic diffusion input D Used in 1970 s [ Latch Design slides based on Weste & Harris], 3/9/

23 Latch Design Transmission gate No V t drop Requires inverted clock D 3/9/

24 Latch Design Inverting buffer / Basic Dynamic Latch Restoring No backdriving Fixes either Output noise sensitivity Or diffusion input Inverted output 3/9/

25 Dynamic Latch Storage capacitance comes primarily from inverter gate capacitance. Setup and hold times determined by transmission gate must ensure that value stored on transmission gate is solid. Stored charge leaks away Duration of stored value being good depends on technology Worst conditions during burn-in (High VDD, high Temp). Modern technologies (almost) mandate static latches. 3/9/

26 Noise Sensitivity Diffusion Input Noise Sensitivity Noise on input can drop node below V T TG NMOS turns on, and X can discharge if it was a 1 Similar problems for V in > V DD 0 Coupling Noise and Supply Noise < -V T X Output Noise Sensitivity State node X is exposed Noise spike on output can corrupt the state X 3/9/

27 Latch Design Tristate feedback Static Backdriving risk D X Static latches are now essential because of leakage If only during burn-in high VDD, T) = 3/9/

28 Latch Design Buffered input Fixes diffusion input Noninverting D X 3/9/

29 Latch Design Buffered output Widely used in standard cells No backdriving Very robust (most important) D X Rather large Rather slow (1.5 2 FO4 delays) High clock loading 3/9/

30 Latch Design Datapath latch (only use in noise-controlled environments) Smaller Faster Unbuffered input D X 3/9/

31 Latch Designs can Suffer from Race Problems t loop t D t 1 Signal can race around during = /9/

32 ****Registers Not transparent use multiple storage elements to isolate output from input. Master-slave, edge triggered principle master slave D 3/9/

33 Master-slave operation D master slave = 0: master latch is disabled; slave latch is enabled, but master latch output is stable, so output does not change. = 1: master latch is enabled, loading value from input; slave latch is disabled, maintaining old output value. = 1 0: Slave latch copies current value of master, and master stops changing 3/9/

34 clickable 3/9/

35 Transistor Level Master Slave Positive Edge Triggered Register Robust Design Can eliminate I 1 and I 4, however, they make design more robust (avoid charge sharing, robust input) (see next) High Clock Load (8 x) 3/9/

36 Set-up Time Simulation Slightly smaller delay between D and CLK 3/9/

37 Ratioed Reduced Clock Load Register I 2 and I 4 are small, even long Lower clock load Increased design complexity Reduced robustness (reverse conduction / backdriving) 3/9/

38 Simple Master-Slave Register Clock phase overlap is important design problem CK 1 CK 2 CK 1 =1 CK 2 =1 Similar problem for 0-0 overlap 3/9/

39 Dynamic Edge Triggered Register t su t hold t cq t T1 approximately zero t I1 + t T2 + t I3 t overlap 0-0 < t T1 + t I1 + t T2 Prevent race through T 1, I 1, T 2 t hold > t overlap 1-1 Enforce hold-time constraint 3/9/

40 Clocking and CSE problems Clock overlap with multiple phases great problem in view of clock skew Power in some cases, around 50% of total power Delay setup time, clk-to-,.. Robustness Noise-sensitivity of element, specifically for dynamic elements Next: advanced CSEs to combat some of the above 3/9/

41 Other Latches/Registers: C 2 MOS Clocked CMOS Register insensitive to overlap V DD V DD M 2 M 6 D CLK M 4 X CLK M 8 CLK M 3 C L1 CLK M 7 C L2 M 1 M 5 Master Stage Slave Stage Keepers can be added to make circuit pseudo-static 3/9/

42 C 2 MOS Latch Clocked CMOS Latch V DD M 2 CLK M 4 = = CLK M 3 M 1 Slightly Slightly Slower Smaller 3/9/

43 Insensitive to Clock-Overlap V DD V DD V DD V DD M 2 M 6 M 2 M 6 D CLK CLK 0 M 4 0 X M 8 D X 1 M 3 1 M 7 M 1 M 5 M 1 M 5 (a) (0-0) overlap (b) (1-1) overlap Output always decoupled from input, even with overlap 3/9/

44 Other Latches/Registers: TSPC True Single Phase Clocking V DD V DD V DD V DD X Out In CLK CLK In CLK CLK Out Positive latch (transparent when CLK= 1) Negative latch (transparent when CLK= 0) TSPC register: positive and negative latch in cascade 3/9/

45 Including Logic in TSPC V DD V DD V DD V DD PUN In 1 In 2 In CLK CLK CLK CLK PDN In 1 In 2 Example: logic inside the latch AND latch 3/9/

46 Alternative TSPC Register V DD V DD V DD M 3 CLK M 6 M 9 Y D CLK M 2 X M 5 CLK M 8 M 1 CLK M 4 M 7 Clk = 0 D sampled on X Precharge Y to VDD Y doesn t make Clk Evaluate based on X Clk = 1 Falling X can t charge Y Y is stable Y sampled on 3/9/

47 Pulse-Triggered Latches An Alternative Approach Remember: Use registers to avoid race-around problem. Two latches in cascade: master-slave Alternative: Pulse triggered latches Data L1 L2 L Data D D D Clk Clk Clk Clk Clk Master-Slave Latches Pulse-Triggered Latch 3/9/

48 Pulsed Latches V DD V DD M 3 M 6 CLK V DD D CLKG M 2 CLKG M 5 M P X CLKG M 1 M 4 M N (a) register (b) glitch generation CLK CLKG (c) glitch clock 3/9/

49 Pulsed Latches Hybrid Latch Flip-flop (HLFF), AMD K-6 and K-7 : CLK P 1 x P 3 M 3 M 6 D M 2 VDD P 2 M 5 M 1 CLKD M 4 3/9/

50 Hybrid Latch-FF Timing D Volts CLK CLKD time (ns) 3/9/

51 More Topics Reset and enable inputs Scan-enabled CSEs Sense-amplifier based CSEs Double-edge triggered Low-leakage sleep mode (Ultra) Low voltage Soft-error / SEU tolerance Timing of CSEs 3/9/

52 Summary Background Timing, terminology, classification Static CSEs Latches Registers Dynamic CSEs Latches Registers 3/9/

Lecture 9: Sequential Logic Circuits. Reading: CH 7

Lecture 9: Sequential Logic Circuits. Reading: CH 7 Lecture 9: Sequential Logic Circuits Reading: CH 7 Sequential Logic FSM (Finite-state machine) Inputs Current State COMBINATIONAL LOGIC Registers Outputs = f(current, inputs) Next state 2 storage mechanisms

More information

Digital Integrated Circuits A Design Perspective

Digital Integrated Circuits A Design Perspective Digital Integrated Circuits A Design Perspective Jan M. Rabaey Anantha Chandrakasan Borivoje Nikolic Designing Sequential Logic Circuits November 2002 Sequential Logic Inputs Current State COMBINATIONAL

More information

GMU, ECE 680 Physical VLSI Design

GMU, ECE 680 Physical VLSI Design ECE680: Physical VLSI esign Chapter IV esigning Sequential Logic Circuits (Chapter 7) 1 Sequential Logic Inputs Current State COMBINATIONAL LOGIC Registers Outputs Next state 2 storage mechanisms positive

More information

9/18/2008 GMU, ECE 680 Physical VLSI Design

9/18/2008 GMU, ECE 680 Physical VLSI Design ECE680: Physical VLSI esign Chapter IV esigning Sequential Logic Circuits (Chapter 7) 1 Sequential Logic Inputs Current State COMBINATIONAL LOGIC Registers Outputs Next state 2 storage mechanisms positive

More information

Digital Integrated Circuits A Design Perspective

Digital Integrated Circuits A Design Perspective igital Integrated Circuits A esign Perspective Jan M. Rabaey Anantha Chandrakasan Borivoje Nikolic esigning Sequential Logic Circuits November 2002 Naming Conventions In our text: a latch is level sensitive

More information

Digital Integrated Circuits A Design Perspective

Digital Integrated Circuits A Design Perspective igital Integrated Circuits A esign Perspective Jan M. Rabaey Anantha Chandrakasan Borivoje Nikolic esigning Sequential Logic Circuits November 2002 Sequential Logic Inputs Current State COMBINATIONAL LOGIC

More information

Jan M. Rabaey Anantha Chandrakasan Borivoje Nikolic. November Digital Integrated Circuits 2nd Sequential Circuits

Jan M. Rabaey Anantha Chandrakasan Borivoje Nikolic. November Digital Integrated Circuits 2nd Sequential Circuits igital Integrated Circuits A esign Perspective Jan M. Rabaey Anantha Chandrakasan Borivoje Nikolic esigning i Sequential Logic Circuits November 2002 Sequential Logic Inputs Current State COMBINATIONAL

More information

Topics. Dynamic CMOS Sequential Design Memory and Control. John A. Chandy Dept. of Electrical and Computer Engineering University of Connecticut

Topics. Dynamic CMOS Sequential Design Memory and Control. John A. Chandy Dept. of Electrical and Computer Engineering University of Connecticut Topics Dynamic CMOS Sequential Design Memory and Control Dynamic CMOS In static circuits at every point in time (except when switching) the output is connected to either GND or V DD via a low resistance

More information

CMPEN 411. Spring Lecture 18: Static Sequential Circuits

CMPEN 411. Spring Lecture 18: Static Sequential Circuits CMPEN 411 VLSI Digital Circuits Spring 2011 Lecture 18: Static Sequential Circuits [Adapted from Rabaey s Digital Integrated Circuits, Second Edition, 2003 J. Rabaey, A. Chandrakasan, B. Nikolic] Sp11

More information

ESE 570: Digital Integrated Circuits and VLSI Fundamentals

ESE 570: Digital Integrated Circuits and VLSI Fundamentals ESE 570: Digital Integrated Circuits and VLSI Fundamentals Lec 18: March 27, 2018 Dynamic Logic, Charge Injection Lecture Outline! Sequential MOS Logic " D-Latch " Timing Constraints! Dynamic Logic " Domino

More information

Integrated Circuits & Systems

Integrated Circuits & Systems Federal University of Santa Catarina Center for Technology Computer Science & Electronics Engineering Integrated Circuits & Systems INE 5442 Lecture 18 CMOS Sequential Circuits - 1 guntzel@inf.ufsc.br

More information

EE141Microelettronica. CMOS Logic

EE141Microelettronica. CMOS Logic Microelettronica CMOS Logic CMOS logic Power consumption in CMOS logic gates Where Does Power Go in CMOS? Dynamic Power Consumption Charging and Discharging Capacitors Short Circuit Currents Short Circuit

More information

ΗΜΥ 307 ΨΗΦΙΑΚΑ ΟΛΟΚΛΗΡΩΜΕΝΑ ΚΥΚΛΩΜΑΤΑ Εαρινό Εξάμηνο 2018

ΗΜΥ 307 ΨΗΦΙΑΚΑ ΟΛΟΚΛΗΡΩΜΕΝΑ ΚΥΚΛΩΜΑΤΑ Εαρινό Εξάμηνο 2018 ΗΜΥ 307 ΨΗΦΙΑΚΑ ΟΛΟΚΛΗΡΩΜΕΝΑ ΚΥΚΛΩΜΑΤΑ Εαρινό Εξάμηνο 2018 ΔΙΑΛΕΞΕΙΣ 12-13: esigning ynamic and Static CMOS Sequential Circuits ΧΑΡΗΣ ΘΕΟΧΑΡΙΔΗΣ (ttheocharides@ucy.ac.cy) (ack: Prof. Mary Jane Irwin and

More information

CMPEN 411 VLSI Digital Circuits Spring 2012 Lecture 17: Dynamic Sequential Circuits And Timing Issues

CMPEN 411 VLSI Digital Circuits Spring 2012 Lecture 17: Dynamic Sequential Circuits And Timing Issues CMPEN 411 VLSI Digital Circuits Spring 2012 Lecture 17: Dynamic Sequential Circuits And Timing Issues [Adapted from Rabaey s Digital Integrated Circuits, Second Edition, 2003 J. Rabaey, A. Chandrakasan,

More information

EE141- Spring 2007 Digital Integrated Circuits

EE141- Spring 2007 Digital Integrated Circuits EE141- Spring 27 igital Integrated Circuits Lecture 19 Sequential Circuits 1 Administrative Stuff Project Ph. 2 due Tu. 5pm 24 Cory box + email ee141- project@bwrc.eecs.berkeley.edu Hw 8 Posts this Fr.,

More information

Hold Time Illustrations

Hold Time Illustrations Hold Time Illustrations EE213-L09-Sequential Logic.1 Pingqiang, ShanghaiTech, 2018 Hold Time Illustrations EE213-L09-Sequential Logic.2 Pingqiang, ShanghaiTech, 2018 Hold Time Illustrations EE213-L09-Sequential

More information

Clock Strategy. VLSI System Design NCKUEE-KJLEE

Clock Strategy. VLSI System Design NCKUEE-KJLEE Clock Strategy Clocked Systems Latch and Flip-flops System timing Clock skew High speed latch design Phase locked loop ynamic logic Multiple phase Clock distribution Clocked Systems Most VLSI systems are

More information

Topics. CMOS Design Multi-input delay analysis. John A. Chandy Dept. of Electrical and Computer Engineering University of Connecticut

Topics. CMOS Design Multi-input delay analysis. John A. Chandy Dept. of Electrical and Computer Engineering University of Connecticut Topics CMO Design Multi-input delay analysis pring 25 Transmission Gate OUT Z OUT Z pring 25 Transmission Gate OUT When is low, the output is at high impedance When is high, the output follows However,

More information

Digital Integrated Circuits A Design Perspective

Digital Integrated Circuits A Design Perspective Digital Integrated Circuits Design Perspective Designing Combinational Logic Circuits Fuyuzhuo School of Microelectronics,SJTU Introduction Digital IC Dynamic Logic Introduction Digital IC 2 EE141 Dynamic

More information

EECS 427 Lecture 15: Timing, Latches, and Registers Reading: Chapter 7. EECS 427 F09 Lecture Reminders

EECS 427 Lecture 15: Timing, Latches, and Registers Reading: Chapter 7. EECS 427 F09 Lecture Reminders EECS 427 Lecture 15: Timing, Latches, and Registers Reading: Chapter 7 1 Reminders CA assignments CA7 is due Thursday at noon ECE Graduate Symposium Poster session in ECE Atrium on Friday HW4 (detailed

More information

Digital Integrated Circuits Designing Combinational Logic Circuits. Fuyuzhuo

Digital Integrated Circuits Designing Combinational Logic Circuits. Fuyuzhuo Digital Integrated Circuits Designing Combinational Logic Circuits Fuyuzhuo Introduction Digital IC Dynamic Logic Introduction Digital IC EE141 2 Dynamic logic outline Dynamic logic principle Dynamic logic

More information

Designing Sequential Logic Circuits

Designing Sequential Logic Circuits igital Integrated Circuits (83-313) Lecture 5: esigning Sequential Logic Circuits Semester B, 2016-17 Lecturer: r. Adam Teman TAs: Itamar Levi, Robert Giterman 26 April 2017 isclaimer: This course was

More information

! Charge Leakage/Charge Sharing. " Domino Logic Design Considerations. ! Logic Comparisons. ! Memory. " Classification. " ROM Memories.

! Charge Leakage/Charge Sharing.  Domino Logic Design Considerations. ! Logic Comparisons. ! Memory.  Classification.  ROM Memories. ESE 57: Digital Integrated Circuits and VLSI Fundamentals Lec 9: March 9, 8 Memory Overview, Memory Core Cells Today! Charge Leakage/ " Domino Logic Design Considerations! Logic Comparisons! Memory " Classification

More information

Sequential vs. Combinational

Sequential vs. Combinational Sequential Circuits Sequential vs. Combinational Combinational Logic: Output depends only on current input TV channel selector (-9) inputs system outputs Sequential Logic: Output depends not only on current

More information

ESE 570: Digital Integrated Circuits and VLSI Fundamentals

ESE 570: Digital Integrated Circuits and VLSI Fundamentals ESE 570: Digital Integrated Circuits and VLSI Fundamentals Lec 19: March 29, 2018 Memory Overview, Memory Core Cells Today! Charge Leakage/Charge Sharing " Domino Logic Design Considerations! Logic Comparisons!

More information

Skew-Tolerant Circuit Design

Skew-Tolerant Circuit Design Skew-Tolerant Circuit Design David Harris David_Harris@hmc.edu December, 2000 Harvey Mudd College Claremont, CA Outline Introduction Skew-Tolerant Circuits Traditional Domino Circuits Skew-Tolerant Domino

More information

Y. Tsiatouhas. VLSI Systems and Computer Architecture Lab

Y. Tsiatouhas. VLSI Systems and Computer Architecture Lab CMOS INTEGRATE CIRCUIT ESIGN TECHNIUES University of Ioannina Memory Elements and other Circuits ept. of Computer Science and Engineering Y. Tsiatouhas CMOS Integrated Circuit esign Techniques Overview.

More information

Dynamic Combinational Circuits. Dynamic Logic

Dynamic Combinational Circuits. Dynamic Logic Dynamic Combinational Circuits Dynamic circuits Charge sharing, charge redistribution Domino logic np-cmos (zipper CMOS) Krish Chakrabarty 1 Dynamic Logic Dynamic gates use a clocked pmos pullup Two modes:

More information

Lecture 16: Circuit Pitfalls

Lecture 16: Circuit Pitfalls Introduction to CMOS VLSI Design Lecture 16: Circuit Pitfalls David Harris Harvey Mudd College Spring 2004 Outline Pitfalls Detective puzzle Given circuit and symptom, diagnose cause and recommend solution

More information

Lecture 4: Implementing Logic in CMOS

Lecture 4: Implementing Logic in CMOS Lecture 4: Implementing Logic in CMOS Mark Mcermott Electrical and Computer Engineering The University of Texas at ustin Review of emorgan s Theorem Recall that: () = + and = ( + ) (+) = and + = ( ) ()

More information

9/18/2008 GMU, ECE 680 Physical VLSI Design

9/18/2008 GMU, ECE 680 Physical VLSI Design ECE680: Physical VLSI Design Chapter III CMOS Device, Inverter, Combinational circuit Logic and Layout Part 3 Combinational Logic Gates (textbook chapter 6) 9/18/2008 GMU, ECE 680 Physical VLSI Design

More information

Clock signal in digital circuit is responsible for synchronizing the transfer to the data between processing elements.

Clock signal in digital circuit is responsible for synchronizing the transfer to the data between processing elements. 1 2 Introduction Clock signal in digital circuit is responsible for synchronizing the transfer to the data between processing elements. Defines the precise instants when the circuit is allowed to change

More information

COMP 103. Lecture 16. Dynamic Logic

COMP 103. Lecture 16. Dynamic Logic COMP 03 Lecture 6 Dynamic Logic Reading: 6.3, 6.4 [ll lecture notes are adapted from Mary Jane Irwin, Penn State, which were adapted from Rabaey s Digital Integrated Circuits, 2002, J. Rabaey et al.] COMP03

More information

Lecture 14: Circuit Families

Lecture 14: Circuit Families Introduction to CMOS VLSI Design Lecture 4: Circuit Families David Harris, Harvey Mudd College Kartik Mohanram and Steven Levitan University of Pittsburgh Outline q Pseudo-nMOS Logic q Dynamic Logic q

More information

ESE 570: Digital Integrated Circuits and VLSI Fundamentals

ESE 570: Digital Integrated Circuits and VLSI Fundamentals ESE 570: Digital Integrated Circuits and VLSI Fundamentals Lec 17: March 23, 2017 Energy and Power Optimization, Design Space Exploration, Synchronous MOS Logic Lecture Outline! Energy and Power Optimization

More information

EECS 141 F01 Lecture 17

EECS 141 F01 Lecture 17 EECS 4 F0 Lecture 7 With major inputs/improvements From Mary-Jane Irwin (Penn State) Dynamic CMOS In static circuits at every point in time (except when switching) the output is connected to either GND

More information

Chapter 5 CMOS Logic Gate Design

Chapter 5 CMOS Logic Gate Design Chapter 5 CMOS Logic Gate Design Section 5. -To achieve correct operation of integrated logic gates, we need to satisfy 1. Functional specification. Temporal (timing) constraint. (1) In CMOS, incorrect

More information

L4: Sequential Building Blocks (Flip-flops, Latches and Registers)

L4: Sequential Building Blocks (Flip-flops, Latches and Registers) L4: Sequential Building Blocks (Flip-flops, Latches and Registers) Acknowledgements: Lecture material adapted from R. Katz, G. Borriello, Contemporary Logic esign (second edition), Prentice-Hall/Pearson

More information

L4: Sequential Building Blocks (Flip-flops, Latches and Registers)

L4: Sequential Building Blocks (Flip-flops, Latches and Registers) L4: Sequential Building Blocks (Flip-flops, Latches and Registers) Acknowledgements:., Materials in this lecture are courtesy of the following people and used with permission. - Randy H. Katz (University

More information

5. Sequential Logic x Computation Structures Part 1 Digital Circuits. Copyright 2015 MIT EECS

5. Sequential Logic x Computation Structures Part 1 Digital Circuits. Copyright 2015 MIT EECS 5. Sequential Logic 6.004x Computation Structures Part 1 igital Circuits Copyright 2015 MIT EECS 6.004 Computation Structures L5: Sequential Logic, Slide #1 Something We Can t Build (Yet) What if you were

More information

ESE 570: Digital Integrated Circuits and VLSI Fundamentals

ESE 570: Digital Integrated Circuits and VLSI Fundamentals ESE 570: Digital Integrated Circuits and VLSI Fundamentals Lec 21: April 4, 2017 Memory Overview, Memory Core Cells Penn ESE 570 Spring 2017 Khanna Today! Memory " Classification " ROM Memories " RAM Memory

More information

UNIVERSITY OF CALIFORNIA, BERKELEY College of Engineering Department of Electrical Engineering and Computer Sciences

UNIVERSITY OF CALIFORNIA, BERKELEY College of Engineering Department of Electrical Engineering and Computer Sciences UNIVERSITY OF CALIFORNIA, BERKELEY College of Engineering Department of Electrical Engineering and Computer Sciences Elad Alon Homework #9 EECS141 PROBLEM 1: TIMING Consider the simple state machine shown

More information

Power Dissipation. Where Does Power Go in CMOS?

Power Dissipation. Where Does Power Go in CMOS? Power Dissipation [Adapted from Chapter 5 of Digital Integrated Circuits, 2003, J. Rabaey et al.] Where Does Power Go in CMOS? Dynamic Power Consumption Charging and Discharging Capacitors Short Circuit

More information

Lecture 1: Circuits & Layout

Lecture 1: Circuits & Layout Lecture 1: Circuits & Layout Outline q A Brief History q CMOS Gate esign q Pass Transistors q CMOS Latches & Flip-Flops q Standard Cell Layouts q Stick iagrams 2 A Brief History q 1958: First integrated

More information

Dynamic Combinational Circuits. Dynamic Logic

Dynamic Combinational Circuits. Dynamic Logic Dynamic Combinational Circuits Dynamic circuits Charge sharing, charge redistribution Domino logic np-cmos (zipper CMOS) Krish Chakrabarty 1 Dynamic Logic Dynamic gates use a clocked pmos pullup Two modes:

More information

Properties of CMOS Gates Snapshot

Properties of CMOS Gates Snapshot MOS logic 1 Properties of MOS Gates Snapshot High noise margins: V OH and V OL are at V DD and GND, respectively. No static power consumption: There never exists a direct path between V DD and V SS (GND)

More information

Memory, Latches, & Registers

Memory, Latches, & Registers Memory, Latches, & Registers 1) Structured Logic Arrays 2) Memory Arrays 3) Transparent Latches 4) How to save a few bucks at toll booths 5) Edge-triggered Registers L13 Memory 1 General Table Lookup Synthesis

More information

ESE570 Spring University of Pennsylvania Department of Electrical and System Engineering Digital Integrated Cicruits AND VLSI Fundamentals

ESE570 Spring University of Pennsylvania Department of Electrical and System Engineering Digital Integrated Cicruits AND VLSI Fundamentals University of Pennsylvania Department of Electrical and System Engineering Digital Integrated Cicruits AND VLSI Fundamentals ESE570, Spring 017 Final Wednesday, May 3 4 Problems with point weightings shown.

More information

CMPEN 411 VLSI Digital Circuits. Lecture 04: CMOS Inverter (static view)

CMPEN 411 VLSI Digital Circuits. Lecture 04: CMOS Inverter (static view) CMPEN 411 VLSI Digital Circuits Lecture 04: CMOS Inverter (static view) Kyusun Choi [Adapted from Rabaey s Digital Integrated Circuits, Second Edition, 2003 J. Rabaey, A. Chandrakasan, B. Nikolic] CMPEN

More information

Name: Answers. Mean: 83, Standard Deviation: 12 Q1 Q2 Q3 Q4 Q5 Q6 Total. ESE370 Fall 2015

Name: Answers. Mean: 83, Standard Deviation: 12 Q1 Q2 Q3 Q4 Q5 Q6 Total. ESE370 Fall 2015 University of Pennsylvania Department of Electrical and System Engineering Circuit-Level Modeling, Design, and Optimization for Digital Systems ESE370, Fall 2015 Final Tuesday, December 15 Problem weightings

More information

F14 Memory Circuits. Lars Ohlsson

F14 Memory Circuits. Lars Ohlsson Lars Ohlsson 2018-10-18 F14 Memory Circuits Outline Combinatorial vs. sequential logic circuits Analogue multivibrator circuits Noise in digital circuits CMOS latch CMOS SR flip flop 6T SRAM cell 1T DRAM

More information

ELCT201: DIGITAL LOGIC DESIGN

ELCT201: DIGITAL LOGIC DESIGN ELCT201: DIGITAL LOGIC DESIGN Dr. Eng. Haitham Omran, haitham.omran@guc.edu.eg Dr. Eng. Wassim Alexan, wassim.joseph@guc.edu.eg Lecture 6 Following the slides of Dr. Ahmed H. Madian محرم 1439 ه Winter

More information

Miscellaneous Lecture topics. Mary Jane Irwin [Adapted from Rabaey s Digital Integrated Circuits, 2002, J. Rabaey et al.]

Miscellaneous Lecture topics. Mary Jane Irwin [Adapted from Rabaey s Digital Integrated Circuits, 2002, J. Rabaey et al.] Miscellaneous Lecture topics Mary Jane Irwin [dapted from Rabaey s Digital Integrated Circuits, 2002, J. Rabaey et al.] MOS Switches MOS transistors can be viewed as simple switches. In an N-Switch, the

More information

ΗΜΥ 307 ΨΗΦΙΑΚΑ ΟΛΟΚΛΗΡΩΜΕΝΑ ΚΥΚΛΩΜΑΤΑ Εαρινό Εξάμηνο 2018

ΗΜΥ 307 ΨΗΦΙΑΚΑ ΟΛΟΚΛΗΡΩΜΕΝΑ ΚΥΚΛΩΜΑΤΑ Εαρινό Εξάμηνο 2018 ΗΜΥ 307 ΨΗΦΙΑΚΑ ΟΛΟΚΛΗΡΩΜΕΝΑ ΚΥΚΛΩΜΑΤΑ Εαρινό Εξάμηνο 2018 ΔΙΑΛΕΞΗ 11: Dynamic CMOS Circuits ΧΑΡΗΣ ΘΕΟΧΑΡΙΔΗΣ (ttheocharides@ucy.ac.cy) (ack: Prof. Mary Jane Irwin and Vijay Narayanan) [Προσαρμογή από

More information

CMPEN 411 VLSI Digital Circuits Spring 2011 Lecture 07: Pass Transistor Logic

CMPEN 411 VLSI Digital Circuits Spring 2011 Lecture 07: Pass Transistor Logic CMPEN 411 VLSI Digital Circuits Spring 2011 Lecture 07: Pass Transistor Logic [dapted from Rabaey s Digital Integrated Circuits, Second Edition, 2003 J. Rabaey,. Chandrakasan,. Nikolic] Sp11 CMPEN 411

More information

Digital Integrated Circuits A Design Perspective

Digital Integrated Circuits A Design Perspective Designing ombinational Logic ircuits dapted from hapter 6 of Digital Integrated ircuits Design Perspective Jan M. Rabaey et al. opyright 2003 Prentice Hall/Pearson 1 ombinational vs. Sequential Logic In

More information

EEC 118 Lecture #6: CMOS Logic. Rajeevan Amirtharajah University of California, Davis Jeff Parkhurst Intel Corporation

EEC 118 Lecture #6: CMOS Logic. Rajeevan Amirtharajah University of California, Davis Jeff Parkhurst Intel Corporation EEC 118 Lecture #6: CMOS Logic Rajeevan mirtharajah University of California, Davis Jeff Parkhurst Intel Corporation nnouncements Quiz 1 today! Lab 2 reports due this week Lab 3 this week HW 3 due this

More information

Lecture 27: Latches. Final presentations May 8, 1-5pm, BWRC Final reports due May 7 Final exam, Monday, May :30pm, 241 Cory

Lecture 27: Latches. Final presentations May 8, 1-5pm, BWRC Final reports due May 7 Final exam, Monday, May :30pm, 241 Cory EE241 - Spring 2008 Advanced Digital Integrated Circuits Lecture 27: Latches Timing Announcements Wrapping-up the class: Final presentations May 8, 1-5pm, BWRC Final reports due May 7 Final exam, Monday,

More information

COMBINATIONAL LOGIC. Combinational Logic

COMBINATIONAL LOGIC. Combinational Logic COMINTIONL LOGIC Overview Static CMOS Conventional Static CMOS Logic Ratioed Logic Pass Transistor/Transmission Gate Logic Dynamic CMOS Logic Domino np-cmos Combinational vs. Sequential Logic In Logic

More information

CPE/EE 427, CPE 527 VLSI Design I Pass Transistor Logic. Review: CMOS Circuit Styles

CPE/EE 427, CPE 527 VLSI Design I Pass Transistor Logic. Review: CMOS Circuit Styles PE/EE 427, PE 527 VLI Design I Pass Transistor Logic Department of Electrical and omputer Engineering University of labama in Huntsville leksandar Milenkovic ( www.ece.uah.edu/~milenka ) Review: MO ircuit

More information

Chapter 13. Clocked Circuits SEQUENTIAL VS. COMBINATIONAL CMOS TG LATCHES, FLIP FLOPS. Baker Ch. 13 Clocked Circuits. Introduction to VLSI

Chapter 13. Clocked Circuits SEQUENTIAL VS. COMBINATIONAL CMOS TG LATCHES, FLIP FLOPS. Baker Ch. 13 Clocked Circuits. Introduction to VLSI Chapter 13 Clocked Circuits SEQUENTIAL VS. COMBINATIONAL CMOS TG LATCHES, FLIP FLOPS SET-RESET (SR) ARBITER LATCHES FLIP FLOPS EDGE TRIGGERED DFF FF TIMING Joseph A. Elias, Ph.D. Adjunct Professor, University

More information

Topic 4. The CMOS Inverter

Topic 4. The CMOS Inverter Topic 4 The CMOS Inverter Peter Cheung Department of Electrical & Electronic Engineering Imperial College London URL: www.ee.ic.ac.uk/pcheung/ E-mail: p.cheung@ic.ac.uk Topic 4-1 Noise in Digital Integrated

More information

Semiconductor memories

Semiconductor memories Semiconductor memories Semiconductor Memories Data in Write Memory cell Read Data out Some design issues : How many cells? Function? Power consuption? Access type? How fast are read/write operations? Semiconductor

More information

CPE/EE 427, CPE 527 VLSI Design I L18: Circuit Families. Outline

CPE/EE 427, CPE 527 VLSI Design I L18: Circuit Families. Outline CPE/EE 47, CPE 57 VLI Design I L8: Circuit Families Department of Electrical and Computer Engineering University of labama in Huntsville leksandar Milenkovic ( www.ece.uah.edu/~milenka ) www.ece.uah.edu/~milenka/cpe57-05f

More information

Chapter 7. Sequential Circuits Registers, Counters, RAM

Chapter 7. Sequential Circuits Registers, Counters, RAM Chapter 7. Sequential Circuits Registers, Counters, RAM Register - a group of binary storage elements suitable for holding binary info A group of FFs constitutes a register Commonly used as temporary storage

More information

Jin-Fu Li Advanced Reliable Systems (ARES) Lab. Department of Electrical Engineering. Jungli, Taiwan

Jin-Fu Li Advanced Reliable Systems (ARES) Lab. Department of Electrical Engineering. Jungli, Taiwan Chapter 7 Sequential Circuits Jin-Fu Li Advanced Reliable Systems (ARES) Lab. epartment of Electrical Engineering National Central University it Jungli, Taiwan Outline Latches & Registers Sequencing Timing

More information

CMOS Digital Integrated Circuits Lec 13 Semiconductor Memories

CMOS Digital Integrated Circuits Lec 13 Semiconductor Memories Lec 13 Semiconductor Memories 1 Semiconductor Memory Types Semiconductor Memories Read/Write (R/W) Memory or Random Access Memory (RAM) Read-Only Memory (ROM) Dynamic RAM (DRAM) Static RAM (SRAM) 1. Mask

More information

Lecture 6: Circuit design part 1

Lecture 6: Circuit design part 1 Lecture 6: Circuit design part 6. Combinational circuit design 6. Sequential circuit design 6.3 Circuit simulation 6.4. Hardware description language Combinational Circuit Design. Combinational circuit

More information

MOSIS REPORT. Spring MOSIS Report 1. MOSIS Report 2. MOSIS Report 3

MOSIS REPORT. Spring MOSIS Report 1. MOSIS Report 2. MOSIS Report 3 MOSIS REPORT Spring 2010 MOSIS Report 1 MOSIS Report 2 MOSIS Report 3 MOSIS Report 1 Design of 4-bit counter using J-K flip flop I. Objective The purpose of this project is to design one 4-bit counter

More information

CPE/EE 427, CPE 527 VLSI Design I Delay Estimation. Department of Electrical and Computer Engineering University of Alabama in Huntsville

CPE/EE 427, CPE 527 VLSI Design I Delay Estimation. Department of Electrical and Computer Engineering University of Alabama in Huntsville CPE/EE 47, CPE 57 VLSI Design I Delay Estimation Department of Electrical and Computer Engineering University of labama in Huntsville leksandar Milenkovic ( www.ece.uah.edu/~milenka ) Review: CMOS Circuit

More information

Lecture 4: DC & Transient Response

Lecture 4: DC & Transient Response Introduction to CMOS VLSI Design Lecture 4: DC & Transient Response David Harris Harvey Mudd College Spring 004 Outline DC Response Logic Levels and Noise Margins Transient Response Delay Estimation Slide

More information

Lecture Outline. ESE 570: Digital Integrated Circuits and VLSI Fundamentals. Total Power. Energy and Power Optimization. Worksheet Problem 1

Lecture Outline. ESE 570: Digital Integrated Circuits and VLSI Fundamentals. Total Power. Energy and Power Optimization. Worksheet Problem 1 ESE 570: Digital Integrated Circuits and VLSI Fundamentals Lec 16: March 20, 2018 Energy and Power Optimization, Design Space Exploration Lecture Outline! Energy and Power Optimization " Tradeoffs! Design

More information

Lecture 5: DC & Transient Response

Lecture 5: DC & Transient Response Lecture 5: DC & Transient Response Outline q Pass Transistors q DC Response q Logic Levels and Noise Margins q Transient Response q RC Delay Models q Delay Estimation 2 Activity 1) If the width of a transistor

More information

Lecture 5. MOS Inverter: Switching Characteristics and Interconnection Effects

Lecture 5. MOS Inverter: Switching Characteristics and Interconnection Effects Lecture 5 MOS Inverter: Switching Characteristics and Interconnection Effects Introduction C load = (C gd,n + C gd,p + C db,n + C db,p ) + (C int + C g ) Lumped linear capacitance intrinsic cap. extrinsic

More information

CARNEGIE MELLON UNIVERSITY DEPARTMENT OF ELECTRICAL AND COMPUTER ENGINEERING DIGITAL INTEGRATED CIRCUITS FALL 2002

CARNEGIE MELLON UNIVERSITY DEPARTMENT OF ELECTRICAL AND COMPUTER ENGINEERING DIGITAL INTEGRATED CIRCUITS FALL 2002 CARNEGIE MELLON UNIVERSITY DEPARTMENT OF ELECTRICAL AND COMPUTER ENGINEERING 18-322 DIGITAL INTEGRATED CIRCUITS FALL 2002 Final Examination, Monday Dec. 16, 2002 NAME: SECTION: Time: 180 minutes Closed

More information

Lecture 6: DC & Transient Response

Lecture 6: DC & Transient Response Lecture 6: DC & Transient Response Slides courtesy of Deming Chen Slides based on the initial set from David Harris CMOS VLSI Design Outline Pass Transistors DC Response Logic Levels and Noise Margins

More information

The Linear-Feedback Shift Register

The Linear-Feedback Shift Register EECS 141 S02 Timing Project 2: A Random Number Generator R R R S 0 S 1 S 2 1 0 0 0 1 0 1 0 1 1 1 0 1 1 1 0 1 1 0 0 1 1 0 0 The Linear-Feedback Shift Register 1 Project Goal Design a 4-bit LFSR SPEED, SPEED,

More information

Digital Integrated Circuits A Design Perspective

Digital Integrated Circuits A Design Perspective Semiconductor Memories Adapted from Chapter 12 of Digital Integrated Circuits A Design Perspective Jan M. Rabaey et al. Copyright 2003 Prentice Hall/Pearson Outline Memory Classification Memory Architectures

More information

Topics to be Covered. capacitance inductance transmission lines

Topics to be Covered. capacitance inductance transmission lines Topics to be Covered Circuit Elements Switching Characteristics Power Dissipation Conductor Sizes Charge Sharing Design Margins Yield resistance capacitance inductance transmission lines Resistance of

More information

EE241 - Spring 2000 Advanced Digital Integrated Circuits. References

EE241 - Spring 2000 Advanced Digital Integrated Circuits. References EE241 - Spring 2000 Advanced Digital Integrated Circuits Lecture 26 Memory References Rabaey, Digital Integrated Circuits Memory Design and Evolution, VLSI Circuits Short Course, 1998.» Gillingham, Evolution

More information

MOS Transistor Theory

MOS Transistor Theory CHAPTER 3 MOS Transistor Theory Outline 2 1. Introduction 2. Ideal I-V Characteristics 3. Nonideal I-V Effects 4. C-V Characteristics 5. DC Transfer Characteristics 6. Switch-level RC Delay Models MOS

More information

EE213, Spr 2017 HW#3 Due: May 17 th, in class. Figure 1

EE213, Spr 2017 HW#3 Due: May 17 th, in class. Figure 1 RULES: Please try to work on your own. Discussion is permissible, but identical submissions are unacceptable! Please show all intermediate steps: a correct solution without an explanation will get zero

More information

P2 (10 points): Given the circuit below, answer the following questions:

P2 (10 points): Given the circuit below, answer the following questions: P1 (10 points): Given the function f(a, b, c, d) = m(3,4,5,10,14) + D(6,7): A: Fill in the timing diagram for f. B: Implement f using only 2-1 MUXes. Your circuit should not include more than four 2-1

More information

! Memory. " RAM Memory. ! Cell size accounts for most of memory array size. ! 6T SRAM Cell. " Used in most commercial chips

! Memory.  RAM Memory. ! Cell size accounts for most of memory array size. ! 6T SRAM Cell.  Used in most commercial chips ESE 57: Digital Integrated Circuits and VLSI Fundamentals Lec : April 3, 8 Memory: Core Cells Today! Memory " RAM Memory " Architecture " Memory core " SRAM " DRAM " Periphery Penn ESE 57 Spring 8 - Khanna

More information

CSE 140 Midterm 2 Tajana Simunic Rosing. Spring 2008

CSE 140 Midterm 2 Tajana Simunic Rosing. Spring 2008 CSE 14 Midterm 2 Tajana Simunic Rosing Spring 28 Do not start the exam until you are told to. Turn off any cell phones or pagers. Write your name and PID at the top of every page. Do not separate the pages.

More information

Where Does Power Go in CMOS?

Where Does Power Go in CMOS? Power Dissipation Where Does Power Go in CMOS? Dynamic Power Consumption Charging and Discharging Capacitors Short Circuit Currents Short Circuit Path between Supply Rails during Switching Leakage Leaking

More information

ECE 438: Digital Integrated Circuits Assignment #4 Solution The Inverter

ECE 438: Digital Integrated Circuits Assignment #4 Solution The Inverter ECE 438: Digital Integrated Circuits Assignment #4 The Inverter Text: Chapter 5, Digital Integrated Circuits 2 nd Ed, Rabaey 1) Consider the CMOS inverter circuit in Figure P1 with the following parameters.

More information

ALU, Latches and Flip-Flops

ALU, Latches and Flip-Flops CSE14: Components and Design Techniques for Digital Systems ALU, Latches and Flip-Flops Tajana Simunic Rosing Where we are. Last time: ALUs Plan for today: ALU example, latches and flip flops Exam #1 grades

More information

Static CMOS Circuits. Example 1

Static CMOS Circuits. Example 1 Static CMOS Circuits Conventional (ratio-less) static CMOS Covered so far Ratio-ed logic (depletion load, pseudo nmos) Pass transistor logic ECE 261 Krish Chakrabarty 1 Example 1 module mux(input s, d0,

More information

EE115C Winter 2017 Digital Electronic Circuits. Lecture 19: Timing Analysis

EE115C Winter 2017 Digital Electronic Circuits. Lecture 19: Timing Analysis EE115C Winter 2017 Digital Electronic Circuits Lecture 19: Timing Analysis Outline Timing parameters Clock nonidealities (skew and jitter) Impact of Clk skew on timing Impact of Clk jitter on timing Flip-flop-

More information

Lecture 9: Clocking, Clock Skew, Clock Jitter, Clock Distribution and some FM

Lecture 9: Clocking, Clock Skew, Clock Jitter, Clock Distribution and some FM Lecture 9: Clocking, Clock Skew, Clock Jitter, Clock Distribution and some FM Mark McDermott Electrical and Computer Engineering The University of Texas at Austin 9/27/18 VLSI-1 Class Notes Why Clocking?

More information

Digital EE141 Integrated Circuits 2nd Combinational Circuits

Digital EE141 Integrated Circuits 2nd Combinational Circuits Digital Integrated Circuits Designing i Combinational Logic Circuits 1 Combinational vs. Sequential Logic 2 Static CMOS Circuit t every point in time (except during the switching transients) each gate

More information

Semiconductor Memories

Semiconductor Memories Semiconductor References: Adapted from: Digital Integrated Circuits: A Design Perspective, J. Rabaey UCB Principles of CMOS VLSI Design: A Systems Perspective, 2nd Ed., N. H. E. Weste and K. Eshraghian

More information

Digital Integrated Circuits A Design Perspective

Digital Integrated Circuits A Design Perspective Digital Integrated Circuits Design Perspective Jan M. Rabaey nantha Chandrakasan orivoje Nikolić Designing Combinational Logic Circuits November 2002. 1 Combinational vs. Sequential Logic In Combinational

More information

EE 434 Lecture 33. Logic Design

EE 434 Lecture 33. Logic Design EE 434 Lecture 33 Logic Design Review from last time: Ask the inverter how it will interpret logic levels V IN V OUT V H =? V L =? V LARGE V H V L V H Review from last time: The two-inverter loop X Y X

More information

LOGIC CIRCUITS. Basic Experiment and Design of Electronics. Ho Kyung Kim, Ph.D.

LOGIC CIRCUITS. Basic Experiment and Design of Electronics. Ho Kyung Kim, Ph.D. Basic Experiment and Design of Electronics LOGIC CIRCUITS Ho Kyung Kim, Ph.D. hokyung@pusan.ac.kr School of Mechanical Engineering Pusan National University Digital IC packages TTL (transistor-transistor

More information

UNIVERSITY OF CALIFORNIA

UNIVERSITY OF CALIFORNIA UNIVERSITY OF CALIFORNIA College of Engineering Department of Electrical Engineering and Computer Sciences Last modified on April 14, 2004 by Brian Leibowitz (bsl@eecs.berkeley.edu) Jan Rabaey Homework

More information

Circuit A. Circuit B

Circuit A. Circuit B UNIVERSITY OF CALIFORNIA College of Engineering Department of Electrical Engineering and Computer Sciences Last modified on November 19, 2006 by Karl Skucha (kskucha@eecs) Borivoje Nikolić Homework #9

More information

CSE241 VLSI Digital Circuits Winter Lecture 07: Timing II

CSE241 VLSI Digital Circuits Winter Lecture 07: Timing II CSE241 VLSI Digital Circuits Winter 2003 Lecture 07: Timing II CSE241 L3 ASICs.1 Delay Calculation Cell Fall Cap\Tr 0.05 0.2 0.5 0.01 0.02 0.16 0.30 0.5 2.0 0.04 0.32 0.178 0.08 0.64 0.60 1.20 0.1ns 0.147ns

More information

CMOS Inverter (static view)

CMOS Inverter (static view) Review: Design Abstraction Levels SYSTEM CMOS Inverter (static view) + MODULE GATE [Adapted from Chapter 5. 5.3 CIRCUIT of G DEVICE Rabaey s Digital Integrated Circuits,, J. Rabaey et al.] S D Review:

More information