5. Sequential Logic x Computation Structures Part 1 Digital Circuits. Copyright 2015 MIT EECS

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1 5. Sequential Logic 6.004x Computation Structures Part 1 igital Circuits Copyright 2015 MIT EECS Computation Structures L5: Sequential Logic, Slide #1

2 Something We Can t Build (Yet) What if you were given the following design specification: #1 button When the button is pushed: 1) Turn the light on if it is off 2) Turn the light off if it is on light #2 The light should change state within a second of the button press What makes this device different from those we ve discussed before? 1. State i.e., the device has memory 2. The output was changed by a input event (pushing a button) rather than an input level Computation Structures L5: Sequential Logic, Slide #2

3 igital State: What We d Like to Build Trigger periodically Input Memory evice LOA Sequence of values Current State Combinational Logic Next State Output Plan: Build a Sequential Circuit with stored digital STATE Memory stores CURRENT state, produced at output Combinational Logic computes NEXT state (from input, current state) OUTPUT bits (from input, current state) State changes on LOA control input Needed: Loadable Memory Computation Structures L5: Sequential Logic, Slide #3

4 We ve chosen to encode information using voltages and we know from physics that we can store a voltage as charge on a capacitor: bit line Memory: Using Capacitors NFET serves as access switch word line V REF C To write: rive bit line, turn on access fet, force storage cap to new voltage To read: precharge bit line, turn on access fet, detect (small) change in bit line voltage Pros: compact low cost/bit (on BI memories) Cons: complex interface stable? (noise, ) it leaks! refresh Suppose we use feedback to refresh continuously? Computation Structures L5: Sequential Logic, Slide #4

5 Memory: Using Feedback IEA: use positive feedback to maintain storage indefinitely. Our logic gates are built to restore marginal signal levels, so noise shouldn t be a problem! Result: a bistable storage element V OUT V IN VTC for inverter pair Feedback constraint: V IN = V OUT V OUT Not affected by noise Three solutions: two end-points are stable middle point is metastable V IN We ll get back to this! Computation Structures L5: Sequential Logic, Slide #5

6 Settable Memory Element It s easy to build a settable storage element (called a latch) using a lenient MUX: Here s a feedback path, so it s no longer a combinational circuit. state signal appears as both input and output A B S 0 1 S : data input : gate input : state output Y Computation Structures L5: Sequential Logic, Slide # stable follows

7 New evice: Latch Circuit: 0 1 =1: follows V1 V2 =0: holds Schematic Symbol: T P V1 T P V2 =1: Follows, independently of =0: Holds stable, independently of BUT A change in or contaminates, hence how can this possibly work? Computation Structures L5: Sequential Logic, Slide #7

8 A Plea for Lenience X X 1 X X X X 1 1 V1 V2 T P V1 V2 Assume LENIENT Mux, propagation delay of T P Then output valid when 1. =1, stable for T P, independently of ; or 2. = stable for T P, independently of ; or T P T P oes lenience guarantee a working latch? What if and change at about the same time 3. =0, stable for T P, independently of Computation Structures L5: Sequential Logic, Slide #8

9 With a Little iscipline Stable A 0 1 To reliably latch V2: Apply V2 to, holding =1 After T P, V2 appears at = After another T P, & both valid for T P ; will hold =V2 independently of Set =0, while & hold = After another T P, =0 and are sufficient to hold =V2 independently of V2 V2 T P T P T P T SETUP T HOL ynamic iscipline for our latch: T SETUP = 2T P : interval prior to transition for which must be stable & valid T HOL = T P : interval following transition for which must be stable & valid Computation Structures L5: Sequential Logic, Slide #9

10 Let s Try It Out! Current State Combinational Logic New State Input When =1, latch is Transparent provides a combinational path from to. Can t work without tricky timing constraints on =1 pulse: Must fit within contamination delay of logic Must accommodate latch setup, hold times Want to signal an INSTANT, not an INTERVAL Output Looks like a stupid approach to me Computation Structures L5: Sequential Logic, Slide #10

11 Flakey Control Systems Sequence of values How do we ensure only one car gets through? ate closed ate open Computation Structures L5: Sequential Logic, Slide #11

12 Solution: Escapement Strategy (2 gates) ate 2 ate 2 ate 1 ate 1 ate 1: open ate 2: closed Sequence of values Key: at no time is there a path through both gates ate 1: closed ate 2: open Computation Structures L5: Sequential Logic, Slide #12

13 (Edge-Triggered) Register 0 1 S What does that one do? CLK The gate of this latch is open when the clock is low master slave Observations: only one latch transparent at any time: master closed when slave is open slave closed when master is open no combinational path through register The gate of this latch is open when the clock is high (the feedback path in one of the master or slave latches is always active) Computation Structures L5: Sequential Logic, Slide #13

14 -Register Waveforms master slave CLK CLK CLK master closed slave open master open slave closed Computation Structures L5: Sequential Logic, Slide #14

15 Um, about that hold time master slave CLK CLK The master s contamination delay must meet the hold time of the slave: t C,M t H,S Slave latch is closing must meet setup/hold times but master latch is opening so may change Computation Structures L5: Sequential Logic, Slide #15

16 -Register Timing 1 t P t C CLK CLK t P : maximum propagation delay, CLK t C : minimum contamination delay, CLK t SETUP t HOL t SETUP : setup time guarantee that has propagated through feedback path before master closes t HOL : hold time guarantee master is closed and data is stable before allowing to change Computation Structures L5: Sequential Logic, Slide #16

17 Single-clock Synchronous Circuits oes that symbol register? We ll use registers in a highly constrained way to build digital systems: Single-clock Synchronous iscipline No combinational cycles Single periodic clock signal shared among all clocked devices Only care about value of register data inputs just before rising edge of clock Period greater than every combinational delay + setup time Change saved state after noise-inducing logic transitions have stopped! Computation Structures L5: Sequential Logic, Slide #17

18 Timing in a Single-clock System CLK CLK R1 reg1 t C, L R1 t C,reg1 t 1 L t P,reg1 t P, L t 2 reg2 uestions for register-based designs: how much time for useful work (i.e. for combinational logic delay)? what happens if there s no combinational logic between two registers? œ what happens if CLK signal t SETUP,reg2 doesn t arrive at the two t 1 = t C,reg1 + t C,L t registers at exactly the HOL,reg2 same time (a phenomenon t 2 = t P,reg1 + t P,L + t SETUP,reg2 t CLK known as clock skew )? Computation Structures L5: Sequential Logic, Slide #18

19 Model: iscrete Time Clock RE Memory State updated every rising clock edge Current State Combinational Logic Next State Input Output Active Clock Edges punctuate time --- iscrete Clock periods Sequences of states Simple rules eg truth tables relating outputs to inputs and the current state) ABSTRACTION: Finite State Machines (next lecture!) Computation Structures L5: Sequential Logic, Slide #19

20 Sequential Circuit Timing Clock Input t C,R = 1ns t P,R = 3ns t S,R = 2ns t H,R = 2ns Current State Combinational Logic t C,L =? t P,L = 5ns Next State Output uestions: Constraints on t C for the logic? Minimum clock period? t C,R (1 ns) + t C,L (?) t H,R (2 ns) t C,L 1 ns t CLK t P,R +t P,L + t S,R = 10nS Setup, Hold times for Inputs? t S,INPUT = t P,L + t S,R = 7 ns t H,INPUT = t H,R - t C,L = 1 ns Input Next State Computation Structures L5: Sequential Logic, Slide #20 clk t S,R t P,L t C,L t H,R

21 Summary Basic memory elements: Feedback, detailed analysis => basic level-sensitive devices (eg, latch) 2 Latches => Register ynamic iscipline: constraints on input timing Synchronous 1-clock logic: Simple rules for sequential circuits Yields clocked circuit with T S, T H constraints on input timing Finite State Machines Next Lecture Topic! Clk In Clk >t S >t H >t C <t P Out Combinational logic Computation Structures L5: Sequential Logic, Slide #21