Chapter 7 Sequential Logic
|
|
- Rodney Robbins
- 5 years ago
- Views:
Transcription
1 Chapter 7 Sequential Logic SKEE2263 Digital Systems Mun im/ismahani/izam {munim@utm.my,e-izam@utm.my,ismahani@fke.utm.my} March 28, 2016
2 Table of Contents 1 Intro 2 Bistable Circuits 3 FF Characteristics 4 FF Excitation
3 Classes of Digital Circuits Digital Circuits Combinational Sequential Asynchronous Synchronous
4 Sequential vs Combinational Combinational: Output = f(present Input) Memoryless Sequential: Output = f(present Input, Past Input) Uses latches/flip-flop as memory May have clock input (synchronous) or not (asynchronous)
5 Clocks Asynchronous sequential circuits have no clock input Inputs Combinational logic Outputs Inputs Combinational logic Outputs Memory elements Memory elements Clock
6 Clock Parts Clock period Clock width Rising edge Falling edge
7 SR Latch: Gate Level Bistable circuits: stable in state 0 or 1 Simplest bistable is SR latch R S
8 SR Latch: Logic Symbol, Characteristic Table S R S R + + Action 0 0 No change Reset Set Forbidden
9 SR Latch: Timing Diagram S R Unknown values Set Reset Set Illegal inputs Both outputs LOW
10 S R Latch: Gate Level, Characteristic Table S R S R + + Action Forbidden Set Reset 1 1 No change
11 Gated SR Latch: Logic Symbol, Characteristic Table S EN R EN S R + Action 0 No change No change Reset Set Forbidden
12 Gated SR Latch: Timing Diagram EN S R Set Reset
13 Gated D Latch: Logic Symbol, Characteristic Table D EN EN D + Action 0 Storage state Transparent mode Transparent mode
14 Gated D Latch: Timing Diagram EN D
15 D Flip-Flop: Logic Symbol, Characteristic Table D Clk D + Action 0 No change 1 No change 0 0 Reset 1 1 Set
16 JK Flip-Flop: Logic Symbol, Characteristic Table Clk J K + Action J K 0 No change 1 No change 0 0 No change Reset Set 1 1 Toggle
17 T Flip-Flop: Logic Symbol, Characteristic Table T Clk D + Action 0 No change 1 No change 0 No change 1 Toggle
18 FF Timing Parameters Data input Clock t SU t H Flip-flop output t CO
19 FF Timing Parameters Setup time, t SU the minimum time that a flip-flop input must be stable before the clock edge. Hold time, t H the minimum time after the clock edge that a flip-flop input must continue to be in the same stable state. Clock to output delay time, t CO the minimum time after a clock edge to obtain a valid output
20 Setup Time Violation Data input t SU Input violates t SU t H Clock Metastable output A Metastable output B t CO Resolves to new data after t Reverts to old data after t CO CO
21 Causes of Metastability Asynchronous Inputs. DIN D XDATA D DOUT TCLK RCLK Transmitter Receiver Data transfer across clock domains.
22 What Happens During Metastability Stable state 0 Stable state 1 Metastable state
23 Solution for Metastability Asynchronous input D Metastable signal D Synchronous signal Synchronous system CLK Two-stage synchronizer
24 D Flip-Flop Characteristic table: D + Operation 0 0 Reset 1 1 Set Excitation table: Present Next State State Input + D Characteristic Equation: + = D D = 0 State diagram: D = 1 = 0 = 1 D = 0 D = 1
25 T Flip-Flop Characteristic table: T + Operation 0 No change 1 Complement Excitation table: Present Next State State Input + T Characteristic Equation: + = T + T = T T = 0 State diagram: T = 1 = 0 = 1 T = 1 T = 0
26 JK Flip-Flop Characteristic table: J K + Operation 0 0 No change Reset Set 1 1 Complement Excitation table: Present Next State State Inputs + J K Characteristic Equation: + = J + K State diagram: JK=10 or 11 JK=00 or 01 = 0 = 1 JK=01 or 11 JK=00 or 10
27 SR Flip-Flop Characteristic table: S R + Operation 0 0 No change Reset Set 1 1? Undefined Excitation table: Present Next State State Inputs + S R Characteristic Equation: + = S + R SR 1 State diagram: S R = 1 0 S R = 0 0 o r 0 1 = 0 = 1 S R = 0 1 S R = 0 0 o r 1 0
28 Excitation Table Summary + S R D J K T
Sequential vs. Combinational
Sequential Circuits Sequential vs. Combinational Combinational Logic: Output depends only on current input TV channel selector (-9) inputs system outputs Sequential Logic: Output depends not only on current
More informationELCT201: DIGITAL LOGIC DESIGN
ELCT201: DIGITAL LOGIC DESIGN Dr. Eng. Haitham Omran, haitham.omran@guc.edu.eg Dr. Eng. Wassim Alexan, wassim.joseph@guc.edu.eg Lecture 6 Following the slides of Dr. Ahmed H. Madian محرم 1439 ه Winter
More informationChapter 14 Sequential logic, Latches and Flip-Flops
Chapter 14 Sequential logic, Latches and Flip-Flops Flops Lesson 4 JK Flip Flop Ch14L4-"Digital Principles and Design", Raj Kamal, Pearson Education, 2006 2 JK Flip-Flop ve edge triggered Output Q and
More informationI. Motivation & Examples
I. Motivation & Examples Output depends on current input and past history of inputs. State embodies all the information about the past needed to predict current output based on current input. State variables,
More informationECEN 248: INTRODUCTION TO DIGITAL SYSTEMS DESIGN. Week 7 Dr. Srinivas Shakkottai Dept. of Electrical and Computer Engineering
ECEN 248: INTRODUCTION TO DIGITAL SYSTEMS DESIGN Week 7 Dr. Srinivas Shakkottai Dept. of Electrical and Computer Engineering SEQUENTIAL CIRCUITS: LATCHES Overview Circuits require memory to store intermediate
More informationSynchronous Sequential Logic
1 IT 201 DIGITAL SYSTEMS DESIGN MODULE4 NOTES Synchronous Sequential Logic Sequential Circuits - A sequential circuit consists of a combinational circuit and a feedback through the storage elements in
More informationL4: Sequential Building Blocks (Flip-flops, Latches and Registers)
L4: Sequential Building Blocks (Flip-flops, Latches and Registers) Acknowledgements:., Materials in this lecture are courtesy of the following people and used with permission. - Randy H. Katz (University
More informationTopic 8: Sequential Circuits
Topic 8: Sequential Circuits Readings : Patterson & Hennesy, Appendix B.4 - B.6 Goals Basic Principles behind Memory Elements Clocks Applications of sequential circuits Introduction to the concept of the
More informationL4: Sequential Building Blocks (Flip-flops, Latches and Registers)
L4: Sequential Building Blocks (Flip-flops, Latches and Registers) Acknowledgements: Lecture material adapted from R. Katz, G. Borriello, Contemporary Logic esign (second edition), Prentice-Hall/Pearson
More informationDigital Circuits and Systems
EE201: Digital Circuits and Systems 4 Sequential Circuits page 1 of 11 EE201: Digital Circuits and Systems Section 4 Sequential Circuits 4.1 Overview of Sequential Circuits: Definition The circuit whose
More informationI. Motivation & Examples
I. Motivation & Examples Output depends on current input and past history of inputs. State embodies all the information about the past needed to predict current output based on current input. State variables,
More informationIntroduction EE 224: INTRODUCTION TO DIGITAL CIRCUITS & COMPUTER DESIGN. Lecture 6: Sequential Logic 3 Registers & Counters 5/9/2010
EE 224: INTROUCTION TO IGITAL CIRCUITS & COMPUTER ESIGN Lecture 6: Sequential Logic 3 Registers & Counters 05/10/2010 Avinash Kodi, kodi@ohio.edu Introduction 2 A Flip-Flop stores one bit of information
More informationLOGIC CIRCUITS. Basic Experiment and Design of Electronics
Basic Experiment and Design of Electronics LOGIC CIRCUITS Ho Kyung Kim, Ph.D. hokyung@pusan.ac.kr School of Mechanical Engineering Pusan National University Outline Combinational logic circuits Output
More informationELCT201: DIGITAL LOGIC DESIGN
ELCT201: DIGITAL LOGIC DESIGN Dr. Eng. Haitham Omran, haitham.omran@guc.edu.eg Dr. Eng. Wassim Alexan, wassim.joseph@guc.edu.eg Following the slides of Dr. Ahmed H. Madian Lecture 10 محرم 1439 ه Winter
More informationSequential Circuit Analysis
Sequential Circuit Analysis Last time we started talking about latches and flip-flops, which are basic one-bit memory units. Today we ll talk about sequential circuit analysis and design. First, we ll
More informationSequential Logic. Rab Nawaz Khan Jadoon DCS. Lecturer COMSATS Lahore Pakistan. Department of Computer Science
Sequential Logic Rab Nawaz Khan Jadoon DCS COMSATS Institute of Information Technology Lecturer COMSATS Lahore Pakistan Digital Logic and Computer Design Sequential Logic Combinational circuits with memory
More informationChapter 5 Synchronous Sequential Logic
Chapter 5 Synchronous Sequential Logic Sequential circuit: A circuit that includes memory elements. In this case the output depends not only on the current input but also on the past inputs. Memory A synchronous
More informationDigital Logic Design - Chapter 4
Digital Logic Design - Chapter 4 1. Analyze the latch circuit shown below by obtaining timing diagram for the circuit; include propagation delays. Y This circuit has two external input and one feedback
More informationFundamentals of Digital Design
Fundamentals of Digital Design Digital Radiation Measurement and Spectroscopy NE/RHP 537 1 Binary Number System The binary numeral system, or base-2 number system, is a numeral system that represents numeric
More informationLecture 14: State Tables, Diagrams, Latches, and Flip Flop
EE210: Switching Systems Lecture 14: State Tables, Diagrams, Latches, and Flip Flop Prof. YingLi Tian Nov. 6, 2017 Department of Electrical Engineering The City College of New York The City University
More informationSequential Logic Circuits
Chapter 4 Sequential Logic Circuits 4 1 The defining characteristic of a combinational circuit is that its output depends only on the current inputs applied to the circuit. The output of a sequential circuit,
More informationDigital Logic and Design (Course Code: EE222) Lecture 19: Sequential Circuits Contd..
Indian Institute of Technology Jodhpur, Year 2017-2018 Digital Logic and Design (Course Code: EE222) Lecture 19: Sequential Circuits Contd.. Course Instructor: Shree Prakash Tiwari Email: sptiwari@iitj.ac.in
More informationIntroduction to Digital Logic
Introduction to Digital Logic Lecture 17: Latches Flip-Flops Problem w/ Bistables Output should have been at end of sequence Problem: Glitch was remembered Need some way to ignore inputs until they are
More informationLOGIC CIRCUITS. Basic Experiment and Design of Electronics. Ho Kyung Kim, Ph.D.
Basic Experiment and Design of Electronics LOGIC CIRCUITS Ho Kyung Kim, Ph.D. hokyung@pusan.ac.kr School of Mechanical Engineering Pusan National University Digital IC packages TTL (transistor-transistor
More informationEET 310 Flip-Flops 11/17/2011 1
EET 310 Flip-Flops 11/17/2011 1 FF s and some Definitions Clock Input: FF s are controlled by a trigger or Clock signal. All FF s have a clock input. If a device which attempts to do a FF s task does not
More informationSequential Circuits Sequential circuits combinational circuits state gate delay
Sequential Circuits Sequential circuits are those with memory, also called feedback. In this, they differ from combinational circuits, which have no memory. The stable output of a combinational circuit
More informationFundamentals of Computer Systems
Fundamentals of Computer Systems Sequential Logic Stephen A. Edwards Columbia University Summer 2017 State-Holding Elements Bistable Elements S Latch Latch Positive-Edge-Triggered Flip-Flop Flip-Flop with
More informationChapter 4. Sequential Logic Circuits
Chapter 4 Sequential Logic Circuits 1 2 Chapter 4 4 1 The defining characteristic of a combinational circuit is that its output depends only on the current inputs applied to the circuit. The output of
More informationProblem Set 9 Solutions
CSE 26 Digital Computers: Organization and Logical Design - 27 Jon Turner Problem Set 9 Solutions. For each of the sequential circuits shown below, draw in the missing parts of the timing diagrams. You
More informationIntegrated Circuits & Systems
Federal University of Santa Catarina Center for Technology Computer Science & Electronics Engineering Integrated Circuits & Systems INE 5442 Lecture 18 CMOS Sequential Circuits - 1 guntzel@inf.ufsc.br
More informationLecture 7: Sequential Networks
CSE 140: Components and Design Techniques for Digital Systems Lecture 7: Sequential Networks CK Cheng Dept. of Computer Science and Engineering University of California, San Diego 1 Part II: Sequential
More informationQ: Examine the relationship between X and the Next state. How would you describe this circuit? A: An inverter which is synched with a clock signal.
/2/2 OF 7 Next, let s reverse engineer a T-Flip flop Prob. (Pg 529) Note that whenever T is equal to, there is a state change, otherwise, there isn t. In this circuit, (x) determines whether the output
More informationELE2120 Digital Circuits and Systems. Tutorial Note 9
ELE2120 Digital Circuits and Systems Tutorial Note 9 Outline 1. Exercise(1) Sequential Circuit Analysis 2. Exercise (2) Sequential Circuit Analysis 3. Exercise (3) Sequential Circuit Analysis 4. Ref. Construction
More informationTopic 8: Sequential Circuits. Bistable Devices. S-R Latches. Consider the following element. Readings : Patterson & Hennesy, Appendix B.4 - B.
Topic 8: Sequential Circuits Bistable Devices Readings : Consider the following element Patterson & Hennesy, Appendix B.4 - B.6 Goals Basic Principles behind Memory Elements Clocks Applications of sequential
More informationChapter 13. Clocked Circuits SEQUENTIAL VS. COMBINATIONAL CMOS TG LATCHES, FLIP FLOPS. Baker Ch. 13 Clocked Circuits. Introduction to VLSI
Chapter 13 Clocked Circuits SEQUENTIAL VS. COMBINATIONAL CMOS TG LATCHES, FLIP FLOPS SET-RESET (SR) ARBITER LATCHES FLIP FLOPS EDGE TRIGGERED DFF FF TIMING Joseph A. Elias, Ph.D. Adjunct Professor, University
More informationP2 (10 points): Given the circuit below, answer the following questions:
P1 (10 points): Given the function f(a, b, c, d) = m(3,4,5,10,14) + D(6,7): A: Fill in the timing diagram for f. B: Implement f using only 2-1 MUXes. Your circuit should not include more than four 2-1
More informationCounters. We ll look at different kinds of counters and discuss how to build them
Counters We ll look at different kinds of counters and discuss how to build them These are not only examples of sequential analysis and design, but also real devices used in larger circuits 1 Introducing
More informationSynchronous Sequential Logic Part I. BME208 Logic Circuits Yalçın İŞLER
Synchronous Sequential Logic Part I BME28 Logic Circuits Yalçın İŞLER islerya@yahoo.com http://me.islerya.com Sequential Logic Digital circuits we have learned, so far, have been combinational no memory,
More informationDigital Circuits ECS 371
Digital Circuits ECS 371 Dr. Prapun Suksompong prapun@siit.tu.ac.th Lecture 18 Office Hours: BKD 3601-7 Monday 9:00-10:30, 1:30-3:30 Tuesday 10:30-11:30 1 Announcement Reading Assignment: Chapter 7: 7-1,
More informationDifferent encodings generate different circuits
FSM State Encoding Different encodings generate different circuits no easy way to find best encoding with fewest logic gates or shortest propagation delay. Binary encoding: K states need log 2 K bits i.e.,
More informationRoger L. Tokheim. Chapter 8 Counters Glencoe/McGraw-Hill
Digital Electronics Principles & Applications Sixth Edition Roger L. Tokheim Chapter 8 Counters 2003 Glencoe/McGraw-Hill INTRODUCTION Overview of Counters Characteristics of Counters Ripple Up Counter
More informationEE141- Spring 2007 Digital Integrated Circuits
EE141- Spring 27 igital Integrated Circuits Lecture 19 Sequential Circuits 1 Administrative Stuff Project Ph. 2 due Tu. 5pm 24 Cory box + email ee141- project@bwrc.eecs.berkeley.edu Hw 8 Posts this Fr.,
More informationELEC Digital Logic Circuits Fall 2014 Sequential Circuits (Chapter 6) Finite State Machines (Ch. 7-10)
ELEC 2200-002 Digital Logic Circuits Fall 2014 Sequential Circuits (Chapter 6) Finite State Machines (Ch. 7-10) Vishwani D. Agrawal James J. Danaher Professor Department of Electrical and Computer Engineering
More informationUMBC. At the system level, DFT includes boundary scan and analog test bus. The DFT techniques discussed focus on improving testability of SAFs.
Overview Design for testability(dft) makes it possible to: Assure the detection of all faults in a circuit. Reduce the cost and time associated with test development. Reduce the execution time of performing
More informationClocked Synchronous State-machine Analysis
Clocked Synchronous State-machine Analysis Given the circuit diagram of a state machine: Analyze the combinational logic to determine flip-flop input (excitation) equations: D i = F i (Q, inputs) The input
More informationCSE140: Components and Design Techniques for Digital Systems. Midterm Information. Instructor: Mohsen Imani. Sources: TSR, Katz, Boriello & Vahid
CSE140: Components and Design Techniques for Digital Systems Midterm Information Instructor: Mohsen Imani Midterm Topics In general: everything that was covered in homework 1 and 2 and related lectures,
More informationSequential Circuit Design
Sequential Circuit esign esign Procedure. Specification 2. Formulation Obtain a state diagram or state table 3. State Assignment Assign binary codes to the states 4. Flip-Flop Input Equation etermination
More informationDigital Electronics Sequential Logic
/5/27 igital Electronics Sequential Logic r. I. J. Wassell Sequential Logic The logic circuits discussed previously are known as combinational, in that the output depends only on the condition of the latest
More informationSequential Logic Worksheet
Sequential Logic Worksheet Concept Inventory: Notes: D-latch & the Dynamic Discipline D-register Timing constraints for sequential circuits Set-up and hold times for sequential circuits 6.004 Worksheet
More informationMemory Elements I. CS31 Pascal Van Hentenryck. CS031 Lecture 6 Page 1
Memory Elements I CS31 Pascal Van Hentenryck CS031 Lecture 6 Page 1 Memory Elements (I) Combinational devices are good for computing Boolean functions pocket calculator Computers also need to remember
More informationModule - 19 Gated Latches
Digital Circuits and Systems Prof. Shankar Balachandran Department of Electrical Engineering Indian Institute of Technology, Bombay And Department of Computer Science and Engineering Indian Institute of
More informationChapter 6 Introduction to state machines
9..7 hapter 6 Introduction to state machines Dr.-Ing. Stefan Werner Table of content hapter : Switching Algebra hapter : Logical Levels, Timing & Delays hapter 3: Karnaugh-Veitch-Maps hapter 4: ombinational
More informationCPE100: Digital Logic Design I
Chapter 3 Professor Brendan Morris, SEB 3216, brendan.morris@unlv.edu http://www.ee.unlv.edu/~b1morris/cpe1/ CPE1: Digital Logic Design I Section 14: Dr. Morris Sequential Logic Design Chapter 3 Chapter
More informationWeek-5. Sequential Circuit Design. Acknowledgement: Most of the following slides are adapted from Prof. Kale's slides at UIUC, USA.
Week-5 Sequential Circuit Design Acknowledgement: Most of the following slides are adapted from Prof. Kale's slides at UIUC, USA. Storing a value: SR = 00 What if S = 0 and R = 0? The equations on the
More informationSynchronous Sequential Logic Part I
Synchronous Sequential Logic Part I Mantıksal Tasarım BBM23 section instructor: Ufuk Çelikcan Sequential Logic Digital circuits we have learned, so far, have been combinational no memory, outputs are entirely
More informationVidyalankar S.E. Sem. III [ETRX] Digital Circuits and Design Prelim Question Paper Solution
S.E. Sem. III [ETRX] Digital Circuits and Design Prelim uestion Paper Solution. (a) Static Hazard Static hazards have two cases: static and static. static- hazard exists when the output variable should
More informationSynchronous Sequential Circuit
Synchronous Sequential Circuit The change of internal state occurs in response to the synchronized clock pulses. Data are read during the clock pulse (e.g. rising-edge triggered) It is supposed to wait
More informationChapter 3. Digital Design and Computer Architecture, 2 nd Edition. David Money Harris and Sarah L. Harris. Chapter 3 <1>
Chapter 3 Digital Design and Computer Architecture, 2 nd Edition David Money Harris and Sarah L. Harris Chapter 3 Chapter 3 :: Topics Introduction Latches and Flip-Flops Synchronous Logic Design Finite
More information6. Finite State Machines
6. Finite State Machines 6.4x Computation Structures Part Digital Circuits Copyright 25 MIT EECS 6.4 Computation Structures L6: Finite State Machines, Slide # Our New Machine Clock State Registers k Current
More informationESE 570: Digital Integrated Circuits and VLSI Fundamentals
ESE 570: Digital Integrated Circuits and VLSI Fundamentals Lec 17: March 23, 2017 Energy and Power Optimization, Design Space Exploration, Synchronous MOS Logic Lecture Outline! Energy and Power Optimization
More informationDigital Design. Sequential Logic
Principles Of igital esign Chapter 6 Sequential Logic Chapter preview Boolean algebra 3 Logic gates and flip-flops 3 Finite-state machine 6 Logic design techniques 4 Sequential design techniques 6 Binary
More informationALU, Latches and Flip-Flops
CSE14: Components and Design Techniques for Digital Systems ALU, Latches and Flip-Flops Tajana Simunic Rosing Where we are. Last time: ALUs Plan for today: ALU example, latches and flip flops Exam #1 grades
More informationState & Finite State Machines
State & Finite State Machines Hakim Weatherspoon CS 3410, Spring 2012 Computer Science Cornell University See P&H Appendix C.7. C.8, C.10, C.11 Big Picture: Building a Processor memory inst register file
More informationLecture 17: Designing Sequential Systems Using Flip Flops
EE210: Switching Systems Lecture 17: Designing Sequential Systems Using Flip Flops Prof. YingLi Tian April 11, 2019 Department of Electrical Engineering The City College of New York The City University
More informationELEN Electronique numérique
ELEN0040 - Electronique numérique Patricia ROUSSEAUX Année académique 2014-2015 CHAPITRE 3 Combinational Logic Circuits ELEN0040 3-4 1 Combinational Functional Blocks 1.1 Rudimentary Functions 1.2 Functions
More informationChapter #6: Sequential Logic Design
Chapter #6: equential Logic esign Contemporary Logic esign No. 6- Cross-Coupled NO Gates ust like cascaded inverters, with capability to force output to (reset) or (set) \ eset Hold et eset et ace \ Forbidden
More informationMenu. Part 2 of 3701: Sequential Digital Machines Latches and Flip-Flops: >S-R latches >D latches >T latches. Comb. n. Logic. m Q.
Menu Part 2 of 3701: equential Digital Machines Latches and Flip-Flops: >- latches >D latches >T latches Look into my... 1 Topic 2 : equential Digital Machines or equential Logic LID from Lecture #2 X
More informationCHW 261: Logic Design
CHW 26: Logic Design Instructors: Prof. Hala Zayed Dr. Ahmed Shalaby http://www.bu.edu.eg/staff/halazayed4 http://bu.edu.eg/staff/ahmedshalaby4# Slide Digital Fundamentals CHAPTER 8 Counters Slide 2 Counting
More informationGates and Flip-Flops
Gates and Flip-Flops Chris Kervick (11355511) With Evan Sheridan and Tom Power December 2012 On a scale of 1 to 10, how likely is it that this question is using binary?...4? What s a 4? Abstract The operation
More informationALU A functional unit
ALU A functional unit that performs arithmetic operations such as ADD, SUB, MPY logical operations such as AND, OR, XOR, NOT on given data types: 8-,16-,32-, or 64-bit values A n-1 A n-2... A 1 A 0 B n-1
More informationKing Fahd University of Petroleum and Minerals College of Computer Science and Engineering Computer Engineering Department
King Fahd University of Petroleum and Minerals College of Computer Science and Engineering Computer Engineering Department Page 1 of 13 COE 202: Digital Logic Design (3-0-3) Term 112 (Spring 2012) Final
More informationComputers also need devices capable of Storing data and information Performing mathematical operations on such data
Sequential Machines Introduction Logic devices examined so far Combinational Output function of input only Output valid as long as input true Change input change output Computers also need devices capable
More information10/12/2016. An FSM with No Inputs Moves from State to State. ECE 120: Introduction to Computing. Eventually, the States Form a Loop
University of Illinois at Urbana-Champaign Dept. of Electrical and Computer Engineering An FSM with No Inputs Moves from State to State What happens if an FSM has no inputs? ECE 120: Introduction to Computing
More informationCPE100: Digital Logic Design I
Professor Brendan Morris, SEB 3216, brendan.morris@unlv.edu CPE100: Digital Logic Design I Midterm02 Review http://www.ee.unlv.edu/~b1morris/cpe100/ 2 Logistics Thursday Nov. 16 th In normal lecture (13:00-14:15)
More informationState & Finite State Machines
State & Finite State Machines Hakim Weatherspoon CS 3410, Spring 2012 Computer Science Cornell University See P&H Appendix C.7. C.8, C.10, C.11 Stateful Components Until now is combinatorial logic Output
More informationAppendix B. Review of Digital Logic. Baback Izadi Division of Engineering Programs
Appendix B Review of Digital Logic Baback Izadi Division of Engineering Programs bai@engr.newpaltz.edu Elect. & Comp. Eng. 2 DeMorgan Symbols NAND (A.B) = A +B NOR (A+B) = A.B AND A.B = A.B = (A +B ) OR
More informationECE/Comp Sci 352 Digital Systems Fundamentals. Charles R. Kime Section 2 Fall Logic and Computer Design Fundamentals
University of Wisconsin - Madison ECE/Comp Sci 352 Digital Systems Fundamentals Charles R. Kime Section 2 Fall 2001 Lecture 5 Registers & Counters Part 2 Charles Kime Counters Counters are sequential circuits
More informationCOEN 312 DIGITAL SYSTEMS DESIGN - LECTURE NOTES Concordia University
1 OEN 312 DIGIAL SYSEMS DESIGN - LEURE NOES oncordia University hapter 6: Registers and ounters NOE: For more examples and detailed description of the material in the lecture notes, please refer to the
More informationUNIVERSITY OF BOLTON SCHOOL OF ENGINEERING BENG (HONS) ELECTRICAL & ELECTRONICS ENGINEERING EXAMINATION SEMESTER /2017
UNIVERSITY OF BOLTON TW35 SCHOOL OF ENGINEERING BENG (HONS) ELECTRICAL & ELECTRONICS ENGINEERING EXAMINATION SEMESTER 2-2016/2017 INTERMEDIATE DIGITAL ELECTRONICS AND COMMUNICATIONS MODULE NO: EEE5002
More informationCHAPTER 9: SEQUENTIAL CIRCUITS
CHAPTER 9: ASYNCHRONOUS SEUENTIAL CIRCUITS Chapter Objectives 2 Sequential circuits that are not snchronized b a clock Asnchronous circuits Analsis of Asnchronous circuits Snthesis of Asnchronous circuits
More informationCS221: Digital Design. Dr. A. Sahu. Indian Institute of Technology Guwahati
CS221: Digital Design Counter&Registers Dr. A. Sahu DeptofComp.Sc.&Engg. Indian Institute of Technology Guwahati Outline Counter : Synchronous Vs Asynchronous Counter: Finite it State t Machine Mhi A register
More informationCMPEN 411. Spring Lecture 18: Static Sequential Circuits
CMPEN 411 VLSI Digital Circuits Spring 2011 Lecture 18: Static Sequential Circuits [Adapted from Rabaey s Digital Integrated Circuits, Second Edition, 2003 J. Rabaey, A. Chandrakasan, B. Nikolic] Sp11
More informationMAHALAKSHMI ENGINEERING COLLEGE TIRUCHIRAPALLI
DEPARTMENT: ECE MAHALAKSHMI ENGINEERING COLLEGE TIRUCHIRAPALLI 6 QUESTION BANK SUBJECT NAME: DIGITAL ELECTRONICS UNIT : Design of Sequential Circuits PART A ( Marks). Draw the logic diagram 4: Multiplexer.(AUC
More informationLecture 10: Synchronous Sequential Circuits Design
Lecture 0: Synchronous Sequential Circuits Design. General Form Input Combinational Flip-flops Combinational Output Circuit Circuit Clock.. Moore type has outputs dependent only on the state, e.g. ripple
More informationCOE 202: Digital Logic Design Sequential Circuits Part 4. Dr. Ahmad Almulhem ahmadsm AT kfupm Phone: Office:
COE 202: Digital Logic Design Sequential Circuits Part 4 Dr. Ahmad Almulhem Email: ahmadsm AT kfupm Phone: 860-7554 Office: 22-324 Objectives Registers Counters Registers 0 1 n-1 A register is a group
More informationDesign of Datapath Controllers
Design of Datapath Controllers Speaker: 俞子豪 Adviser: Prof. An-Yeu Wu ACCESS IC LAB Outline vsequential Circuit Model vfinite State Machines vuseful Modeling Techniques P. 2 Model of Sequential Circuits
More informationLaboratory Exercise #8 Introduction to Sequential Logic
Laboratory Exercise #8 Introduction to Sequential Logic ECEN 248: Introduction to Digital Design Department of Electrical and Computer Engineering Texas A&M University 2 Laboratory Exercise #8 1 Introduction
More informationPreparation of Examination Questions and Exercises: Solutions
Questions Preparation of Examination Questions and Exercises: Solutions. -bit Subtraction: DIF = B - BI B BI BO DIF 2 DIF: B BI 4 6 BI 5 BO: BI BI 4 5 7 3 2 6 7 3 B B B B B DIF = B BI ; B = ( B) BI ( B),
More informationDigital Logic: Boolean Algebra and Gates. Textbook Chapter 3
Digital Logic: Boolean Algebra and Gates Textbook Chapter 3 Basic Logic Gates XOR CMPE12 Summer 2009 02-2 Truth Table The most basic representation of a logic function Lists the output for all possible
More information5. Sequential Logic x Computation Structures Part 1 Digital Circuits. Copyright 2015 MIT EECS
5. Sequential Logic 6.004x Computation Structures Part 1 igital Circuits Copyright 2015 MIT EECS 6.004 Computation Structures L5: Sequential Logic, Slide #1 Something We Can t Build (Yet) What if you were
More informationEECS Components and Design Techniques for Digital Systems. FSMs 9/11/2007
EECS 150 - Components and Design Techniques for Digital Systems FSMs 9/11/2007 Sarah Bird Electrical Engineering and Computer Sciences University of California, Berkeley Slides borrowed from David Culler
More informationPAST EXAM PAPER & MEMO N3 ABOUT THE QUESTION PAPERS:
EKURHULENI TECH COLLEGE. No. 3 Mogale Square, Krugersdorp. Website: www. ekurhulenitech.co.za Email: info@ekurhulenitech.co.za TEL: 011 040 7343 CELL: 073 770 3028/060 715 4529 PAST EXAM PAPER & MEMO N3
More informationHold Time Illustrations
Hold Time Illustrations EE213-L09-Sequential Logic.1 Pingqiang, ShanghaiTech, 2018 Hold Time Illustrations EE213-L09-Sequential Logic.2 Pingqiang, ShanghaiTech, 2018 Hold Time Illustrations EE213-L09-Sequential
More informationExperiment 9 Sequential Circuits
Introduction to Counters Experiment 9 Sequential Circuits The aim of this experiment is to familiarize you, frst with the basic sequential circuit device called a fip fop, and then, with the design and
More informationS.Y. Diploma : Sem. III [CO/CM/IF/CD/CW] Digital Techniques
S.Y. Diploma : Sem. III [CO/CM/IF/CD/CW] Digital Techniques Time: 3 Hrs.] Prelim Question Paper Solution [Marks : 100 Q.1(a) Attempt any SIX of the following : [12] Q.1(a) (i) Derive AND gate and OR gate
More informationSynchronous Sequential Logic. Chapter 5
Synchronous Sequential Logic Chapter 5 Other Flip Flops D flip flops requires smallest number of gates. Thus, they are commonly used Other flip flops are JK flip flops T flip flops
More informationChapter 3. Chapter 3 :: Topics. Introduction. Sequential Circuits
Chapter 3 Chapter 3 :: Topics igital esign and Computer Architecture, 2 nd Edition avid Money Harris and Sarah L. Harris Introduction Latches and Flip Flops Synchronous Logic esign Finite State Machines
More informationSequential Logic Design: Controllers
Sequential Logic Design: Controllers Controller Design, Flip Flop Timing Copyright (c) 2012 Sean Key Standard Controller Architecture Controller A circuit that implements a FSM is referred to as a controller
More informationDigital Integrated Circuits A Design Perspective
Digital Integrated Circuits A Design Perspective Jan M. Rabaey Anantha Chandrakasan Borivoje Nikolic Designing Sequential Logic Circuits November 2002 Sequential Logic Inputs Current State COMBINATIONAL
More informationCprE 281: Digital Logic
CprE 281: Digital Logic Instructor: Alexander Stoytchev http://www.ece.iastate.edu/~alexs/classes/ Synchronous Sequential Circuits Basic Design Steps CprE 281: Digital Logic Iowa State University, Ames,
More information