Chapter 7 Sequential Logic

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1 Chapter 7 Sequential Logic SKEE2263 Digital Systems Mun im/ismahani/izam {munim@utm.my,e-izam@utm.my,ismahani@fke.utm.my} March 28, 2016

2 Table of Contents 1 Intro 2 Bistable Circuits 3 FF Characteristics 4 FF Excitation

3 Classes of Digital Circuits Digital Circuits Combinational Sequential Asynchronous Synchronous

4 Sequential vs Combinational Combinational: Output = f(present Input) Memoryless Sequential: Output = f(present Input, Past Input) Uses latches/flip-flop as memory May have clock input (synchronous) or not (asynchronous)

5 Clocks Asynchronous sequential circuits have no clock input Inputs Combinational logic Outputs Inputs Combinational logic Outputs Memory elements Memory elements Clock

6 Clock Parts Clock period Clock width Rising edge Falling edge

7 SR Latch: Gate Level Bistable circuits: stable in state 0 or 1 Simplest bistable is SR latch R S

8 SR Latch: Logic Symbol, Characteristic Table S R S R + + Action 0 0 No change Reset Set Forbidden

9 SR Latch: Timing Diagram S R Unknown values Set Reset Set Illegal inputs Both outputs LOW

10 S R Latch: Gate Level, Characteristic Table S R S R + + Action Forbidden Set Reset 1 1 No change

11 Gated SR Latch: Logic Symbol, Characteristic Table S EN R EN S R + Action 0 No change No change Reset Set Forbidden

12 Gated SR Latch: Timing Diagram EN S R Set Reset

13 Gated D Latch: Logic Symbol, Characteristic Table D EN EN D + Action 0 Storage state Transparent mode Transparent mode

14 Gated D Latch: Timing Diagram EN D

15 D Flip-Flop: Logic Symbol, Characteristic Table D Clk D + Action 0 No change 1 No change 0 0 Reset 1 1 Set

16 JK Flip-Flop: Logic Symbol, Characteristic Table Clk J K + Action J K 0 No change 1 No change 0 0 No change Reset Set 1 1 Toggle

17 T Flip-Flop: Logic Symbol, Characteristic Table T Clk D + Action 0 No change 1 No change 0 No change 1 Toggle

18 FF Timing Parameters Data input Clock t SU t H Flip-flop output t CO

19 FF Timing Parameters Setup time, t SU the minimum time that a flip-flop input must be stable before the clock edge. Hold time, t H the minimum time after the clock edge that a flip-flop input must continue to be in the same stable state. Clock to output delay time, t CO the minimum time after a clock edge to obtain a valid output

20 Setup Time Violation Data input t SU Input violates t SU t H Clock Metastable output A Metastable output B t CO Resolves to new data after t Reverts to old data after t CO CO

21 Causes of Metastability Asynchronous Inputs. DIN D XDATA D DOUT TCLK RCLK Transmitter Receiver Data transfer across clock domains.

22 What Happens During Metastability Stable state 0 Stable state 1 Metastable state

23 Solution for Metastability Asynchronous input D Metastable signal D Synchronous signal Synchronous system CLK Two-stage synchronizer

24 D Flip-Flop Characteristic table: D + Operation 0 0 Reset 1 1 Set Excitation table: Present Next State State Input + D Characteristic Equation: + = D D = 0 State diagram: D = 1 = 0 = 1 D = 0 D = 1

25 T Flip-Flop Characteristic table: T + Operation 0 No change 1 Complement Excitation table: Present Next State State Input + T Characteristic Equation: + = T + T = T T = 0 State diagram: T = 1 = 0 = 1 T = 1 T = 0

26 JK Flip-Flop Characteristic table: J K + Operation 0 0 No change Reset Set 1 1 Complement Excitation table: Present Next State State Inputs + J K Characteristic Equation: + = J + K State diagram: JK=10 or 11 JK=00 or 01 = 0 = 1 JK=01 or 11 JK=00 or 10

27 SR Flip-Flop Characteristic table: S R + Operation 0 0 No change Reset Set 1 1? Undefined Excitation table: Present Next State State Inputs + S R Characteristic Equation: + = S + R SR 1 State diagram: S R = 1 0 S R = 0 0 o r 0 1 = 0 = 1 S R = 0 1 S R = 0 0 o r 1 0

28 Excitation Table Summary + S R D J K T

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