Vidyalankar S.E. Sem. III [ETRX] Digital Circuits and Design Prelim Question Paper Solution

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1 S.E. Sem. III [ETRX] Digital Circuits and Design Prelim uestion Paper Solution. (a) Static Hazard Static hazards have two cases: static and static. static- hazard exists when the output variable should be a logical, but goes to momentarily as a result of a variable changing. static- hazard exists when an output variable should be logically but goes to. (b) Dynamic Hazards nother class of hazards exists where the output changes more than once as a result a single input variable change. --- or a --- change is called a dynamic hazard. Static hazards needed only two different delay paths, dynamic hazards must have three or more different propagation delay data path. This occurs when at three levels of logic are present. D (i/p) Clk S 3 N N 3 R 2 4 N 2 N 4 3/Engg/SE/Pre Pap/23/ETRX/DCD_Soln

2 : S.E. DCD If clk = and D =, than S = and R = Output of N = D. (c) clk In the above diagram assume = = The output is fed to D input. S = and R = The output of NND gate N is: N = and that of NND gate N 2 is : N 2 = Output of N 3 : N 3 = The output changes from to for D = This output is fed back to N 4 NND gate N 4 = = Since = ; D = S = and R = The output of NND gates N = ; N 2 = N 3 = = ; i.e. the output does not change for D = When the output of D flipflop is connected to D input it acts as a toggle switch. Difference between Synchronous and synchronous Counters synchronous Counter Synchronous Counter ) In an synchronous Counter the output of one Flip Flop acts as the clock Input of the next Flip Flop. In a Synchronous Counter all the Flip Flop s are connected to a common clock signal. 2) Speed is High. Speed is Low. 3) Only JK or T Flip Flop can be used to Synchronous Counter can be construct synchronous Counter. designed using JK, RS, T and D Flip Flop. 4) Problem of Glitch arises. Problem of Lockout. 5) Only serial count either up or down is Random and serial counting is possible. possible. 6) Settling time is more. Settling time is less. 7) lso called as serial counter. lso called as Parallel Counter. P 2 3/Engg/SE/Pre Pap/23/ETRX/DCD_Soln

3 Prelim uestion Paper Solution 8). (d) F(F,, R, S) = m (,, 3, 4, 8, 9, 5) D D D 2 D 3 D 4 D 5 D 6 D D (a) For MN Flip-Flop M N n n + J K x x x x x x x x K-map N M x x x x J = MN O D D 2 D 3 D 4 D 5 D 6 D 7 8 : MUX S 2 S S B C D N M x x x x M J K = MN Y N K Conversion Logic MN Flip Flop 3/Engg/SE/Pre Pap/23/ETRX/DCD_Soln 3

4 : S.E. DCD 2. (b) K-map : Y = B C C D = B C C D C(B B) = B + + C + D + C [ B = + B and + = ] = ( + B + D + C) + C = + C Implementation using NND gates only : The minimized expression is Y = + C = C = C 3. (a) Mealy Model In the case of a Mealy model, the next state is a function of the present state and the present inputs. Its output is also a function of the present state and the present inputs. In general, the next state and the output of a Mealy model are uniquely defined by Next State = F (Present state, inputs) Outputs = F 2 (Present state, inputs) State diagram : State map : input states q q q q q q q q 4 3/Engg/SE/Pre Pap/23/ETRX/DCD_Soln

5 3. (b) Prelim uestion Paper Solution Master Slave JK Flip Flop : ) Figure shows the master slave JK flip flop. 2) It is a combination of a clocked JK latch and clocked SR latch. 3) The clocked JK latch as the master and the clocked SR latch acts as the slave. 4) Master is positive level triggered. But due to the presence of the inverter in the clock line, the slave will respond to the negative level. 5) Hence when the clock = (low level) the slave is active and the master is inactive. Fig. : Master slave JK FF 6) Table gives truth table of master slave JK flip flop. Table : Truth table of master slave JK FF Case Inputs Outputs Remark CLK J K n+ n+ I n n No change II () n n No change III () Reset IV () Set V () n n Toggle Operation : We will discuss the operation of the master slave JK FF with reference to its truth table. We must always remember one important thing that in the positive half cycle of the clock, the master is active and in the negative half cycle, the slave is active. This is shown in figure 2. Fig. 2 3/Engg/SE/Pre Pap/23/ETRX/DCD_Soln 5

6 : S.E. DCD Case I : Clock = x, J = K = i) For clock =, the master is active, slave inactive. s J = K =. Outputs of master i.e. and will not change. Hence the S and R inputs to the slave will remain unchanged. ii) s soon as clock =, the slave becomes active and master is inactive. But since the S and R inputs have not changed, the slave outputs will also remain unchanged. The outputs will no change if J = K = Case II : Clock =, J = K = This condition has been already discussed in case I. Case III: Clock =, J = and K = Clock = : Master active, slave inactive. Outputs of the master become = and =. That means S = and R = Clock = : Slave active, master inactive. Outputs of the slave become = and = gain if clock = : Master active, slave inactive. Even with the changed outputs = and = fed back to master, its output will = and =. That means S = and R =. Hence with clock = and slave becoming active, the outputs of slave will remain = and =. Thus we get a stable output from the Master slave. Case IV : CLK =, J =, K = Clock = : Master active, slave inactive. Outputs of master become = and = i.e. S =, R =. Clock = : Master inactive, slave active. Outputs of slave become = and =. gain if clock = then it can be shown that the outputs of the slave are stabilized to = and =. 6 3/Engg/SE/Pre Pap/23/ETRX/DCD_Soln

7 Prelim uestion Paper Solution Case V : CLK =, J =, K = Clock J K Master output or S Slave output or R Slave output Fig. 3 : Waveforms of master slave JK flip flop Clock = : Master active, slave inactive. Outputs of master will toggle. So S and R also will be inverted. Clock = : Master inactive, slave active. Outputs of the slave will toggle. These changed output are returned back to the master inputs. But since clock =, the master is still inactive. So it does not respond to these changed outputs. This avoids the multiple toggling which leads to the race around condition. Thus the master slave flip flop will avoid the rave around condition. The waveforms for the master slave flipflop are shown in figure 3. Observations from the waveforms : We can make the following important observations from the waveforms of the master slave JK FF. The slave always follows the master, after a delay of half cycle clock period. The multiple toggling or the race around condition is successfully avoided. 3/Engg/SE/Pre Pap/23/ETRX/DCD_Soln 7

8 : S.E. DCD 4. (a) Characteristic equation of D Flip-flop n+ = D* * = D * = D = + 2 [ * represents the next state] 2 * = D 2 = X. 2 Z = + 2 Previous Next State Next State State (X = ) (X = ) Output (Z) 2 * 2 * * 2 * X = X = Replacing the above states with =, B =, C =, D = Previous Next State Output (Z) State X = X = X = X = C D B C C C B D C C 4. (b) (i) F(, B, C, D) = M(, 6, 7, 8, 2, 3, 4, 5) Here M max terms i.e. whose outputs is To obtain SOP (Sum of Products), we would need minterms F(, B, C, D) = m(, 2, 3, 4, 5, 9,, ) Truth table B C D Y D, K-map simplification CD B Y = CD CD C, D CD Y CD CD 8 3/Engg/SE/Pre Pap/23/ETRX/DCD_Soln

9 To implement is using only NND gates. Y = CD C = CD CD = CDCD Prelim uestion Paper Solution B C duality theorem B C D CD CD (ii) VHDL features VHDL has powerful constructs VHDL language supports hierarchy (i.e modelled using a set of interconnected components) VHDL is not case sensitive VHDL supports both synchronous and asynchronous timing models. Concurrency timing and clocking can be modeled using VHDL VHDL is target independent VHDL supports design library VHDL has flexible design methodologies i.e. TOP DOWN, BOTTOM UP, MIXED The logical behavior and timing behavior of the design can be modeled using VHDL. VHDL is not technology specific i.e. VHDL is not dependent on the specific manufacturer i.e. XILINX or LTTICE. VHDL s technology specific feature allows to specify components from various vendors VHDL also allows the user to specify his own data type and component. Y 3/Engg/SE/Pre Pap/23/ETRX/DCD_Soln 9

10 : S.E. DCD 5. (a) F (, B, C, D) = m (,, 3, 5, 7, 9,, 4,) + d (2, 4). Groups 2 3 Minterms Binary representation Groups Minterms Binary representation Groups Minterms Binary representation Collect prime implicants. (4 in table (a) is not considered as it X) Y = BD D Prepare in the PI table PI Decimal No. Minterms BD, 3, 9, X X X X D, 5, 3, 7 X X X X 2, 3 X X Y = D BD 3/Engg/SE/Pre Pap/23/ETRX/DCD_Soln

11 Prelim uestion Paper Solution 5. (b) ) state Diagram = 5 states to ) No. of statas n = 5 N < N = 2 m 5 < 2 m M = 3 3) Design of vesat circuit Truth Table is N = 2 m = 2 3 = 8 But n = 5 C B Y o/p CLK IN T T B B T C C Y = CLR CLR CLR Y Reset logic K map 4) s synchronous counter, assumption was made that propagation delay through FF and reset circuit is sec. But practically this situation does not exist, therefore glitch occurs. Let s consider propagation delay of reset logic. For analysis let s consider example states are,, 2. Redraw the wave forms considering propagation delay of reset CLK. B 3 2 Y CC B C C 3/Engg/SE/Pre Pap/23/ETRX/DCD_Soln

12 : S.E. DCD Working : Refer Fig. ( = B = B) ) Initially all FFs are reset. B = Y = 2) When st CLK edge hits, will toggle B =, Y = 3) t 2 nd CLK edge, will toggle from (negative edge), B also toggles B = Y = 4) When 3 rd CLK edge hits, will toggle from (positive edge), B is unchanged. B = Reset circuit is designed in such a way that, hen occurs Y =. but appearing of logic at NND input, getting settled, then propagate through NND and appear at output, then resetting the FF will take some time in sec. During this period B =. This condition is invalid condition and produces unwanted short duration pulse called glitch. 5) In asynchronous counter mainly two problems were present, glitch and delay in counter. To avoid this, synchronous counter came into picture. Synchronous counter is now most widely used. Generalized block schematic of synchronous counter is shown in Fig. Observation from block schematic : () CLK pin of all FFs are tied together, so that FF changes output in synchronism. Fig. : Block schematic of synchronous counter. 2 3/Engg/SE/Pre Pap/23/ETRX/DCD_Soln

13 Prelim uestion Paper Solution (2) Output given to combinational logic circuit. This circuit is designed in such a way that G G B G C generate from it, applies proper logic to input of FF, so that we get correct next state. (3) O/p depends upon previous input of FF, when CLK edge hits. Basically we are going to design synchronous counter using, () T FF (2) D FF (3) JK FF (also master slave) 6. (a) Step : Draw the state diagram : Fig. Step 2 : Write the circuit excitation table : Step 3 : K-maps and simplification : Fig. (a) 3/Engg/SE/Pre Pap/23/ETRX/DCD_Soln 3

14 : S.E. DCD 6. (b) Fig. (b) Fig. (c) Fig. (d) Operation : Case I : =, B = For this case works in normal mode and transistors 2 and 3 both will be OFF and voltage at V x point will be V CC and this is sufficient to turn ON 4 and D (because to turn ON 4 and D voltage V x = V B4 = V BE4 + V D = =.4 V) so 4 and D both will be ON when output V. 4 3/Engg/SE/Pre Pap/23/ETRX/DCD_Soln

15 Prelim uestion Paper Solution V = V x V BE4 V D = V CC V BE4 V D = = 3.6 V V = logic Case II : =, B = same as case (I) Case III : =, B = Case IV : =, B = For this case, transistor works in inverse mode due to this 2 and 3 both will be ON and voltage at V x = V CE2 + V CE2 (sat) + V BE3 = =.9 V This voltage is not sufficient to turn ON 4 and D because it is less than.4 V. So 4 and D both will be OFF and output V = V CE3 (sat) =.2 V = logic. Circuit diagram : B V B R B V 2 V B2 Multi emitter i/p stage B V BE2 V x V CC R C2 R E2 Phase Splitter B Y = B V B4 V BE4 D V BE3 I C3 R C3 4 3 Totem pole o/p stage Y = B V D o/p 3/Engg/SE/Pre Pap/23/ETRX/DCD_Soln 5

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