Digital Design. Sequential Logic

Transcription

1 Principles Of igital esign Chapter 6 Sequential Logic

2 Chapter preview Boolean algebra 3 Logic gates and flip-flops 3 Finite-state machine 6 Logic design techniques 4 Sequential design techniques 6 Binary system and data representation 2 Combinational components 5 Storage components 7 Generalized finite-state machines 8 Register-transfer design 8 Processor components 9 Copyright by aniel. Gajski 2

3 Sequential components Sequential components contain memory elements The output values of sequential components depend on the input values and the values stored in the memory elements The values in the memory elements define the state of sequential components Example : Ring counter that starts the answering machine after 4 rings Sequential components can be ()asynchronous or (2) synchronous Asynchronous sequential components change their state and output values as a response to change in input values Synchronous sequential components change their state and output values at fixed points of time defined by the clock signal Copyright by aniel. Gajski 3

4 Clock signal Clock period Clock width Rising edge Falling edge Clock period ( measured in micro or nanoseconds ) is the time between successive transitions in the same direction Clock frequency ( measured in MHz or GHz ) is the reciprocal of clock period Clock width is the time interval during which clock is equal to uty cycle is the ratio of the clock width and clock period Clock signal is active high if the changes occur at the rising edge or during the clock width Clock signal is active low otherwise Copyright by aniel. Gajski 4

5 SR-latch ( NOR implementation ) SR-latch has two states: () set state (Q=) and (2) reset state (Q=) S Q S R Q Q (next) Q (next) (hold) (hold) (reset) R Logic schematic Q Truth table (set) (?) S R Q Undefined.4 Q Undefined Copyright by aniel. Gajski t t t 2 t 3 t 4 t 5 t 6 Timing diagram 5 t 7 t 8 t 9 t

6 SR-latch ( NAN implementation ) S.4 Q S R Q Q (next) Q (next) (?) (set) (reset) R.4 Q (hold) (hold) Logic schematic Truth table S R Q Undefined Q Undefined t t t 2 t 3 t 4 t 5 t 6 t 7 t 8 t 9 t Copyright by aniel. Gajski Timing diagram 6

7 Gated SR-latch S C R Q Q Graphic symbol Control signal C activates the latch R C S Logic schematic Q Q C S R Q Q(next) NA (inactive) (inactive) (hold) (hold) (reset) (set) (?) Truth table reset state set state reset state C S R Q t t t 2 t 3 t 4 t 5 t 6 t 7 t 8 t 9 t t t 2 t 3 Copyright by aniel. Gajski Timing diagram 7 t setup t hold

8 Gated -latch C Q Q C Q Q C Q Q(next) Graphic symbol Logic schematic Truth table C reset state set state reset state Q Setup time is minimum time inputs must be stable before C Hold time is minimum time inputs must be stable after C Q follows while C is asserted as long as satisfies setup and hold time restrictions Copyright by aniel. Gajski t t t 2 t 3 t 4 t 5 t 6 t 7 t 8 t 9 t setup t hold t setup t hold t setup t hold Timing diagram 8

9 Flip Flops Latches are level-sensitive since they respond to input changes during clock width. Latches are difficult to work with for this reason. Flip-Flops respond to input changes only during the change in clock signal. They are easy to work with though more expensive than latches. Two styles of flip-flops are available. () master-slave (MS) (2) edge-triggered (ET) Copyright by aniel. Gajski 9

10 Erroneous shifting with -latches Erroneous operation is possible with level-sensitive latches Q 4./3. C Q 2 4./3. C Q 3 4./3. C Y Logic schematic Q Q Q t 2 t t t 3 t 4 t 5 t 7 Timing diagram Note: Low-to-high delay is 4.ns. High-to-low delay is 3.ns. t 6 Copyright by aniel. Gajski

11 Master-slave slave flip-flop flop In a MS flip-flop is sampled and stored at the rising edge (low-to-high) of the signal Master latch Q m 4./3. C Slave latch Q s 4./3. C Q Logic schematic Q m Q s t t 3 t 4 t 5 t 7 t 8 t 9 t t 2 t 6 Copyright by aniel. Gajski Timing diagram

12 Shifting with master-slave slave flip-flops flops Master-slave flip-flops Q n 4./3. C Q s 4./3. C Master-slave flip-flops Q 2n 4./3. C Q 2s 4./3. C Master-slave flip-flops Q 3n 4./3. C Q 3s 4./3. C Y Logic schematic Q m Q s Q 2m Q 2s Q 3m Q 3s 4. Copyright by aniel. Gajski t t t 2 t 3 t 4 t 5 t 6 t 7 Timing diagram 2

13 Edge-triggered flip-flop flop Set latch A S R Output latch B Reset latch Logic schematic Q Q A S R.4.4 B Q Copyright by aniel. Gajski t t t 2 t 3 t 5 t 6 Timing diagram 3 t 4 t 7 t 8 t 9

14 Flip-flop types Flip-flop name Flip-flop symbol Characteristic table Characteristic equation Excitation table SR S Q R Q S R Q(next) Q NA Q(next)=S+R Q SR= Q Q(next) S R JK J Q K Q J K Q(next) Q Q Q(next)=JQ +K Q Q Q(next) J K Q Q Q(next) Q(next)= Q Q(next) T T Q Q T Q(next) Q Q Q(next)=TQ +T Q Q Q(next) T Note: For master-slave and edge-triggered flip-flops data inputs must satisfy Copyright by aniel. Gajski set-up and hold time constraints. 4

15 State diagrams for different flip-flops flops Flip-flop name State diagram SR S,R=, S,R=, Q= Q= S,R=, S,R=, J,K=, or, J,K=, J,K=, JK Q= Q= J,K=, or, = = Q= Q= = T T= = T= Q= Q= T= T= Copyright by aniel. Gajski 5

16 A latch and flip-flop flop with asynchronous inputs CLR C Q Q PRS Q C Q CLR PRS latch Graphic symbol PRS Set latch A S Q PRS Q R Q C Q CLR B Output latch Graphic symbol CLR Reset latch Copyright by aniel. Gajski Edge-triggered flip-flop 6

17 Graphic symbols for flip-flops flops with asynchronous inputs Flip-flop name SR JK Flip-flop symbol Preset S Q R Q Clear Preset J Q K Q Clear Preset Q Q Clear Preset T T Q Q Clear Copyright by aniel. Gajski 7

18 Analysis of sequential logic Excitation equations are Boolean expressions of the flip-flop inputs. Next-state equations are Boolean expressions representing the next value of the flip- flop outputs. Next-state table ( similar to next-state equations ) gives the next value of flip-flop outputs for each input value and state of flip-flops. Analysis of a sequential circuit is a procedure that produces the nextstate table, state diagram and timing diagram from the logic schematic of the circuit. The analysis gives the answer to the following questions: (a) What is the next state? (b) What is the output? (c) What is the function of the circuit? Copyright by aniel. Gajski 8

19 Analysis of a sequential circuit Example: Modulo-4 4 counter Problem: erive the state table and state diagram for the sequential ential circuit represented by the schematic below. Cnt Q Q Cnt= Q Q = Cnt= Q Q = Cnt= Logic schematic Q Q = Cnt Q = Cnt Q + Cnt Q Cnt= Cnt= Q Q = Cnt= State diagram Cnt= Q Q = = Cnt Q + Cnt Q Q + Cnt Q Q Clock cycle Clock cycle 2 Clock cycle 3 Clock cycle 4 Excitation equation Q (next) = = Cnt Q + Cnt Q Q (next) = = Cnt Q + Cnt Q Q + Cnt Q Q Next-state equation Cnt Cnt= PRESENT STATE Q Q NET STATE Q (next) Q (next) Q Copyright by aniel. Gajski Cnt= State table Cnt= 9 Q t t t 2 t 3 t 4 t 5 Timing diagram

20 Analysis of a Moore-type modulo-4 4 counter Example: Moore-type modulo-4 4 counter Problem: erive the state and output tables and the state diagram for the sequential circuit given by the schematic below. = Cnt Q = Cnt Q + Cnt Q = Cnt Q + Cnt Q Q + Cnt Q Q Excitation equation Q (next) = = Cnt Q + Cnt Q Q (next) = = Cnt Q + Cnt Q Q + Cnt Q Q Y = Q Q Next-state and output equation Logic schematic PRESENT STATE NET STATE OUTPUTS Q Q Q (next) Q (next) Y Cnt= Cnt= Copyright by aniel. Gajski State and output table 2

21 Analysis of a Moore type modulo-4 4 counter Cnt= Cnt= Q Q = Y= Cnt= Q Q = Y= Cnt= Cnt= Cnt= Cnt= Q Q = Y= Cnt= Q Q = Y= State diagram Cnt Q Q Y t t t 2 t 3 t 4 Timing diagram t 5 Copyright by aniel. Gajski 2

22 Analysis of a Mealy-type modulo-4 4 counter Example: Mealy-type modulo-4 4 counter Problem: erive the state/output table and the state diagram for the sequential ential Cnt circuit given below. Q Y = Cnt Q = Cnt Q + Cnt Q Q = Cnt Q + Cnt Q Q + Cnt Q Q Excitation equation Q (next) = = Cnt Q + Cnt Q Q Q (next) = = Cnt Q + Cnt Q Q + Cnt Q Q Q Y = Cnt Q Q Logic schematic Copyright by aniel. Gajski Next-state and output equation PRESENT STATE Q Q NET STATE /OUTPUTS Q (next) Q (next)/y Cnt= Cnt= / / / / / / / / State and output table 22

23 Analysis of a Mealy-type modulo-4 4 counter Cnt=/Y= Q Q = Cnt=/Y= Q Q = Cnt=/Y= Cnt=/Y= Cnt=/Y= Cnt=/Y= Q Q = Cnt=/Y= Q Q = Cnt=/Y= State diagram Clock cycle Clock cycle 2 Clock cycle 3 Clock cycle 4 Cnt Q Q Y Copyright by aniel. Gajski t t t 2 t 3 t 4 t 5 Timing diagram 23

24 Analysis procedure for sequential circuits Logic schematic erive excitation equations erive next-state and output equations 2 Generate next-state and output tables 3 Generate state diagram 4 evelop timing diagram 5 Simulate logic schematic 6 Copyright by aniel. Gajski 24

25 Finite-state machine model I A Q,, Q m Y O A k Y n The finite state machine ( FSM ) can be defined abstractly as the quintuple < S, I, O, f, h> where S, I, and O represent a set of states, set of inputs and a set of outputs, respectively, and f and h represent the next-state and the output functions. f : S x I S h : S x I O ( Mealy-type ) S O ( Moore-type ) S = Q x Q 2 x x Q m, I = A x A 2 x x A k, O = Y x Y 2 x x Y n, Copyright by aniel. Gajski 25

26 FSM model of modulo-4 4 counter ( Moore ) Cnt Q Q Copyright by aniel. Gajski Logic schematic Q Q = Cnt Q = Cnt Q + Cnt Q = Cnt Q + Cnt Q Q + Cnt Q Q Excitation equation Q (next) = = Cnt Q + Cnt Q Q (next) = = Cnt Q + Cnt Q Q + Cnt Q Q PRESENT STATE Q Q Next-state equation NET STATE Q (next) Q (next) Cnt= State table Cnt= 26 PRESENT STATE S S S 2 S 3 NET STATE ( SxI S ) i i S S S S 2 S 2 S 3 S 3 S OUTPUTS (S O) FSM model of modulo-4 counter Note: Output is dependent only on the state of FSM. O O O O

27 FSM model of modulo-4 4 counter ( Mealy ) Cnt Q Y Q Q Q PRESENT STATE NET STATE(SxI S)/ OUTPUT(SxI O) i i Logic schematic = Cnt Q = Cnt Q + Cnt Q = Cnt Q + Cnt Q Q + Cnt Q Q Excitation equation Q (next) = = Cnt Q + Cnt Q Q (next) = = Cnt Q + Cnt Q Q + Cnt Q Q Y = Cnt Q Q Next-state and output equations PRESENT STATE Q Q Copyright by aniel. Gajski NET STATE /OUTPUTS Q (next) Q (next)/y Cnt= / / / / State and output table Cnt= / / / / 27 S S S 2 S 3 S /O S /O S /O S 2 /O S 2 /O S 3 /O S 3 /O S /O FSM model of modulo-4 counter Note: Output is dependent on the state and the input of the FSM.

28 Finite-state state-machine implementations State-based Input-based Copyright by aniel. Gajski 28

29 Synthesis procedure for sequential logic esign description or timing diagram evelop state diagram Generate next-state and output tables Minimize states Encode inputs, states, outputs erive next-state and output equations Choose memory elements erive excitation equations Optimize logic implementation erive logic schematic and timing diagrams Simulate logic schematic Verify functionality and timing Copyright by aniel. Gajski 29

30 State diagram for a modulo-3 3 up/down counter Example: Modulo-3 3 up-down counter Problem: erive the state diagram for an up-down, modulo-3 3 counter. The counter has two inputs: count enable (C) and count direction (). When C=, the counter will count in the direction specified by, and it will stop counting when C=. the counter will count up when = and down when =. The counter has one output Y which will be asserted when the counter reaches 2 while counting up, or when it reaches s while counting down. C Modulo-3 up/down counter Counter symbol Y Partial state diagram (up and down counting) C= C= C= C= C= u u u 2 C= C= C= C= C= C= C= C= C= d d d 2 Copyright by aniel. Gajski Partial state diagram (changing direction) 3 C= C= C= C= Final state diagram

31 State minimization State minimization reduces the number of states, and therefore, number of flip-flops needed to implemented the circuit. State minimization is based on the concept of behavioral equivalence which states that two FSM are equivalent if they produce the same sequence of output symbols for every sequence of input symbols. More formally, two states, s j and s k in an FSM are said to be equivalent, s j s k, iff the following two conditions are true. Condition : Both states s j and s k produce the same output symbol for every input symbol i: that is, h (s j,i) = h (s k,i); Condition 2: Both states have equivalent next sates for every input symbol i : that is, h (s j,i) = h (s k,i); Minimization procedure:. partition states into equivalence classes 2. construct new FSM with one state for each equivalence class Copyright by aniel. Gajski 3

32 State reduction for modulo-3 3 counter Example: State reduction Problem: erive the minimal-state FSM for the modulo-3 3 counter. PRESENT STATE NET STATE / OUTPUT C= C= C= u u / u / d / 2 u u / u / 2 d / u 2 u 2 / u / d / d d / u / d / 2 d d / u / 2 d / d 2 / u / d / d 2 PRESENT STATE s NET STATE / OUTPUT C= C= C= s / s / s s / s / 2 s 2 / s / s 2 Initial next-state/output table s 2 / s / s / Partition into arrays with the same output Partition into arrays with the same next state C = C = ( u, u, u 2, d, d, d 2 ) G = (u, d ) G = (u, d ) G 2 = (u 2, d 2 ) G G G G G 2 G 2 G G G 2 G 2 G G G 2 G 2 G G G G Partitioning into equivalence classes Output values Next states Final next-state/output table Copyright by aniel. Gajski 32

33 State reduction with implication table Example: State reductions with implication table. Problem: Find the minimal number of states for the FSM specified by the table t below. s s 2 s 3 s 4 s 5 <s 3,s 4 > <s 2,s 6 > <s,s 4 > s 6 s s s 2 s 3 s 4 s 5 Implication table PRESENT STATE NET STATE C= C= C= u u / u / d / 2 u u / u / 2 d / u 2 u 2 / u / d / d d / u / d / 2 d d / 2 u / 2 d / d 2 / u / d / d 2 Next-state and output table u u 2 d d <u,d 2 > Equivalence classes: <u, d > <u > <d > <u 2, d 2 > d 2 u u u 2 d d Implication table for the table above Copyright by aniel. Gajski 33

34 State encoding ENCOING NUMBER s s s 2 s 3 The cost and delay of FSM implementation depends on encoding of symbolic states. For example, four states can be encoded in 4!=24 different ways. There are more than n! different encodings for n states. Exploration of all encodings is impossible Thus, we use heuristics. Three different heuristics: minimum-bit change prioritized adjacency one-hot encoding Copyright by aniel. Gajski 24 encodings of four states 34

35 Minimum-bit change Minimum-bit change strategy assigns codes to states so that the total number of bit changes for all state transitions is minimized. In other words, if every arc in the state diagram has a weight that is equal to the number of bits by which the source and destination encodings differ, then the optimal encoding would be the one that minimizes the sum of all these weights. Example: Two different encodings for 2-bit binary counter. s Straightforward encoding Minimum-bit-change encoding Copyright by aniel. Gajski 35

36 Prioritized adjacency Prioritized adjacency strategy assigns adjacent encodings to all states with common source, common destination or common output. Highest priority is given to states with the same next state since the same next-state code will appear in adjacent entries in the Karnaugh map. The second priority is given to the next states of the same state since they also may appear adjacent in the Karnaugh map. The third priority is given to states that have the same output value for the same input value since they may be adjacent in the output map. Example: encoding based on prioritized adjacency. Copyright by aniel. Gajski Initial state diagram Priority : (s, s 2 ) Priority 2: (s, s 2 ) Priority : (s, s ), (s 2, s 3 ) Adjacency priorities 36 /, / / / / s / Possible encoding

37 Hot-one one encoding Hot-one encoding is a redundant encoding with one flip-flop per state having value and others having value. The flip-flop with value reminds one of a hot-potato being passed from one hand to another. Hot-one encoding is too expensive for FSMs with large number of states. It is used only in small FSMs. Copyright by aniel. Gajski 37

38 Encoding example Example: State encodings for modulo-3 3 counter. Problem: Given the up/down, modulo-3 3 counter which was specified by the minimal next-state/output table in Figure 6.8 derive the encoding that will minimize the cost and delay of the counter logic. STATE ENCOING A ENCOING B ENCOING C Q Q Q Q Q 2 Q Q S S S 2 Possible state encodings for modulo-3 counter Encoding A = Minimum-bit change/prioritized adjacency Encoding B = Simplified output logic Encoding C = Hot-one encoding Copyright by aniel. Gajski 38

39 Cost/delay estimation for encoding A C Q Q Q Q Q (next), Q (next) Next-state map Q (next) = Q C +Q C +Q Q C Q (next) = Q C +Q C+Q Q C Y= Q C +Q Q C Excitation and output equations C Y Output map.4 Q (next).4 Q (next) Y Cost (Q ) = 24 elay (Q ) = Cost (Q ) = 24 elay (Q ) = 4. Cost and delay estimation Cost (Y) = 8 elay (Y) = 3.6 Copyright by aniel. Gajski Total cost = 66 Max. input delay = 4.ns, Max. output delay = 3.6ns 39

40 Cost/delay estimation for encoding B C Q Q Q Q Q (next), Q (next) Next-state map Q (next) = Q C +Q C+Q Q C Q (next) = Q C +Q C +Q Q C Y= Q C+Q C Excitation and output equations C Y Output map Cost (Q ) = 24 elay (Q ) = 4. Q (next) Q (next).8 Cost (Q ) = 24 elay (Q ) = 4. Cost and delay estimation.8 Y.4.8 Cost (Y) = 6 elay (Y) = 3.2 Copyright by aniel. Gajski Total cost = 64 Max. input delay = 4.ns, Max. output delay = 3.2ns 4

41 Cost/delay estimation for encoding C Q 2 Q Q C Q 2 (next),q (next),q (next) Next-state map Q 2 Q Q Q 2 (next) = Q 2 C +Q C+Q C Q (next) = Q C +Q 2 C+Q C Q (next) = Q C +Q 2 C +Q C Y= Q C+Q 2 C Excitation and output equations Q 2 (next) Q (next) Q (next) C Y.8.8 Output map Y.4 Cost (Q ) = Cost (Q ) = Cost (Q 2 ) = 22 elay (Q ) = elay (Q ) = elay (Q ) = 3.6 Cost and delay estimation Cost (Y) = 6 elay (Y) = 3.2 Copyright by aniel. Gajski Total cost = 82 Max. input delay = 3.6ns, Max. output delay = 3.2ns 4

42 Choice of memory elements Select the type of flip-flop from:, SR, JK, T SR and JK reduce the cost of input logic; but require twice as many connections. and T require single connection per flip-flop. T is suitable for counting functions since it changes output value when its input is. Copyright by aniel. Gajski 42

43 Modulo-3 3 counter implementation with different flip-flops flops Example: Flip-flop selection. Problem: Given the modulo-3 3 counter with Encoding A, as specified below, select the type of flip-flop flop that will minimize the cost and/or delay of input logic. C Q Q Q (next), Q (next) Q (present) Q (next)) S R J K T Next-state table for encoding A C Q Q S,R,S,R Flip-flop excitation table S = Q C +Q Q C (cost = 8, delay = 3.6) R = Q C = (Q +C ) (cost = 4, delay =.4) S = Q C+Q Q C (cost = 8, delay = 3.6) R = Q C = (Q +C ) (cost = 4, delay =.4) Copyright by aniel. Gajski Implementation with SR flip-flops 43

44 Modulo-3 3 counter with different flip-flops flops C Q Q C Q Q S,R,S,R S = Q C +Q Q C (cost = 8, delay = 3.6) J,K,J,K J = Q C +Q C = (C +Q +Q ) (cost = 2, delay = 2.4) R = Q C = (Q +C ) (cost = 4, delay =.4) K = C (cost =, delay = ) S J = Q C+Q C = (C +Q +Q ) (cost = 2, delay = 2.4) = Q C+Q Q C (cost = 8, delay = 3.6) R = Q C = (Q +C ) (cost = 4, delay =.4) K = C (cost =, delay = ) C Q Q T,T Implementation with SR flip-flops Implementation with JK flip-flops Q Q C T = Q C+Q C+Q C (cost = 22, delay = 3.6) = Q C +Q C +Q Q C (cost = 24, delay = 4.) T = Q C+Q C+Q C (cost = 22, delay = 3.6) = Q C +Q C+Q Q C (cost = 24, delay = 4.),, Implementation with T flip-flops Implementation with flip-flops Copyright by aniel. Gajski 44

45 C Optimization and timing Y Input-output delays C, to to Y C, to Y to C Q Logic schematic elay table Q Y t t Copyright by aniel. Gajski t 2 t 3 Timing diagram 45 t 4 t 5 t 6

46 Chapter Summary We introduced memory elements Latches (asynchronous) Flip-flops (synchronous) We presented several ways to describe memory elements Characteristic tables Characteristic equations Static diagrams Timing diagrams We described procedures for sequential logic Analysis Synthesis with FSM capture state minimization state encoding optimization and timing We defined the concept of a FSM Copyright by aniel. Gajski 46