ELEC Digital Logic Circuits Fall 2014 Sequential Circuits (Chapter 6) Finite State Machines (Ch. 7-10)

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1 ELEC Digital Logic Circuits Fall 2014 Sequential Circuits (Chapter 6) Finite State Machines (Ch. 7-10) Vishwani D. Agrawal James J. Danaher Professor Department of Electrical and Computer Engineering Auburn University, Auburn, AL Fall 2014, Nov ELEC Lecture 7 1

2 Combinational vs. Sequential Combinational circuit: Output is a function of input No memory Example: parallel adder Sequential circuit: Output is a function of input and something else stored in the circuit Internal memory Example: serial adder Fall 2014, Nov ELEC Lecture 7 2

3 Parallel and Serial Adders (LSB) (LSB) Four-bit Adder (LSB) (LSB) time One-bit Adder One-bit memory S C time (LSB) 1. Memory initialized to 0 (initial carry = 0) 2. Time synchronization of Inputs, output, and memory (clock) Fall 2014, Nov ELEC Lecture 7 3

4 Another Example of Sequential System Four-year degree program: Student can be in four states (Fr, So, Jr, Sr) One-bit yearly input, 1 (completed) or 0 (in progress) Output = 1 (degree completed), 0 (in progress) State diagram: 0/0 0/0 0/0 0/0 1/0 1/0 1/0 Fr So Jr Sr Initial state 1/1 Fall 2014, Nov ELEC Lecture 7 4

5 State Table or Excitation Table Input Present State Next State Output 0 Fr Fr 0 0 So So 0 0 Jr Jr 0 0 Sr Sr 0 1 Fr So 0 1 So Jr 0 1 Jr Sr 0 1 Sr Sr 1 Initial State: Fr Fall 2014, Nov ELEC Lecture 7 5

6 State Table (Alternative Form) Next state/output Inputs 0 1 Fr Fr/0 So/0 Present state So Jr Sr So/0 Jr/0 Sr/0 Jr/0 Sr/0 Sr/1 Fall 2014, Nov ELEC Lecture 7 6

7 When Is Circuit Not Combinational? When the present input does not completely control output. For a logic circuit without feedback, input uniquely determines the output. Examples of non-combinational (sequential) circuits: Toggling or 1 0 Odd inversions Even inversions Fall 2014, Nov ELEC Lecture 7 7

8 SR Latch: Basic Sequential Circuit Feedback loop with even number of inversions (no oscillation?). Output(s): two sets of logic values from the loop. Input functions: To control loop logic values To set the loop in input control or store state Fall 2014, Nov ELEC Lecture 7 8

9 Adding Inputs to Feedback Loop S R Q Q Fall 2014, Nov ELEC Lecture 7 9

10 NOR Set-Reset (SR) Latch S R Q Q S Q S Q Q R Q R Also drawn as Symbol used in Logic schematics Fall 2014, Nov ELEC Lecture 7 10

11 States of Latch State S R Q Q Set Reset Store 0 0 Prev. Q Prev. Q Illegal Fall 2014, Nov ELEC Lecture 7 11

12 The Set State Loop is broken S = 1 Q = 1 R = 0 Q = 0 Behavior is combinational. Fall 2014, Nov ELEC Lecture 7 12

13 The Reset State S = 0 Q = 0 R = 1 Q = 1 Loop is broken Behavior is combinational. Fall 2014, Nov ELEC Lecture 7 13

14 The Store State S = 0 Q = 1 R = 0 Q = 0 Loop is activated; behavior is sequential. Fall 2014, Nov ELEC Lecture 7 14

15 The Illegal State S = 1 Q = 0 R = 1 Q = 0 Loop is broken in two places and inconsistent values inserted. Fall 2014, Nov ELEC Lecture 7 15

16 Illegal State Cannot Be Stored Assume two gates have equal delays. S = 1 0 Q = R = 1 0 Q = Output oscillates with a period of loop delay. For unequal gate delays, faster gate will settle to 1 and slower gate to 0. This is known as RACE CONDITION. Fall 2014, Nov ELEC Lecture 7 16

17 Excitation Table of SR Latch Excitation inputs Present state Next state S R Q Q* Functional Name of State Store Reset Set Illegal Race Illegal condition Fall 2014, Nov ELEC Lecture 7 17

18 Characteristic Equation for SR Latch Next-state function: Treat illegal states as don t care Minimize using Karnaugh map Characteristic equation, Q* = S + RQ S Φ 1 Q 1 Φ 1 R Fall 2014, Nov ELEC Lecture 7 18

19 State Diagram of SR Latch SR = 0X SR = 10 SR = X0 Q = 0 Q = 1 SR = 01 Fall 2014, Nov ELEC Lecture 7 19

20 Clocked SR Latch S SR-latch Q CK Q R Fall 2014, Nov ELEC Lecture 7 20

21 Clocked Delay Latch or D-Latch D SR-latch Q CK Q Fall 2014, Nov ELEC Lecture 7 21

22 Setup and Hold Times of Latch Signals are synchronized with respect to clock (CK). Operation is level-sensitive: CK = 1 allows data (D) to pass through CK = 0 holds the value of Q, ignores data (D) Setup time is the interval before the clock transition during which data (D) should be stable (not change). This will avoid any possible race condition. Hold time is the interval after the clock transition during which data should not change. This will avoid data from latching incorrectly. Fall 2014, Nov ELEC Lecture 7 22

23 Latch Inputs t p 1 D 0 time t s t h 1 CK 0 time t r Fall 2014, Nov ELEC Lecture 7 23

24 JK-Latch SR-latch J Q K Q Characteristic Equation, Q = J Q* + K Q* Where Q = present state, Q* = previous state Fall 2014, Nov ELEC Lecture 7 24

25 T-Latch (Toggle Latch) J SR-latch Q T K Q Characteristic Equation, Q = T Q* + T Q* Where Q = present state, Q* = previous state Fall 2014, Nov ELEC Lecture 7 25

26 Master-Slave D-Flip-Flop D Master latch Slave latch Q Q CK Fall 2014, Nov ELEC Lecture 7 26

27 Master-Slave D-Flip-Flop Uses two clocked D-latches. Transfers data (D) with one clock period delay. Operation is edge-triggered: Negative edge-triggered, CK = 1 0, Q = D (previous slide) Positive edge-triggered, CK = 0 1, Q = D Fall 2014, Nov ELEC Lecture 7 27

28 Negative-Edge Triggered D-Flip-Flop Clock period, T CK Triggering clock edge Master open Slave closed Setup time Slave open Master closed Hold time D Data can change Data stable Data can change Time Fall 2014, Nov ELEC Lecture 7 28

29 D-Flip-Flop With CLEAR CLR D Master latch Slave latch Q Q CK Fall 2014, Nov ELEC Lecture 7 29

30 D-Flip-Flop With PRESET D Master latch Slave latch Q Q CK PRESET Fall 2014, Nov ELEC Lecture 7 30

31 Symbols for Latch and D-Flip-Flops CK D Q (LATCH) Level sensitive Q (DFF) Pos. Edge Triggered Q (DFF) Neg. Edge Triggered D CK D CK D CK Q Q Q Fall 2014, Nov ELEC Lecture 7 31

32 CLR Register (3-Bit Example) Stores parallel data Parallel input D0 D1 D2 D CLR Q D CLR Q D CLR Q CK CK CK CK Q0 Q1 Q2 Parallel output Fall 2014, Nov ELEC Lecture 7 32

33 Shift Register (3-Bit Example) Stores serial data (parallel output) Delays data (serial output) CLR D Serial input D CLR Q D CLR Q D CLR Q Serial output CK CK CK CK Q0 Q1 Q2 Parallel output Fall 2014, Nov ELEC Lecture 7 33

34 Two Types of Digital Circuits 1. Output depends uniquely on inputs: Contains only logic gates, AND, OR,... No feedback interconnects 2. Output depends on inputs and memory: Contains logic gates, latches and flip-flops May have feedback interconnects Contents of flip-flops define internal state; N flipflops provide 2 N states; finite memory means finite states, hence the name finite state machine (FSM). Clocked memory synchronous FSM No clock asynchronous FSM Fall 2014, Nov ELEC Lecture 7 34

35 Textbook Organization Chapter 6: Sequential devices latches, flipflops. Chapter 7: Modular sequential logic registers, shift registers, counters. Chapter 8: Specification and analysis of FSM. Chapter 9: Synchronous (clocked) FSM design. Chapter 10: Asynchronous (pulse mode) FSM design. Fall 2014, Nov ELEC Lecture 7 35

36 Mealy and Moore FSM Mealy machine: Output is a function of input and the state. Moore machine: Output is a function of the state alone. 1/1 0/1 0/0 1/0 0/1 0/0 S0 S1 S0/1 S1/0 1/0 1/1 Mealy machine Moore machine G. H. Mealy, A Method for Synthesizing Sequential Circuits, Bell Systems Tech. J., vol. 34, pp , September E. F. Moore, Gedanken-Experiments on Sequential Machines, Annals of Mathematical Studies, no. 34, pp ,1956, Princeton Univ. Press, NJ. Fall 2014, Nov ELEC Lecture 7 36

37 Example 8.17: Robot Control A robot moves in straight line, encounters obstacle and turns right or left until path is clear; on successive obstacles right and left turn strategies are used. Define input: One bit X = 0, no obstacle X = 1, an obstacle encountered Define outputs: Two bits to represent three possible actions. Z1, Z2 = 00 no turn Z1, Z2 = 01 turn right by a predetermined angle Z1, Z2 = 10 turn left by a predetermined angle Z1, Z2 = 11 output not used Fall 2014, Nov ELEC Lecture 7 37

38 Example 8.17: Robot Control (Continued... 2) Because turning strategy depends on the action for the previous obstacle, the robot must remember the past. Therefore, we define internal memory states: State A = no obstacle detected, last turn was left State B = obstacle detected, turning right State C = no obstacle detected, last turn was right State D = obstacle detected, turning left Fall 2014, Nov ELEC Lecture 7 38

39 Realization of FSM The general hardware architecture of an FSM, known as Huffman model, consists of: Flip-flops for storing the state. Combinational logic to generate outputs and next state from inputs and present state. Clock to synchronize state changes. Initialization hardware to set the machine in prespecified state. Inputs Present state Combinational logic Next state Outputs Flipflops Clock Clear Fall 2014, Nov ELEC Lecture 7 39

40 Example 8.17: Robot Control (Continued... 3) Construct state diagram. X Z1 Z2 A: no obstacle, last turn was left B: obstacle, turn right C: no obstacle, last turn was right D: obstacle, turn left 0/00 A 1/01 B 1/01 Input: X = 0, no obstacle X = 1, obstacle 0/00 0/00 Outputs: Z1, Z2 = 00, no turn Z1, Z2 = 01, right turn Z1, Z2 = 10, left turn 1/10 D 1/10 C 0/00 Fall 2014, Nov ELEC Lecture 7 40

41 Example 8.17: Robot Control (Continued... 4) Construct state table. 0/00 A X Z1 Z2 1/01 B 1/01 X Present 0 1 state A A/00 B/01 B C/00 B/01 0/00 0/00 C C/00 D/10 1/10 D 1/10 C 0/00 Next state D A/00 D/10 Outputs Z1, Z2 Fall 2014, Nov ELEC Lecture 7 41

42 Example 8.17: Robot Control (Continued... 5) State assignment: Each state is assigned a unique binary code. Need log 2 4 = 2 binary state variables to represent 4 states. Let memory variables be Y1,Y2: A: {Y1,Y2} = 00; B: {Y1,Y2} = 01; C: {Y1,Y2} = 11, D: {Y1,Y2} = 10 X Present 0 1 state A A/00 B/01 X Y1 Y /00 01/01 B C/00 B/ /00 01/01 C C/00 D/ /00 10/10 D A/00 D/ /00 10/10 Fall 2014, Nov ELEC Lecture 7 42

43 Realization of FSM Primary input: X Primary outputs: Present state variables: Z1, Z2 Y1, Y2 Next state variables: Y1*, Y2* Clock Clear X Y1 Combinational logic Y2 Y1* Flipflop Flipflop Y2* Z1 Z2 Fall 2014, Nov ELEC Lecture 7 43

44 Example 8.17: Robot Control (Continued... 6) Construct truth tables for outputs, Z1 and Z2, and excitation variables, Y1 and Y2. X Y1 Y /00 11/00 11/00 00/00 Next State, Y1*, Y2* 01/01 01/01 10/10 10/10 Outputs Z1, Z2 Input Present state Outputs Next state X Y1 Y2 Z1 Z2 Y1* Y2* Fall 2014, Nov ELEC Lecture 7 44

45 Example 8.17: Robot Control (Continued... 7) Synthesize logic functions, Z1, Z2, Y1*, Y2*. Input Present state Outputs Next state X Y1 Y2 Z1 Z2 Y1* Y2* Z1 = XY1 Y2 + XY1 Y2 = XY1 Z2 = X Y1 Y2 + X Y1 Y2 = X Y1 Y1* = X Y1 Y Y2* = X Y1 Y Fall 2014, Nov ELEC Lecture 7 45

46 Example 8.17: Robot Control (Continued... 8) Synthesize logic functions, Z1, Z2, Y1*, Y2*. Z1 X Y1* X 1 1 Y2 1 Y Z2 Y1 X Y2* Y1 X 1 1 Y2 1 Y Y1 Fall 2014, Nov ELEC Lecture 7 46 Y1

47 Example 8.17: Robot Control (Continued... 9) Synthesize logic and connect memory elements (flip-flops). X Combinational logic Z1 Y1* Y2* Z2 Y1 Y1 Y2 Y2 CLEAR CK Fall 2014, Nov ELEC Lecture 7 47

48 Steps in FSM Synthesis Examine specified function to identify inputs, outputs and memory states. Draw a state diagram. Minimize states (see Section 9.1). Assign binary codes to states (Section 9.4). Derive truth tables for state variables and output functions. Minimize multi-output logic circuit. Connect flip-flops for state variables. Don t forget to connect clock and clear signals. Fall 2014, Nov ELEC Lecture 7 48

49 Architecture of an FSM The Huffman model, containing: Flip-flops for storing the state. Combinational logic to generate outputs and next state from inputs and present state. Inputs Present state Combinational logic Next state Outputs Flipflops Clock Clear D. A. Huffman, The Synthesis of Sequential Switching Circuits, J. Franklin Inst., vol. 257, pp , March-April Fall 2014, Nov ELEC Lecture 7 49

50 State Minimization An FSM contains flip-flops and combinational logic: Number of flip-flops, N ff = log 2 N s, N s = #states Size of combinational logic depends on state assignment. Examples: Ceiling operator 1. N s = 16, N ff = log 2 16 = 4 2. N s = 17, N ff = log 2 17 = = 5 Fall 2014, Nov ELEC Lecture 7 50

51 Equivalent States Two states of an FSM are equivalent (or indistinguishable) if for each input they produce the same output and their next states are identical. Si 0/0 1/0 Sm Si and Sj are equivalent and merged into a single state. 1/0 Sm 1/0 Si,j 0/0 Sj 0/0 Sn Sn Fall 2014, Nov ELEC Lecture 7 51

52 Minimizing States Example: States A... I, Inputs I1, I2, Output, Z A and D are equivalent A and E produce same output Q: Can they be equivalent? A: Yes, if B and D were equivalent and C and G were equivalent. Present state Next state, output (Z) I1 Input I2 A D / 0 C / 1 B E / 1 A / 1 C H / 1 D / 1 D D / 0 C / 1 E B / 0 G / 1 F H / 1 D /1 G A / 0 F / 1 H C / 0 A / 1 I G / 1 H / 1 Fall 2014, Nov ELEC Lecture 7 52

53 Implication Table Method B C EH AD Present state Next state, output (Z) I1 Input I2 A D / 0 C / 1 D E F BD CG EH AD BD CG B E / 1 A / 1 C H / 1 D / 1 D D / 0 C / 1 E B / 0 G / 1 F H / 1 D / 1 G H AD CF CD AC AD CF CD AC AB FG BC AG AC AF G A / 0 F /1 H C / 0 A / 1 I G / 1 H / 1 I EG AH GH DH GH DH A B C D E F G H Fall 2014, Nov ELEC Lecture 7 53

54 Implication Table Method (Cont.) B Equivalent states: C EH AD S1: A, D, G D S2: B, C, F E BD CG BD CG S3: E, H F EH AD S4: I G AD CF AD CF AB FG H CD AC CD AC BC AG AC AF I EG AH GH DH GH DH A B C D E F G H Fall 2014, Nov ELEC Lecture 7 54

55 Minimized State Table Present state Original Next state, output (Z) I1 Input I2 A D / 0 C / 1 B E / 1 A / 1 C H / 1 D / 1 D D / 0 C / 1 E B / 0 G / 1 F H / 1 D / 1 G A / 0 F / 1 H C / 0 A / 1 I G / 1 H / 1 Present state Minimized Next state, output (Z) I1 Input I2 S1 = (A, D, G) S1 / 0 S2 / 1 S2 = (B, C, F) S3 / 1 S1 / 1 S3 = (E, H) S2 / 0 S1 / 1 S4 = I S1 / 1 S3 / 1 Number of flip-flops is reduced from 4 to 2. Fall 2014, Nov ELEC Lecture 7 55

56 State Assignment State assignment means assigning distinct binary patterns (codes) to states. N flip-flops generate 2 N codes. While we are free to assign these codes to represent states in any way, the assignment affects the optimality of the combinational logic. Rules based on heuristics are used to determine state assignment. Fall 2014, Nov ELEC Lecture 7 56

57 Criteria for State Assignment Optimize: Logic gates, or Delay, or Power consumption, or Testability, or Any combination of the above Up to 4 or 5 flip-flops: can try all assignments and select the best. More flip-flops: Use an existing heuristic (one discussed next) or invent a new heuristic. Fall 2014, Nov ELEC Lecture 7 57

58 The Idea of Adjacency Inputs are A and B State variables are Y1 and Y2 An output is F(A, B, Y1, Y2) A next state function is G(A, B, Y1, Y2) A Karnaugh map of output function or next state function Y2 Larger clusters produce smaller logic function. Y Clustered minterms differ in one variable. B Fall 2014, Nov ELEC Lecture 7 58

59 Size of an Implementation Number of product terms determines number of gates. Number of literals in a product term determines number of gate inputs, which is proportional to number of transistors. Hardware α (total number of literals) Examples of four minterm functions: F1 = ABCD + A B C D + A BCD + AB CD has 16 literals F2 = ABC + A CD has 6 literals Fall 2014, Nov ELEC Lecture 7 59

60 Rule 1 States that have the same next state for some fixed input should be assigned logically adjacent codes. Fixed Inputs Si Sj Present state Combinational logic Flipflops Sk Next state Outputs Clock Clear Fall 2014, Nov ELEC Lecture 7 60

61 Rule 2 States that are the next states of the same state under logically adjacent inputs, should be assigned logically adjacent codes. Adjacent Inputs I1 I2 Fixed present state Si Combinational logic Sk Sm Next state Outputs Flipflops Clock Clear Fall 2014, Nov ELEC Lecture 7 61

62 Example of State Assignment Present state Next state, output (Z) Input, X 0 1 A C, 0 D, 0 A adj C (Rule 1) 0/1 1/0 A 0/0 1/0 A adj B (Rule 1) B C, 0 A, 0 C B, 0 D, 0 D A, 1 B, 1 Figure 9.19 of textbook 0 1 C adj D (Rule 2) D 1/0 1/1 C 0/0 B 0/0 0 1 A C B D Verify that BC and AD are not adjacent. B adj D (Rule 2) Fall 2014, Nov ELEC Lecture 7 62

63 A = 00, B = 01, C = 10, D = 11 Present state Y1, Y2 Next state, output Y1*Y2*, Z Input, X 0 1 A = / 0 11 / 0 B = / 0 00 / 0 C = / 0 11 / 0 D = / 1 01 / 1 Input Present state Output Next state X Y1 Y2 Z Y1* Y2* Fall 2014, Nov ELEC Lecture 7 63

64 Logic Minimization for Optimum State Assignment X Z Y1* X Y2 1 1 Y2 1 1 Y1 Y2* Y1 X Result: 5 products, 10 literals. Y Fall 2014, Nov ELEC Lecture 7 64 Y1

65 Circuit for Optimum State Assignment X 32 transistors Combinational logic Z Y1* Y1 Y1 Y2* CLEAR Y2 Y2 CK Fall 2014, Nov ELEC Lecture 7 65

66 Using an Arbitrary State Assignment: A = 00, B = 01, C = 11, D = 10 Present state Y1, Y2 Next state, output Y1*Y2*, Z Input, X 0 1 A = / 0 10 / 0 B = / 0 00 / 0 C = / 0 10 / 0 D = / 1 01 / 1 Input Present state Output Next state X Y1 Y2 Z Y1* Y2* Fall 2014, Nov ELEC Lecture 7 66

67 Logic Minimization for Arbitrary State Assignment X Z Y1* 1 1 X 1 1 Y2 Y2 1 1 Y1 Y2* Y1 X Result: 6 products, 14 literals. 1 1 Y2 1 1 Fall 2014, Nov ELEC Lecture 7 67 Y1

68 Circuit for Arbitrary State Assignment Comb. logic Z X Y1* Y2* 42 transistors Y1 Y1 CLEAR Y2 Y2 CK Fall 2014, Nov ELEC Lecture 7 68

69 Find Out More About FSM State minimization through partioning (Section 9.2.2). Incompletely specified sequential circuits (Section 9.3). Further rules for state assignment and use of implication graphs (Section 9.4). Asynchronous or fundamental-mode sequential circuits (Chapter 10). Fall 2014, Nov ELEC Lecture 7 69

EE40 Lec 15. Logic Synthesis and Sequential Logic Circuits

EE40 Lec 15. Logic Synthesis and Sequential Logic Circuits EE40 Lec 15 Logic Synthesis and Sequential Logic Circuits Prof. Nathan Cheung 10/20/2009 Reading: Hambley Chapters 7.4-7.6 Karnaugh Maps: Read following before reading textbook http://www.facstaff.bucknell.edu/mastascu/elessonshtml/logic/logic3.html