Timing Constraints in Sequential Designs. 63 Sources: TSR, Katz, Boriello & Vahid

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1 Timing Constraints in Sequential esigns 63 Sources: TSR, Katz, Boriello & Vahid

2 Where we are now. What we covered last time: FSMs What we ll do next: Timing constraints Upcoming deadlines: ZyBook today: Sec HW#5 due next Tuesday Note: we grade only 2 problems out of 4 on each HW assignment Quiz #5 today Quiz curve for 0 score needs manual input, let me know if there is an issue! Midterm #2 coming up next week iscussion session next Monday will help prepare for midterm Class survey: Lowest HW grade dropped if response rate > 80% by Th, 5/21, 11am Textbook references: chap 3, Sec 6.3 Prof. office hours today: 1:30-2:30pm (instead of starting at 2:20pm) TA/Tutor office hours back to full schedule starting tonight Sources: TSR, Katz, Boriello & Vahid

3 Timing Constraints in Sequential Circuit esigns Combinational Our seemingly logically correct design can go wrong signals don t travel in zero time We next look at timing constraints for combinational and sequential logic.

4 Combinational Logic Timing I. Min delay of a gate, also called contamination delay: t cd Minimum time from when an input changes until the output starts to change II. Max delay of a gate, also called propagation delay: t pd Maximum time from when an input changes until the output is guaranteed to reach its final value (i.e., stop changing) 66 Sources: TSR, Katz, Boriello & Vahid

5 Combinational Logic: Output Timing Constraints A B C Y Which path in the above circuit determines the contamination delay of the circuit (assuming the delay of all the gates is the same)? A. Blue path B. Red path C. Both. Neither 67 Sources: TSR, Katz, Boriello & Vahid

6 Combinational Logic: Output Timing Constraints A B C Y Which path in the above circuit determines the propagation delay of the circuit (assuming the delay of all the gates is the same)? A. Blue path B. Red path C. Both. Neither 68 Sources: TSR, Katz, Boriello & Vahid

7 -FF Input Constraints: Setup and Hold Times S latch Q Q C R Q S latch t setup t hold C Q t a R I. Setup time: t setup Time before the clock edge that data must be stable (i.e. not change) II. Hold time: t hold Time after the clock edge that data must be stable Aperture time: t a Time around clock edge that data must be stable (t a = t setup + t hold ) 69 Sources: TSR, Katz, Boriello & Vahid

8 Output Timing Constraints Q Q Q t ccq t pcq I. Min delay of FF, also called contamination delay or min to Q delay: t ccq Time after clock edge that Q might be unstable (i.e., starts changing) II. Max delay of FF, also called propagation delay or maximum to Q delay: t pcq Time after clock edge that the output Q is guaranteed to be stable (i.e. stops changing) 70

9 The timing of which of the following signals can cause a setup-time violation? A. The input signal (t) B. The output signal Q(t) C. Both of the above. None of the above Comb Logic (t) Q Q Q(t) 71 Sources: TSR, Katz, Boriello & Vahid

10 Causes of Timing Issues in Sequential Circuits Input to a FF comes from the output of another FF through a combinational circuit The FF and combinational circuit have a min & max delay (a) 2 (b) R1 C L T c 2 R2 Which of the following violations occurs if max delay of R1 is zero & max delay of the combinational circuit is equal to the clock period? A. Hold time violation for R2 B. Setup violation for R2 C. Hold time violation for R1. Setup violation for R1 E. None of the above

11 Setup Time Constraint Input to a FF comes from the output of another FF through a combinational circuit The FF and combinational circuit have a min & max delay C L 2 (a) R1 R2 Setup time constraint: 2 (b) T c T c t setup + max delay(ff) + max delay(combinational) T c t pcq + t pd + t setup

12 Causes of Timing Issues in Sequential Circuits Input to a FF comes from the output of another FF through a combinational circuit The FF and combinational circuit have a min & max delay (a) R1 C L 2 R2 Which of the violations would occur if the min delay of R1 was zero and the combinational circuit was just a wire? 2 (b) T c A. Hold time violation for R2 B. Setup violation for R2 C. Hold time violation for R1. Setup violation for R1 E. None of the above

13 Hold Time Constraint Input to a FF comes from the output of another FF through a combinational circuit The FF and combinational circuit have a min & max delay C L 2 (a) R1 R2 Hold time constraint: T c t hold < min delay(ff) + min delay(combinational) t hold < t ccq + t cd 2 (b)

14 FF Timing Parameters Once a flip flop has been built, its timing characteristics stay fixed: t setup, t hold, t ccq, t pcq 1 2 R1 Combinational R2 What about the clock? oes the clock edge arrive at the same time to all the -FFs on the chip? 76 Sources: TSR, Katz, Boriello & Vahid

15 Clock Skew The clock doesn t arrive at all registers at the same time Skew: difference between the two clock edges Perform the worst case analysis delay 1 2 C L 2 R1 R2 t skew 1 2

16 Setup Time Constraint with Skew In the worst case, 2 is earlier than 1 t pcq is max delay through FF, t pd is max delay through logic 1 2 C L R1 T c R2 T c t pcq + t pd + t setup + t skew t pd T c (t pcq + t setup + t skew ) t pcq t pd t setup t skew

17 Hold Time Constraint with Skew In the worst case, 2 is later than 1 t ccq is min delay through FF, t cd is min delay through logic 1 C L R1 R2 t ccq + t cd > t hold + t skew t cd > t hold + t skew t ccq 2 t ccq t cd t skew t hold Sources: TSR, Katz, Boriello & Vahid

18 Timing Analysis Example A B C X' X Timing Characteristics t ccq t pcq t setup t hold = 30 ps = 50 ps = 60 ps = 70 ps t pd = 3 x 35 ps = 105 ps t cd = 25 ps Setup time constraint: T c ( ) ps = 215 ps f c = 1/T c = 4.65 GHz Y' Y per gate t pd t cd = 35 ps = 25 ps Hold time constraint: t ccq + t cd > t hold? ( ) ps > 70 ps? No!

19 Timing Analysis Example Add buffers to the short paths: A B C X' X Timing Characteristics t ccq t pcq t setup t hold = 30 ps = 50 ps = 60 ps = 70 ps t pd = 3 x 35 ps = 105 ps t cd = 2 x 25 ps = 50 ps Setup time constraint: T c ( ) ps = 215 ps f c = 1/T c = 4.65 GHz Y' Y per gate t pd t cd = 35 ps = 25 ps Hold time constraint: t ccq + t cd > t hold? ( ) ps > 70 ps? Yes!

20 Sequential Circuit esign Summary SRAM memory, SR Latch, Latch, -FF esign procedure for FSMs 1. Capture FSM 2. Create state table 3. Assign the states 4. Excitation table 5. Implement the combinational logic Mealy vs. Moore FSM Non-ideal properties of FFs Setup/hold time constraints Maximum operating frequency Clock skew 82 Sources: TSR, Katz, Boriello & Vahid

21 MORE FSM EXAMPLES 83 Sources: TSR, Katz, Boriello & Vahid

22 15 cents for candy! Watch out no change! Moore machine outputs associated with state Reset N + Reset Mealy machine outputs associated with transitions Reset/0 (N + Reset)/0 0 [0] N 0 N /0 N N/0 5 [0] N /0 5 N /0 N N/0 10 [0] N /1 10 N /0 N+ N+/1 15 [1] Reset 15 Reset /1 84

23 Example: Moore implementation 1 Encode states and map to logic 0 Open N N N X X 1 X X X 1 X X X 1 X Q0 Q0 Q0 present state inputs next state output Q0 N 1 0 open

24 Example: Mealy implementation Reset/0 Reset/0 0 N/0 /0 5 N/0 /1 10 N+/1 15 N /0 N /0 N /0 Reset /1 Open X X 1 X Q0 N present state inputs next state output Q0 N 1 0 open Sources: TSR, Katz, Boriello & Vahid

25 FSM design: Multiple input counter Given FSM of a multiple input counter, design the circuit implementing its functionality S0 S , S1 S present next state output state S0 S0 S1 S2 S3 1 S1 S0 S3 S1 S3 0 S3 S1 S0 S0 S3 0 S2 S1 S3 S2 S State Input Inputs State

26 Multiple input counter: Logic for -FF erive logic equations for inputs of State -FF Input I1I I1I