Adders, subtractors comparators, multipliers and other ALU elements

Transcription

1 CSE4: Components and Design Techniques for Digital Systems Adders, subtractors comparators, multipliers and other ALU elements Instructor: Mohsen Imani UC San Diego Slides from: Prof.Tajana Simunic Rosing & Dr.Pietro Mercati

2 Adders 2

3 Circuit Delay Transistors have instrinsic resistance and capacitance Signals take time to propagate from the input to the output of a gate Sometimes delays are labeled in circuit drawings 3

4 -Bit & Multi-bit Adders Half Adder A C out + S B C out Full Adder A + S B C in Types of multi-bit adders Ripple-carry (slow) Carry-lookahead (faster) Two-level logic adder (even faster) A B C out S = A B C out = AB S C in A B C out S C out Symbol A B N N + S N C in S = A B C in C out = AB + AC in + BC in

5 Ripple-Carry Adder Chain -bit adders together Carry ripples through entire chain Disadvantage: slow A 3 B 3 A 3 B 3 A B A B C out + C + 3 C 29 C + C + C in S 3 S 3 S S Ripple-carry adder delay t ripple = Nt FA where t FA is the delay of a full adder

6 Two-level Logic Adder No matter how many inputs you have, look at the truth table, convert to Kmap, apply the algorithm for two-level logic minimization Very fast adder, but. Beyond 8 inputs, a shockingly large amount of gates! Number of gates increases exponentially Ripple carry adder Carry-lookahead adder (next slide) FAST Two-level logic adder COMPLEX

7 Carry-lookahead adders c4 c3 c2 c c a3 a2 a a b3 b2 b b s3 s2 s s Carries First operand Second operand From the very beginning I can look ahead into the value of carries

8 Full Adder Ci+ = Ai Bi + Ci (Ai xor Bi) Generate Propagate Ci+ = Gi + Ci Pi 8

9 Carry-lookahead adders Adder with propagate (P) and generate (G) outputs: Ci+ = Ai Bi + Ci (Ai xor Bi) Generate Propagate Ci+ = Gi + Ci Pi The carry at some level is equal to if either the generate signal is equal to one or if the propagate and the previous carry are both

10 Carry-Lookahead Adder Ref: Dan Earnst

11 Carry-Lookahead Adder A [5-2] B [5-2] C 4-bit Adder 2 P G 4 A [-8] B [-8] C 4-bit Adder 8 P G 4 A [7-4] B [7-4] C 4-bit Adder 4 P G 4 A [3-] B [3-] C 4-bit Adder P G 4 S [5-2] S [ -8] S [7-4] S [3-] P 3 G 3 C 3 P 2 G 2 C 2 P G C P G C C 6 C 4 Lookahead Carry Unit P 3- G 3- C 4 bit adders with internal carry look-ahead P and G logic Second level carry-lookahead unit creates the GROUP P and G signals

12 Carry-lookahead adders Example: 4-bit CLA adder c = G + P c c2 = G + P c c3 = G2 + P2 c2 c4 = G3 + P3 c3 Gi = ai bi Pi = ai xor bi generate propagate All G and P are immediately available, but c are not (except the c). So you need to make substitutions: c = G + P c c2 = G + P (G + P c) c3 = G2 + P2 c2 c4 = G3 + P3 c3 = G + PG + PPc = (derive at home) = (derive at home) 2

13 Carry-lookahead adders Propagate/Generate circuit (one per each input bit) Ai Bi Ci gate delay 2 gate delays gate delay Carry circuits (implement the equations derived in the previous slide) C P G C P P G P G 3 3 C P P P2 G P P2 G P2 G2 3 Note: this approach of looking ahead for building multi-bit operations is not limited to adders! C P P P2 P3 G P P2 P3 G P2 P3 G2 P3 G3 3 3

14 Carry-select adder Redundant hardware to make carry calculation go faster compute two high-order sums in parallel while waiting for carry-in one assuming carry-in is and another assuming carry-in is select correct result once carry-in is finally computed 4

15 Carry-select adder A 6-bit carry-select adder with a uniform block size of 4 Using three blocks and a 4-bit ripple carry adder Carry-in is known at the beginning of computation, a carry select block is not needed for the first four bits The delay of this adder will be four full adder delays, plus three MUX delays. 5

16 Carry Save Adder (CSA) Making N additions independent and in parallel with no carry propagation Propagate carry at the last stage 6

17 Approximate Adder Several applications accept a part of inaccuracy in their computation (e.g. multimedia) Inaccuracy is inherent in many applications due to its stochastic behavior (e.g. machine learning) Can we relax the computation in order to improve efficiency? A 3 B 3 A 3 B 3 A B A B C out + C + 3 C 29 C + C + C in S 3 S 3 S S 7

18 Quality Comparison Sobel Application (Image Processing) Robert Application (Image Processing)

19 Approximate Adder How about dropping the least N significant bits? A 3 B 3 A 3 B 3 A B A B C out + C + 3 C 29 C + C + C in S 3 S 3 S S 9

20 Approximate Adder Can we do better job than dropping values? Carry is more costly or sum? Except two cases: C out!=sum A 3 B 3 A 3 B 3 A B A B C out + C + 3 C 29 C + C + C in 2 S 3 S 3 S S

21 Subtractors 2

22 2s complement If N is a positive number, then the negative of N (its 2s complement or N* ) is bit-wise complement plus The most significant bit represent the sign: for positive and for negative N bit can represent [ 2 N ] integer positive numbers In 2s complement, you can represent the interval (2 N (2 N )] 22

23 2s Complement: Examples A 8-bit example (positive) = (complement) (add ) A 5-bit example (negative) = -4 (complement) (add ) 23

24 Subtraction If you are using 4 bit numbers, what is the result of the following equation in 2s complement: y = 4-7 A. B. C. D. E. None of the above 24

25 Detecting Overflow: Method Assuming 4-bit two s complement numbers, one can detect overflow by detecting when the two numbers sign bits are the same but are different from the result s sign bit If the two numbers sign bits are different, overflow is impossible Adding a positive and negative can t exceed the largest magnitude positive or negative Simple circuit overflow = a3 b3 s3 + a3b3s3 sign bits overflow (a) overflow (b) no overflow (c) If the numbers sign bits have the same value, which differs from the result s sign bit, overflow has occurred. 25

26 Detecting Overflow: Method 2 Detect a difference between carry-in to sign bit and carry-out from it Yields a simpler circuit: overflow = c3 xor c4 = c3 c4 + c3 c overflow (a) overflow (b) no overflow (c) If the carry into the sign bit column differs from the carry out of that column, overflow has occurred. 26

27 Subtractor A subtraction between A and B is the same as the sum between the first value and the negative of the second value: (A - B) = A + (-B) Represent numbers in 2s complement and use a normal adder! Symbol A B N N - Y N Implementation A B N N N + Y N

28 Adder/subtractor A3 B3B3' A2 B2B2' A BB' A BB' Sel Sel Sel Sel A B A B A B A B Cout Cin Cout Cin Cout Cin Cout Cin Sel Sum Sum Sum Sum S3 S2 S S Overflow In this schematic addition occurs when Sel signal is: A. True B. False 28

29 More ALU Components 29

30 Comparator: Equality Two numbers are equal if each digit at each position is equal (this is true for any base: decimal, binary, etc). The bit-to-bit equality can be evaluated with the XNOR gate. Symbol Implementation A 3 B 3 A 4 = B 4 A 2 B 2 A Equal Equal B A B

31 Comparator: Less Than If a number A is less than B and you consider the difference A B, this is: negative. So comparing numbers is equivalent to check the sign of the difference. In 2s complement representation, the sign of the result corresponds to: the most significant bit A N B N - N [N-] A < B 5-<3>

32 Shifters Logical shifter: shifts value to left or right and fills empty spaces with s Ex: >> 2 = Ex: << 2 = Arithmetic shifter: same as logical shifter, but on right shift, fills empty spaces with the old most significant bit Ex: >>> 2 = Ex: <<< 2 = Rotator: rotates bits in a circle, such that bits shifted off one end are shifted into the other end Ex: ROR 2 = Ex: ROL 2 = Useful for 2- complement numbers

33 General Shifter Design A 3 A 2 A A shamt : 2 S : Y 3 Based on the value of the selection input (shamt = shift amount) S : Y 2 The chain of multiplexers determines how many bits to shift S : S : Y Example: if S = then Y3 = Y2 = A3 Y = A2 Y = A Y

34 Multiplication of positive binary numbers Generalized representation of multiplication by hand Example: in decimal, 32 * 4 = (3+2)*4 = 3*4 + 2*4 Basically: sum up the partial products (pp) The binary multiplier is based on the same idea: For demo see: 34

35 pp4 pp3 pp2 pp Multiplier design array of AND gates Multiplier Array Style a3 a2 a a b b b2 + (5-bit) b3 + (6-bit) A * P B If the multiplier has two N-bit inputs, how many bits are required for the output? + (7-bit) p7..p Block symbol 35

36 Approximate Multiplier How about Approximate Multiplier? What will happen if one of the input operands are power of two? Do we need to multiply? Detect such cases and replace multiplication with shift operation E.g. * shift the first operand to right (-bit) E.g. A * shift the first operand to right (2-bit) How about A*? Can I ignore the last bit and just shift the number by 9-bits? 36

37 Floating Point Multiplication Why we need floating point unit (FP) representation? More precision, covering wide range of values! FP representation: sign.fraction * 2^(exponent) E.g. =.() b * 2^9 =.25 * 2^9 37

38 Division of positive binary numbers Repeated subtraction Set quotient to Repeat while dividend >= divisor Subtract divisor from dividend Add to quotient When dividend < divisor: Reminder = dividend Quotient is correct B A Example: Dividend: ; Divisor: Dividend Quotient DIVIDER OUT For demo see: 38

39 ALU: Arithmetic Logic Unit 39

40 Zero Extend 2 3 Arithmetic Logic Unit Example A N N N B N F 2 A N ALU N Y B N 3 F F 2: Function A & B A B A + B Not used A & ~B A ~B C out + [N-] S A - B Not used N N N N 2 F : Implement the ALU using as few components as possible Y N

41 Transistors Summary of what we have seen so far Boolean algebra Basic gates Logic functions and truth tables Canonical forms (SOP and POS) Two-level logic minimization Kmaps Multiplexers (behavior and how to implement logic functions with them) Decoders (behavior and how to implement logic functions with them) Today: Adders, subtractors, and other ALU components SO FAR: only COMBINATIONAL logic (i.e. no memory elements) 4

42 CSE4: Components and Design Techniques for Digital Systems Sequential Circuit Introduction Latches and Flip-Flops Tajana Simunic Rosing

43 What is a sequential circuit? A circuit whose output depends on current inputs and past outputs A circuit with memory Memory / Time steps x i s i y i Clock y i =f i (S t,x) s i t+ =g i (S t,x) 43

44 Why do we need circuits with memory? Circuits with memory can be used to store data Systems have circuits that run a sequence of tasks Memory Hierarchy Registers Cache Main Memory Hard disk

45 Flight attendant call button Flight attendant call button Press call: light turns on Stays on after button released Press cancel: light turns off Logic circuit to implement this? Call button Cancel button Bit Storage Blue light. Call button pressed light turns on SR latch implementation Call= : sets Q to and keeps it at Cancel= : resets Q to Call button Cancel button Bit Storage Blue light 2. Call button released light stays on a Call button S Call button Cancel button Bit Storage Blue light Cancel button R Q Blue light 3. Cancel button pressed light turns off 45

46 SR Latch Analysis S =, R = : then Q = and Q = R N Q S N2 Q S =, R = : then Q = and Q = R N Q S N2 Q

47 SR Latch Analysis S =, R = : Q prev = Q prev = then Q = Q prev Memory! R N Q R N Q S N2 Q S N2 Q S =, R = : then Q =, Q = Invalid State Q NOT Q R S N N2 Q Q

48 What if a kid presses both call and cancel Call but ton Cancel but ton & then releases them? S R If S= and R= at the same time and then released, Q=? Can also occur also due to different delays of different paths Q may oscillate and eventually settle to or due to diff. path delay 48 Q Blue light S R Q hold not allowed S R t Q

49 SR Latch Symbol SR stands for Set/Reset Latch Stores one bit of state (Q) Control what value is being stored with S, R inputs Set: Make the output (S =, R =, Q = ) Reset: Make the output (S =, R =, Q = ) Hold: Keep data stored (S =, R =, Q = Q previous ) SR Latch Symbol R S Q Q

50 SR Latch Characteristic Equation To analyze, break the feedback path SR Latch Symbol R Q Q(t) R Q S Q' S R Q(t+ ) S Q S R Q(t) Q(t+ ) S hold X reset Q(t) X R set X characteristic equation not allowed X Q(t+ ) = S + R Q(t) State Diagram 5 SR

51 Add input C Avoiding S=R= Part : Level-Sensitive SR Latch Change C to only after S and R are stable C is usually a clock (CLK) S Level-sensitive SR latch S C R R Q

52 Clocks Freq GHz GHz GHz MHz MHz Period. ns. ns ns ns ns Clock -- Pulsing signal for enabling latches; ticks like a clock Synchronous circuit: sequential circuit with a clock Clock period: time between pulse starts Above signal: period = 2 ns Clock cycle: one such time interval Above signal shows 3.5 clock cycles Clock duty cycle: time clock is high 5% in this case Clock frequency: /period Above : freq = / 2ns = 5MHz; 52

53 Clock question The clock shown in the waveform below has: ns CLK A. Clock period of 4ns with 25MHz frequency B. Clock duty cycle 75% C. Clock period of ns with GHz frequency D. A. & B. E. None of the above 53

54 Avoiding S=R= Part 2: Level-Sensitive D Latch D C D S D latch S C R Q Q R SR latch requires careful design so SR= never occurs D latch helps by inserting the inverter between S & R inputs Inserted inverter ensures R is always the opposite of S when C= 54

55 D Latch Truth Table CLK D R R Q Q D S S Q Q CLK D X D X S R Q Q Q prev Q prev

56 D Latch Summary Two inputs: CLK, D CLK: controls when the output changes D (the data input): controls what the output changes to Function When CLK =, D passes through to Q (transparent) When CLK =, Q holds its previous value (opaque) (Mostly) avoids invalid case Q = Q D Latch Symbol D CLK Q Q