Vidyalankar S.E. Sem. III [CMPN] Digital Logic Design and Analysis Prelim Question Paper Solution
|
|
- Christina Jefferson
- 5 years ago
- Views:
Transcription
1 . (a) (i) ( B C 5) H (A 2 B D) H S.E. Sem. III [CMPN] Digital Logic Design and Analysis Prelim Question Paper Solution ( B C 5) H (A 2 B D) H = (FFFF 698) H (ii) (2.3) 4 + (22.3) (2.3) 4 + (22.3) 4 = (23.2) 4 (iii) (77) 8 (7) 8 Octal Table X octal addition (7 + 7 = 6) Note : Add octal addition = octal multiplication table. Octal Addition Octal Multiplicaiton /Engg/SE/Pre Pap/23/CMPN/DLDA_Soln
2 : S.E. DLDA. (b) (iv) () 2 () 2 Quotient = () 2 Reminder = () 2 (i) A AB ABC ABCD A + B + AB(C CD) ( A + AB = A + B) A + B + AB(C D) ( A (B + C) = AB + AC) A + B + ABC ABD A + ABC B BAD A + BC B AD A + AD B BC A + D + B + C A + B + C + D (ii) A[BC(ABAC)] = A [B + C (AB.AC)] (De-Morgan 2 law = AB AB) = A [B + C (A B). (A C)] (De-Morgan law = AB A B) = A [B + C (A.A A.B A.C B.C)] = A [B + C ( A.B A.C B.C)] (A.A ) = A [B + C. + A.BC A.CC B.CC] (A. = ) = A [B + + A.BC ] = AB + A.A.B.C = AB + = AB 2 3/Engg/SE/Pre Pap/23/CMPN/DLDA_Soln
3 Prelim Question Paper Solution. (c) D in : 4 Demux 2 Y Y 3 O/Ps Data input D in : 4 Demux S 3 S 2 D in D in D in : 4 Demux 3 : 4 Demux 4 : 4 Demux 5 In all five : 4 Demux ICs are used. S S S 2 S 3 are the four select lines. D in is the data input and Y Y 5 are the 6 outputs of the :6 demux. The truth table of :6 Demux is shown in below table. Select inputs Output S 3 S 2 S S Y = D in S 3 S 2 = : : : Demux 2 is selected : : : Y 3 = D in Y 4 = D in S 3 S 2 = : : : Demux 3 is selected : : : Y 7 = D in Y 8 = D in S 3 S 2 = : : : Demux 4 is selected : : : Y = D in Y 2 = D in S 3 S 2 = : : : Demux 5 is selected : : : Y 5 = D in Y 4 Y 7 Y 8 Y Y 2 Y 5 O/Ps O/Ps O/Ps S S 3/Engg/SE/Pre Pap/23/CMPN/DLDA_Soln 3
4 : S.E. DLDA. (d) The "Race Around Condition" that we are going to explain occurs when J = K = i.e. when the latch is in the toggle mode. Refer figure which shows the waveforms for the various modes, when a rectangular waveform is applied to the "Enable" input Waveforms for various modes of a JK latch. Interval t -t During this interval J =, K = and E =. Hence the latch is disabled and there is no change in Q. Interval t -t 2 During this interval J =, K = and E = l. Hence this is a set condition and Q becomes. Interval t 2 -t 3 : Race Around At instant t 2, J = K = and E = Hence the JK latch is in the toggle mode and Q becomes low () and Q = l. These changed outputs get applied at the inputs of NAND gates 3 and 4 of the JK latch. Thus the new inputs to Gates 3 and 4 are : NAND-3 : J =, E = l, Q = NAND-4 : K =, E =, Q =. Hence R' will become and S' will become. Therefore after a time period corresponding to the propagation delay, the Q and Q outputs will change to, Q = and Q =. These changed output again get applied to the inputs of NAND-3 and 4 and the outputs will toggle again. Thus as long as J = K = and E =, the outputs will keep toggling indefinitely as shown in figure. This multiple, toggling in the J-K latch is called as Race Around condition. It must be avoided. Interval t 3 -t 4 During this interval J =, K = and E =. Hence it is the reset condition. So Q becomes zero. 4 3/Engg/SE/Pre Pap/23/CMPN/DLDA_Soln
5 Prelim Question Paper Solution 2. (a) Given F(A, B, C, D) = m (, 2, 3, 6, 7, 8, 9, 2, 3) = m (, 4, 5,,, 4, 5) Step : Arranging minterms in groups of s Group (No. of s) Minterm A B C D Step 2: Arranging minterms to form pairs Minterm Group pairs A B C D Step 3: Arranging minterms to form Quads Prime Implicants ACD ABC Groups Quad pairs A B C D Prime implicants 4 5 AC 4 5 Table of prime implicants Prime Given minterm Minterm Implicants ACD, 5 ABC 4, 5 AC,, 4, 5 can t ignore F(A,B,C,D) = ACD ABC AC F(A,B,C,D) = = ACD ABC AC = (ACD)(ABC)(AC) (ACD)(ABC)(AC) 3/Engg/SE/Pre Pap/23/CMPN/DLDA_Soln 5
6 : S.E. DLDA Implementation using NAND gates A B C D ACD 2. (b) Full Adder using Half Adder Fig. The full adder circuit can be constructed using two half adders as shown in fig. and the detail circuit is shown in fig.2. A full adder can be implemented using two half adders and the OR gate as shown in fig.2. Fig.2 Now let us prove that this circuit acts as a full adder. Truth table ABC AC (ACD)(ABC)(AC) = F = ACD ABC AC 6 3/Engg/SE/Pre Pap/23/CMPN/DLDA_Soln
7 3. (a) Proof : Refer Fig. 2 and write the expression for sum output as, S = (A B) C in = A B C in This expression is same as that obtained for the full adder. Now write the expression for carry output C as C = (A B) C in + AB C = (AB AB)C AB in = in in ABC ABC AB = in in in Prelim Question Paper Solution ABC ABC AB( C ) = ABCin ABCin AB ABCin = in in BC (A A) ABC AB = BCin ABCin AB = in in in BC ABC AB( C ) = BCin ABCin AB ABCin = in in BC AB AC (B B) C = BC in AB AC in This expression is same that for a full adder. Thus we have proved that circuit shown in fig.2 really behaves like a full adder. Applications of Full Adder The full adder acts as the basic building block of the 4 bit/8 bit binary/bcd adder ICs such as The NAND and NOR gates are called as Universal Gates Because it is possible to implement any Boolean expression with the help of only NAND or only NOR gates. Hence a user can build any combinational circuit with the help of only NAND gates or only NOR gates. This is a great advantage because a user will have to make a stock of only NAND or NOR gate ICs. Universal Property NAND Gate The NAND gate can be used to generate the NOT function, the AND function, the OR function, and the NOR function. NOT Function: An inverter can be made from a NAND gate by connecting all of the inputs together and creating, in effect, a single common input, as shown in Fig., for a twoinput gate: Fig. : NOT function using NAND gates 3/Engg/SE/Pre Pap/23/CMPN/DLDA_Soln 7
8 : S.E. DLDA AND Function : An AND function can be generated using only NAND gates. It is generated by simply inverting output of NAND gate; i.e. AB = AB. Fig. 2 shows the two input AND gate using NAND gates. A B AB A B AB AB Table : Truth Table OR Function OR function is generated using only NAND gates as follows : We know that Boolean expression for OR gate is Y = A + B = AB Rule 9 : [AA] Theorem Fig. 2 : AND function using NAND gates = A.B DeMorgan s The above equation is implemented using only NAND gates as shown in the Fig. 3. Fig. 3 : OR function using only NAND gates Note : Bubble at the input of NAND gate indicates inverted input. A B A+B A B A.B A.B Table : Truth table 8 3/Engg/SE/Pre Pap/23/CMPN/DLDA_Soln
9 Prelim Question Paper Solution NOR Function NOR function is generated using only NAND gates as follows : We know that Boolean expression for NOR gate is Y = AB = A.B = A.B DeMorgan s Theorem 2 Rule 9 : [A A] The above equation is implemented using only NAND gates, as shown in the fig. 4. Fig. 4 : NOR function using only NAND gates A B A B A B A.B A.B A.B Table : Truth Table NOR Gate Similar to NAND gate, the NOR gate is also a universal gate, since it can be used to generate the NOT, AND, OR and NAND functions. NOT Function An inverter can be made from a NOR gate by connecting all of the inputs together and creating, in effect, a single common input, as shown in Fig. 5. Fig. 5 : NOT function using NOR gate 3/Engg/SE/Pre Pap/23/CMPN/DLDA_Soln 9
10 : S.E. DLDA OR Function An OR function can be generated using only NOR gates. It can be generated by simply inverting output of NOR gate; i.e. A B = A + B. Fig. 6 shows the two input OR gate using NOR gates. Fig. 6 : OR function using NOR gates A B A+B A B A B A B Table : Truth table AND Function AND function is generated using only NOR gates as follows : We know that Boolean expression for AND gate is Y = A. B = A.B Rule 9 : [A A] = A B DeMorgan s Theorem 2 The above equation is implemented using only NOR gates as shown in the Fig. 7. Fig. 7 : AND function using NOR gates A B A+B A B A B A B Table : Truth table 3/Engg/SE/Pre Pap/23/CMPN/DLDA_Soln
11 Prelim Question Paper Solution NAND Function NAND function is generated using only NOR gates as follows : We know that Boolean expression for NAND gate is Y = A.B = A B DeMorgan s Theorem = A B Rule 9 : [A A] The above equation is implemented using only NOR gates, as shown in the Fig. 8. Fig. 8 : NAND function using only NOR gates A B A+B A B A B A B A B Table : Truth table 3. (b) Flip-flops required : 2 n N N = 6 n = 3 i.e., three flip-flops required. Fig. : MOD-6 synchronous p counter FF-A acts as a toggle FF since J A = K A =. Q A output of FF-A is applied to J B as well as K B. Hence if Q A = at the instant of triggering, then FF-B will toggle but if Q A = then FF-B will not change its state. Q A and Q B are ANDed and the output of AND gate is applied to J C and K C. Hence when Q A and Q B both are simultaneously high, then J C = K C = and FF-C will toggle. Otherwise there is no change in the state of FF-3. 3/Engg/SE/Pre Pap/23/CMPN/DLDA_Soln
12 : S.E. DLDA So in general we can say that each FF should have its J and K inputs connected such that they are high only when the outputs of all lower order FFs are in the high state. Operation Initially all the FFs are in their rest state. Q C Q B Q A = st clock pulse FF-A toggles and Q A changes to from. But since Q A = at the instant o application of st falling clock edge, J B = K B = and Q B does not change state. Q B remains. Similarly Q C also does not change state. Q C = Q C Q B Q A = after st clock pulse 2 nd clock pulse FF-A toggles and Q A becomes. But at the instant of application of 2 nd falling clock edge Q A was equal to. Hence J B = K B =. Hence FF-B will toggle and Q B becomes. Output of AND gate is at the instant of negative clock edge. So J C = K C =. Hence Q C remains. Q C Q B Q A = after the 2 nd clock pulse 3 rd clock pulse After the 3 rd clock pulse, the outputs are Q C Q B Q A =. 4 th clock pulse Note that Q B = Q A =. Hence output of AND gate = and J C = K C =, at the instant of application of 4 th negative edge of the clock. Hence on application of this clock pulse, FF-C will toggle and Q C changes from to. FF-A toggles as usual and Q A becomes. Since Q A was equal to earlier, FF-B will also toggle to make Q B =. Q C Q B Q A = after the 4 th clock pulse Thus the counting progresses. After the 7 th clock pulse the output is and after the 8 th clock pulse, all the flip-flops toggle and change their outputs to. Hence Q C Q B Q A = after the 8 th pulse and the operation repeats. Clock Q C Q B Q A st () 2 nd () 3 rd () 4 th () 5 th () 6 th () 7 th () Fig /Engg/SE/Pre Pap/23/CMPN/DLDA_Soln
13 4. (a) Prelim Question Paper Solution Below figure shows the implementation of given Boolean function with 8 : multiplexer. 4. (b) D D D 2 D 3 D 4 D 5 D 6 D 7 A A A A A A D D D 2 D 3 D 4 D 5 D 6 D 7 8 : MUX (i) Design a D flip Flop from a RS Flop Next state Q n + S R Inputs Outputs D Present state Q n X X Entries from excitation table of D FF Entries from excitation table of SR FF (ii) JK to T J and K are the actual inputs of the flip flop and T is taken as the external input for conversion. Four combinations are produced with T and Q p. J and K are expressed in terms of T and Q p. The conversion table, K-maps, and the logic diagram are given below. y 3/Engg/SE/Pre Pap/23/CMPN/DLDA_Soln 3
14 : S.E. DLDA J-K Flip Flop to T Flip-Flop 5. (a) Conversion Table T input Outputs J-K inputs Q p Q p + J K (i) Firstly we have to prepare a table where we have binary (4 bitts, B 3 B 2 B B ) inputs and gray (4 bits G 3 G 2 G G ) outputs (ii) Truth table is, (iii) Now the next step is very simple. You draw Kmaps for G 3, G 2, G and G separately. 4 3/Engg/SE/Pre Pap/23/CMPN/DLDA_Soln
15 Prelim Question Paper Solution (iv) Kmaps : (v) Circuit : ) A shift register which can shift the data in only one direction is called as a unidirectional shift register. 2) A shift register which can shift the data in both the directions is called as a bidirectional shift register. 3) Applying the same logic, a shift register which can shift the data in both the directions (shift right or left) as well as load it parallely, then it is called as a universal shift register. 5. (b) 3/Engg/SE/Pre Pap/23/CMPN/DLDA_Soln 5
16 : S.E. DLDA Figure shows the logic diagram of a universal shift register. This shift register is capable of performing the following operations : ) Parallel loading (parallel input parallel output) 2) Left shifting 3) Right shifting The Mode control input is connected to Logic for parallel loading operation whereas it is connected to for serial shifting. With mode control pin connected to ground, the universal shift register acts as a bi-directional register. For serial left operation, the input is applied to the serial input which goes to AND gate- in Figure. Whereas for the shift right operation, the serial input is applied to D input (input of AND gate 8). The well-known example of universal shift register in the IC form is IC7495. Fig. : Logic diagram of a universal shift register 4) Universal Shift Register IC 7495 : General description : IC 7495 is a TTL MSI shift register. It is a 4-bit shift register with serial and parallel synchronous operating modes. Because of its capability to operate in all the possible modes, it is called as a universal shift register. 6 3/Engg/SE/Pre Pap/23/CMPN/DLDA_Soln
17 Prelim Question Paper Solution Serial Shift Right Operation The connection diagram for serial shift right mode is shown in Figure 2. Make mode control =, therefore AND gates, 3, 5, 7 will be enabled and AND gate 2, 4, 6, 8 will get disabled. Hence the ABCD inputs become don t care. The data input to FF-A is now the serial input. Clock 2 input is don t care. This is because AND gate 9 is enabled and gate is disabled. Apply CLOCK input to clock. A HIGH to low transition on enabled clock input transfers data serially from serial input to Q A, Q A to Q B, Q B to Q C to Q D respectively (right shift). Serial Shift Left Operation The connection diagram of 7495 for the shift left operation is shown in figure 3. Note that Q D is connected to C, Q C to B and Q B to A and the serial data is applied at input D. Clock Serial input 9 CLK Q A Q B Q C Q D 3 2 Fig. 3: 7495 connected for serial shift left operation Mode control is connected to. Hence the AND gates 2, 4, 6, 8 are enabled whereas, 3, 5 and 7 are disabled. This will make the serial input (pin no. ) a don t care input. The serial data is applied to D which will be routed through the enabled AND gates 2, 4, 6, 8 to facilitate the right shifting operation. As M =, AND gate is enabled and gate 9 is disabled. So clock becomes a don t care input. Apply clock pulses to CLK 2 (shift left). Each high to low transition of clock will transfer data from D to Q D, Q D to Q C, Q C to Q B and Q B to Q A. Thus the shift left operation is performed. 6 Mode control = Direction of data shifting Fig. 2: 7495 connected for serial right shifting CLK A Q B B Q B C Q D M D +V CC Mode control = Serial input 3/Engg/SE/Pre Pap/23/CMPN/DLDA_Soln 7
18 : S.E. DLDA 6. (a) High Speed CMOS The high speed CMOS devices have silicon gates instead of metal gates. This improved version of CMOS ICs has higher switching speeds and higher output current capacity. The high speed CMOS devices are pin compatible and functionally equivalent to TTL ICs with the same device numbers. Comparison of CMOS and TTL Families Parameter CMOS TTL Silicon gate Metal gate 74 74LS 74AS 74ALS CMOS CMOS V IH (min) V IL (max) V OH (min) V OL (max) V NH V NL Propagation Delay (ns) Power per gate (mw) Speed power product or figure or merit.4 pj.5 pj pj 2 pj 2.8 pj 4 pj Input connection Input cannot be left open. It Input can be left open. It is has to be connected to, or treated as logic high input. to V DD or to the another input. More than CMOS. It is Power Very less, but increases with constant, does not depend dissipation increase in switching speed on switching speed. Fan out Fanout is more than TTL typically 5 Fanout for TTL is. Noise More susceptible to noise Less susceptible to noise. 6. (b) De Morgan's theorem : The two theorems suggested by De-Morgen and which are extremely useful in Boolean algebra are as follows : Theorem : AB A B : NAND = Bubbled OR This theorem states that the complement of a product is equal to addition of the complements. This rule is illustrated Fig.. The left hand side (LHS) of this theorem represents a NAND gate with inputs A and B whereas the right hand side (RHS) of the theorem represents an OR gate with inverted inputs. This OR gate is called as "Bubbled OR". Thus we can state De-Morgans first theorem as, NAND = Bubbled OR 8 3/Engg/SE/Pre Pap/23/CMPN/DLDA_Soln
19 Prelim Question Paper Solution Fig. : Illustration of De-Morgan's first theorem. This theorem can be verified by writing a truth table as shown in Fig.2. A B AB A B A B LHS AB A B RHS Fig. 2 : Verification of the theorem AB A B Theorem 2 : AB A.B : NOR = Bubbled AND The LHS of this theorem represents a NOR gate with inputs A and B whereas the RHS represents an AND gate with inverted inputs. This AND gate is called as "Bubbled AND". Thus we can state De-Morgan's second theorem as : NOR = Bubbled AND Fig. 3 : Illustration of De-Morgan's second theorem. This theorem can be verified by writing a truth table for both the sides of the theorem statement. This truth table is shown in Fig. 4, which shows that LHS = RHS. A B A B A B A.B LHS ABA.B RHS Fig.4 : Truth table to verify De-Morgan's theorem 3/Engg/SE/Pre Pap/23/CMPN/DLDA_Soln 9
20 : S.E. DLDA 6. (c) Difference between CPLDs & FPGAs CPLDs FPGAs Architecture Large, wide fan-in blocks of AND-OR logic Array of small logic blocks surrounded by I/O Applications Bus interfaces complex state machines fast memory interfaces wide decoders PAL-device integration Logic consolidation board integration replace obsolete devices simple state machines complex controllers / interfaces Key Attributes Fast pin-to-pin performance Predictable timing Easy to use Very high density lots of I/Os and flip-flops generally lower power SRAM devices are reprogrammable. Gate Capacity 3-6, gates 8-, gates Design Timing Fixed, PAL-like very fast pinto-pin performance Application dependent very high shift frequencies Number of I/Os Number of Flip-flops Process Technology In-System Programmable One-Time Programmable (OTP) Power Consumption ,5 EPROM EEPROM FLASH Some EEPROM- and FLASH-based devices EPROM devices in plastic packages. Some EEPROMand FLASH-based devices.5-2.w static.5-4.w dynamic SRAM Anti-fuse EEPROM SRAM-based devices and some EEPROM-based devices All anti-fuse-based devices Very low static dynamic consumption is application dependent,.-2w typical 6. (d) () Canonical is a word used to describe a condition of a switching equation. In normal use the work means conforming to a general rule. The rule, for switching logic, is that each term used in a switching equation must contain all of the available input variables. Two formats generally exist for expressing switching equations in a canonical form: Sums of minterms and products of maxterms. (2) Canonical sum of products A canonical sum of products is a complete set of minterms that defines when an output variable is a logical. Each minterm corresponds to the row in the truth table where the output function is ; that is, the SOP for the output M is M = a bms + ab ms + abms (3) Canonical product of sums : A canonical product of sums is a complete set of maxterms that defines when an output is a logical. Each maxterm 2 3/Engg/SE/Pre Pap/23/CMPN/DLDA_Soln
21 Prelim Question Paper Solution corresponds to a row in the truth table where the output is a ; that is, the POS for the output O is O = (C + C 2 + C 3 ) (C + C 2 + C 3 ) (C + C 2 + C 3 ) (C + C 2 + C 3 ) (C + C 2 + C 3 ) (4) To place a SOP equation into canonical form using Boolean algebra, we do the following : (i) Identify the missing variable(s) in each AND term. (ii) AND the missing term and its complement with the original AND term, xy(z+z ). Because (Z+Z) =, the original AND term value is not changed. (iii) Expand the term by application of the property of distribution, xyz+xyz. (5) To place POS equation into canonical form using Boolean algebra, we do this : (i) Identify the mission variable(s) in each OR term. (ii) OR the missing term(s) and its complement with the original OR term, x+y+zz. Because zz =, the original OR term value is not changed. (iii) Expand the term by application of distributive property, (x+y+z)(x+y+z). (6) P = f(a, b, c) = ab + ac + bc (SOP) (i) First term, ab, is missing the variable c. So we AND (c+c) with ab: ab = ab (c + c) = abc + abc (ii) Second term, ac, is missing the variable b. So we AND (b+b) with ac. ac = ac (b+b) = abc + abc (iii) Third term is missing the variable a. So we AND (a+a) with bc. bc = bc (a+a) = abc + abc (iv) The final canonical SOP form is P = abc + abc + abc + abc + abc + abc Note that two terms, the second and the fourth, are identical. Only one is needed, because any variable or group of variables ORed with itself is redundant : x + x = x (property of idempotency or sameness). The final equation becomes P = abc + abc + abc + abc + abc (7) (c) T = f(a,b,c) = (a + b)(b + c) (POS) (i) The variable c is missing from the first term. a + b + cc = (a + b + c)(a + b + c) (ii) The variable a is missing from the second term. b + c + aa = (a + b + c)(a + b + c) (iii) The complete equation is T = f(a, b, c) = (a + b + c)(a + b + c)(a + b + c) Features of VHDL (Derived from Capabilities) VHDL has powerful constructs VHDL language supports hierarchy (i.e modelled using a set of interconnected components) 6. (e) 3/Engg/SE/Pre Pap/23/CMPN/DLDA_Soln 2
22 : S.E. DLDA VHDL is not case sensitive VHDL supports both synchronous and asynchronous timing models. Concurrency timing and clocking can be modeled using VHDL VHDL is target independent VHDL supports design library VHDL has flexible design methodologies i.e. TOP DOWN, BOTTOM UP, MIXED The logical behavior and timing behavior of the design can be modeled using VHDL. VHDL is not technology specific i.e. VHDL is not dependent on the specific manufacturer i.e. XILINX or LATTICE. VHDL s technology specific feature allows to specify components from various vendors VHDL also allows the user to specify his own data type and component VHDL is publicly available and has no proprietary. 22 3/Engg/SE/Pre Pap/23/CMPN/DLDA_Soln
Vidyalankar S.E. Sem. III [EXTC] Digital Electronics Prelim Question Paper Solution ABCD ABCD ABCD ABCD ABCD ABCD ABCD ABCD = B
. (a). (b). (c) S.E. Sem. III [EXTC] igital Electronics Prelim Question Paper Solution ABC ABC ABC ABC ABC ABC ABC ABC = B LHS = ABC ABC ABC ABC ABC ABC ABC ABC But ( ) = = ABC( ) ABC( ) ABC( ) ABC( )
More informationKUMARAGURU COLLEGE OF TECHNOLOGY COIMBATORE
Estd-1984 KUMARAGURU COLLEGE OF TECHNOLOGY COIMBATORE 641 006 QUESTION BANK UNIT I PART A ISO 9001:2000 Certified 1. Convert (100001110.010) 2 to a decimal number. 2. Find the canonical SOP for the function
More informationVidyalankar S.E. Sem. III [ETRX] Digital Circuits and Design Prelim Question Paper Solution
S.E. Sem. III [ETRX] Digital Circuits and Design Prelim uestion Paper Solution. (a) Static Hazard Static hazards have two cases: static and static. static- hazard exists when the output variable should
More informationVidyalankar. S.E. Sem. III [EXTC] Digital System Design. Q.1 Solve following : [20] Q.1(a) Explain the following decimals in gray code form
S.E. Sem. III [EXTC] Digital System Design Time : 3 Hrs.] Prelim Paper Solution [Marks : 80 Q.1 Solve following : [20] Q.1(a) Explain the following decimals in gray code form [5] (i) (42) 10 (ii) (17)
More informationSample Test Paper - I
Scheme G Sample Test Paper - I Course Name : Computer Engineering Group Marks : 25 Hours: 1 Hrs. Q.1) Attempt any THREE: 09 Marks a) Define i) Propagation delay ii) Fan-in iii) Fan-out b) Convert the following:
More informationvidyarthiplus.com vidyarthiplus.com vidyarthiplus.com ANNA UNIVERSITY- COMBATORE B.E./ B.TECH. DEGREE EXAMINATION - JUNE 2009. ELECTRICAL & ELECTONICS ENGG. - FOURTH SEMESTER DIGITAL LOGIC CIRCUITS PART-A
More informationS.E. Sem. III [ETRX] Digital Circuit Design. t phl. Fig.: Input and output voltage waveforms to define propagation delay times.
S.E. Sem. III [ETRX] Digital ircuit Design Time : 3 Hrs.] Prelim Paper Solution [Marks : 80. Solve following : [20].(a) Explain characteristics of logic families. [5] haracteristics of logic families are
More information( c) Give logic symbol, Truth table and circuit diagram for a clocked SR flip-flop. A combinational circuit is defined by the function
Question Paper Digital Electronics (EE-204-F) MDU Examination May 2015 1. (a) represent (32)10 in (i) BCD 8421 code (ii) Excess-3 code (iii) ASCII code (b) Design half adder using only NAND gates. ( c)
More informationS.Y. Diploma : Sem. III [DE/ED/EI/EJ/EN/ET/EV/EX/IC/IE/IS/IU/MU] Principles of Digital Techniques
S.Y. Diploma : Sem. III [DE/ED/EI/EJ/EN/ET/EV/EX/IC/IE/IS/IU/MU] Principles of Digital Techniques Time: 3 Hrs.] Prelim Question Paper Solution [Marks : 100 Q.1(a) Attempt any SIX of the following : [12]
More informationCS470: Computer Architecture. AMD Quad Core
CS470: Computer Architecture Yashwant K. Malaiya, Professor malaiya@cs.colostate.edu AMD Quad Core 1 Architecture Layers Building blocks Gates, flip-flops Functional bocks: Combinational, Sequential Instruction
More informationDepartment of Electrical & Electronics EE-333 DIGITAL SYSTEMS
Department of Electrical & Electronics EE-333 DIGITAL SYSTEMS 1) Given the two binary numbers X = 1010100 and Y = 1000011, perform the subtraction (a) X -Y and (b) Y - X using 2's complements. a) X = 1010100
More informationMAHARASHTRA STATE BOARD OF TECHNICAL EDUCATION (Autonomous) (ISO/IEC Certified)
WINTER 17 EXAMINATION Subject Name: Digital Techniques Model Answer Subject Code: 17333 Important Instructions to examiners: 1) The answers should be examined by key words and not as word-to-word as given
More informationon candidate s understanding. 7) For programming language papers, credit may be given to any other program based on equivalent concept.
WINTER 17 EXAMINATION Subject Name: Digital Techniques Model Answer Subject Code: 17333 Important Instructions to examiners: 1) The answers should be examined by key words and not as word-to-word as given
More informationReg. No. Question Paper Code : B.E./B.Tech. DEGREE EXAMINATION, NOVEMBER/DECEMBER Second Semester. Computer Science and Engineering
Sp 6 Reg. No. Question Paper Code : 27156 B.E./B.Tech. DEGREE EXAMINATION, NOVEMBER/DECEMBER 2015. Second Semester Computer Science and Engineering CS 6201 DIGITAL PRINCIPLES AND SYSTEM DESIGN (Common
More informationEE40 Lec 15. Logic Synthesis and Sequential Logic Circuits
EE40 Lec 15 Logic Synthesis and Sequential Logic Circuits Prof. Nathan Cheung 10/20/2009 Reading: Hambley Chapters 7.4-7.6 Karnaugh Maps: Read following before reading textbook http://www.facstaff.bucknell.edu/mastascu/elessonshtml/logic/logic3.html
More informationLOGIC CIRCUITS. Basic Experiment and Design of Electronics. Ho Kyung Kim, Ph.D.
Basic Experiment and Design of Electronics LOGIC CIRCUITS Ho Kyung Kim, Ph.D. hokyung@pusan.ac.kr School of Mechanical Engineering Pusan National University Digital IC packages TTL (transistor-transistor
More information3 Logic Function Realization with MSI Circuits
3 Logic Function Realization with MSI Circuits Half adder A half-adder is a combinational circuit with two binary inputs (augund and addend bits) and two binary outputs (sum and carry bits). It adds the
More informationSAU1A FUNDAMENTALS OF DIGITAL COMPUTERS
SAU1A FUNDAMENTALS OF DIGITAL COMPUTERS Unit : I - V Unit : I Overview Fundamentals of Computers Characteristics of Computers Computer Language Operating Systems Generation of Computers 2 Definition of
More informationS.Y. Diploma : Sem. III [CO/CM/IF/CD/CW] Digital Techniques
S.Y. Diploma : Sem. III [CO/CM/IF/CD/CW] Digital Techniques Time: 3 Hrs.] Prelim Question Paper Solution [Marks : 100 Q.1(a) Attempt any SIX of the following : [12] Q.1(a) (i) Derive AND gate and OR gate
More informationFundamentals of Boolean Algebra
UNIT-II 1 Fundamentals of Boolean Algebra Basic Postulates Postulate 1 (Definition): A Boolean algebra is a closed algebraic system containing a set K of two or more elements and the two operators and
More informationDHANALAKSHMI COLLEGE OF ENGINEERING, CHENNAI DEPARTMENT OF COMPUTER SCIENCE AND ENGINEERING CS6201 DIGITAL PRINCIPLES AND SYSTEM DESIGN
DHANALAKSHMI COLLEGE OF ENGINEERING, CHENNAI DEPARTMENT OF COMPUTER SCIENCE AND ENGINEERING CS6201 DIGITAL PRINCIPLES AND SYSTEM DESIGN UNIT I : BOOLEAN ALGEBRA AND LOGIC GATES PART - A (2 MARKS) Number
More informationDIGITAL LOGIC CIRCUITS
DIGITAL LOGIC CIRCUITS Introduction Logic Gates Boolean Algebra Map Specification Combinational Circuits Flip-Flops Sequential Circuits Memory Components Integrated Circuits Digital Computers 2 LOGIC GATES
More informationMAHARASHTRA STATE BOARD OF TECHNICAL EDUCATION (Autonomous) (ISO/IEC Certified) State any two Boolean laws. (Any 2 laws 1 mark each)
Subject Code: 17333 Model Answer Page 1/ 27 Important Instructions to examiners: 1) The answers should be examined by key words and not as word-to-word as given in the model answer scheme. 2) The model
More informationBoolean Algebra and Digital Logic 2009, University of Colombo School of Computing
IT 204 Section 3.0 Boolean Algebra and Digital Logic Boolean Algebra 2 Logic Equations to Truth Tables X = A. B + A. B + AB A B X 0 0 0 0 3 Sum of Products The OR operation performed on the products of
More informationSIR C.R.REDDY COLLEGE OF ENGINEERING ELURU DIGITAL INTEGRATED CIRCUITS (DIC) LABORATORY MANUAL III / IV B.E. (ECE) : I - SEMESTER
SIR C.R.REDDY COLLEGE OF ENGINEERING ELURU 534 007 DIGITAL INTEGRATED CIRCUITS (DIC) LABORATORY MANUAL III / IV B.E. (ECE) : I - SEMESTER DEPARTMENT OF ELECTRONICS AND COMMUNICATION ENGINEERING DIGITAL
More informationLOGIC CIRCUITS. Basic Experiment and Design of Electronics
Basic Experiment and Design of Electronics LOGIC CIRCUITS Ho Kyung Kim, Ph.D. hokyung@pusan.ac.kr School of Mechanical Engineering Pusan National University Outline Combinational logic circuits Output
More informationSUMMER 18 EXAMINATION Subject Name: Principles of Digital Techniques Model Answer Subject Code:
Important Instructions to examiners: 1) The answers should be examined by key words and not as word-to-word as given in the model answer scheme. 2) The model answer and the answer written by candidate
More informationSection 3: Combinational Logic Design. Department of Electrical Engineering, University of Waterloo. Combinational Logic
Section 3: Combinational Logic Design Major Topics Design Procedure Multilevel circuits Design with XOR gates Adders and Subtractors Binary parallel adder Decoders Encoders Multiplexers Programmed Logic
More informationVidyalankar S.E. Sem. III [INFT] Analog and Digital Circuits Prelim Question Paper Solution
. (a). (b) S.E. Sem. III [INFT] Analog and Digital Circuits Prelim Question Paper Solution Practical Features of OpAmp (A 74) i) Large voltage gain (of the order of 2 0 5 ) ii) Very high input resistance
More informationELECTRONICS & COMMUNICATION ENGINEERING PROFESSIONAL ETHICS AND HUMAN VALUES
EC 216(R-15) Total No. of Questions :09] [Total No. of Pages : 02 II/IV B.Tech. DEGREE EXAMINATIONS, DECEMBER- 2016 First Semester ELECTRONICS & COMMUNICATION ENGINEERING PROFESSIONAL ETHICS AND HUMAN
More informationCHAPTER 7. Exercises 17/ / /2 2 0
CHAPTER 7 Exercises E7. (a) For the whole part, we have: Quotient Remainders 23/2 /2 5 5/2 2 2/2 0 /2 0 Reading the remainders in reverse order, we obtain: 23 0 = 0 2 For the fractional part we have 2
More informationMODEL ANSWER SUMMER 17 EXAMINATION Subject Title: Principles of Digital Techniques
MODEL ANSWER SUMMER 17 EXAMINATION Subject Title: Principles of Digital Techniques Subject Code: Important Instructions to examiners: 1) The answers should be examined by key words and not as word-to-word
More informationCHW 261: Logic Design
CHW 26: Logic Design Instructors: Prof. Hala Zayed Dr. Ahmed Shalaby http://www.bu.edu.eg/staff/halazayed4 http://bu.edu.eg/staff/ahmedshalaby4# Slide Digital Fundamentals Digital Concepts Slide 2 What?
More informationMAHARASHTRA STATE BOARD OF TECHNICAL EDUCATION
MAHARASHTRA STATE BOARD OF TECHNICAL EDUCATION (Autonomous) (ISO/IEC - 27001-2005 Certified) Subject Code: 12069 SUMMER 13 EXAMINATION Model Answer Important Instructions to examiners: 1) The answers should
More informationDE58/DC58 LOGIC DESIGN DEC 2014
Q.2 a. In a base-5 number system, 3 digit representations is used. Find out (i) Number of distinct quantities that can be represented.(ii) Representation of highest decimal number in base-5. Since, r=5
More informationChapter 7 Logic Circuits
Chapter 7 Logic Circuits Goal. Advantages of digital technology compared to analog technology. 2. Terminology of Digital Circuits. 3. Convert Numbers between Decimal, Binary and Other forms. 5. Binary
More informationPART-A. 2. Expand ASCII and BCD ASCII American Standard Code for Information Interchange BCD Binary Coded Decimal
PART-A 1. What is radix? Give the radix for binary, octal, decimal and hexadecimal Radix is the total number of digits used in a particular number system Binary - 2 (0,1) Octal - 8 (0 to 7) Decimal - 10
More informationShow that the dual of the exclusive-or is equal to its compliment. 7
Darshan Institute of ngineering and Technology, Rajkot, Subject: Digital lectronics (2300) GTU Question ank Unit Group Questions Do as directed : I. Given that (6)0 = (00)x, find the value of x. II. dd
More informationDigital Electronics Circuits 2017
JSS SCIENCE AND TECHNOLOGY UNIVERSITY Digital Electronics Circuits (EC37L) Lab in-charge: Dr. Shankraiah Course outcomes: After the completion of laboratory the student will be able to, 1. Simplify, design
More informationBoolean Algebra. Digital Logic Appendix A. Postulates, Identities in Boolean Algebra How can I manipulate expressions?
Digital Logic Appendix A Gates Combinatorial Circuits Sequential Circuits Other operations NAND A NAND B = NOT ( A ANDB) = AB NOR A NOR B = NOT ( A ORB) = A + B Truth tables What is the result of the operation
More informationDigital Logic Appendix A
Digital Logic Appendix A Boolean Algebra Gates Combinatorial Circuits Sequential Circuits 1 Boolean Algebra George Boole ideas 1854 Claude Shannon, apply to circuit design, 1938 Describe digital circuitry
More information211: Computer Architecture Summer 2016
211: Computer Architecture Summer 2016 Liu Liu Topic: Storage Project3 Digital Logic - Storage: Recap - Review: cache hit rate - Project3 - Digital Logic: - truth table => SOP - simplification: Boolean
More informationFor smaller NRE cost For faster time to market For smaller high-volume manufacturing cost For higher performance
University of California at Berkeley College of Engineering Department of Electrical Engineering and Computer Sciences EECS5 J. Wawrzynek Spring 22 2/22/2. [2 pts] Short Answers. Midterm Exam I a) [2 pts]
More informationCPE/EE 422/522. Chapter 1 - Review of Logic Design Fundamentals. Dr. Rhonda Kay Gaede UAH. 1.1 Combinational Logic
CPE/EE 422/522 Chapter - Review of Logic Design Fundamentals Dr. Rhonda Kay Gaede UAH UAH Chapter CPE/EE 422/522. Combinational Logic Combinational Logic has no control inputs. When the inputs to a combinational
More informationWritten exam with solutions IE Digital Design Friday 21/
Written exam with solutions IE204-5 Digital Design Friday 2/0 206 09.00-3.00 General Information Examiner: Ingo Sander. Teacher: Kista, William Sandvist tel 08-7904487, Elena Dubrova phone 08-790 4 4 Exam
More informationBoolean Algebra. Digital Logic Appendix A. Boolean Algebra Other operations. Boolean Algebra. Postulates, Identities in Boolean Algebra
Digital Logic Appendix A Gates Combinatorial Circuits Sequential Circuits George Boole ideas 1854 Claude Shannon, apply to circuit design, 1938 (piirisuunnittelu) Describe digital circuitry function programming
More informationLecture A: Logic Design and Gates
Lecture A: Logic Design and Gates Syllabus My office hours 9.15-10.35am T,Th or gchoi@ece.tamu.edu 333G WERC Text: Brown and Vranesic Fundamentals of Digital Logic,» Buy it.. Or borrow it» Other book:
More informationWritten reexam with solutions for IE1204/5 Digital Design Monday 14/
Written reexam with solutions for IE204/5 Digital Design Monday 4/3 206 4.-8. General Information Examiner: Ingo Sander. Teacher: William Sandqvist phone 08-7904487 Exam text does not have to be returned
More informationDept. of ECE, CIT, Gubbi Page 1
Verification: 1) A.B = A + B 7404 7404 7404 A B A.B A.B 0 0 0 1 0 1 0 1 1 0 0 1 1 1 1 0 A B A B A + B 0 0 1 1 1 0 1 1 0 1 1 0 0 1 1 1 1 0 0 0 2) A+B = A. B 7404 7404 7404 A B A+B A+B 0 0 0 1 0 1 1 0 1
More informationReview for Test 1 : Ch1 5
Review for Test 1 : Ch1 5 October 5, 2006 Typeset by FoilTEX Positional Numbers 527.46 10 = (5 10 2 )+(2 10 1 )+(7 10 0 )+(4 10 1 )+(6 10 2 ) 527.46 8 = (5 8 2 ) + (2 8 1 ) + (7 8 0 ) + (4 8 1 ) + (6 8
More informationDigital Logic: Boolean Algebra and Gates. Textbook Chapter 3
Digital Logic: Boolean Algebra and Gates Textbook Chapter 3 Basic Logic Gates XOR CMPE12 Summer 2009 02-2 Truth Table The most basic representation of a logic function Lists the output for all possible
More informationUnit 2 Session - 6 Combinational Logic Circuits
Objectives Unit 2 Session - 6 Combinational Logic Circuits Draw 3- variable and 4- variable Karnaugh maps and use them to simplify Boolean expressions Understand don t Care Conditions Use the Product-of-Sums
More informationPhiladelphia University Student Name: Student Number:
Philadelphia University Student Name: Student Number: Faculty of Engineering Serial Number: Final Exam, First Semester: 2017/2018 Dept. of Computer Engineering Course Title: Logic Circuits Date: 29/01/2018
More informationMAHARASHTRA STATE BOARD OF TECHNICAL EDUCATION (Autonomous) (ISO/IEC Certified) SUMMER 14 EXAMINATION Model Answer
MAHARASHTRA STATE BOARD OF TECHNICAL EDUCATION (Autonomous) (ISO/IEC 27001 2005 Certified) SUMMER 14 EXAMINATION Model Answer Subject Code : 17320 Page No: 1/34 Important Instructions to examiners: 1)
More informationReview for B33DV2-Digital Design. Digital Design
Review for B33DV2 The Elements of Modern Behaviours Design Representations Blocks Waveforms Gates Truth Tables Boolean Algebra Switches Rapid Prototyping Technologies Circuit Technologies TTL MOS Simulation
More informationUnit 3 Session - 9 Data-Processing Circuits
Objectives Unit 3 Session - 9 Data-Processing Design of multiplexer circuits Discuss multiplexer applications Realization of higher order multiplexers using lower orders (multiplexer trees) Introduction
More informationFundamentals of Computer Systems
Fundamentals of Computer Systems Review for the Final Stephen A. Edwards Columbia University Summer 25 The Final 2 hours 8 problems Closed book Simple calculators are OK, but unnecessary One double-sided
More informationChap 2. Combinational Logic Circuits
Overview 2 Chap 2. Combinational Logic Circuits Spring 24 Part Gate Circuits and Boolean Equations Binary Logic and Gates Boolean Algebra Standard Forms Part 2 Circuit Optimization Two-Level Optimization
More informationLab 3 Revisited. Zener diodes IAP 2008 Lecture 4 1
Lab 3 Revisited Zener diodes R C 6.091 IAP 2008 Lecture 4 1 Lab 3 Revisited +15 Voltage regulators 555 timers 270 1N758 0.1uf 5K pot V+ V- 2N2222 0.1uf V o. V CC V Vin s = 5 V Vc V c Vs 1 e t = RC Threshold
More informationUnit II Chapter 4:- Digital Logic Contents 4.1 Introduction... 4
Unit II Chapter 4:- Digital Logic Contents 4.1 Introduction... 4 4.1.1 Signal... 4 4.1.2 Comparison of Analog and Digital Signal... 7 4.2 Number Systems... 7 4.2.1 Decimal Number System... 7 4.2.2 Binary
More informationChapter 2 Boolean Algebra and Logic Gates
Chapter 2 Boolean Algebra and Logic Gates The most common postulates used to formulate various algebraic structures are: 1. Closure. N={1,2,3,4 }, for any a,b N we obtain a unique c N by the operation
More informationDIGITAL LOGIC CIRCUITS
DIGITAL LOGIC CIRCUITS Introduction Logic Gates Boolean Algebra Map Specification Combinational Circuits Flip-Flops Sequential Circuits Memor Components Integrated Circuits BASIC LOGIC BLOCK - GATE - Logic
More informationCSC9R6 Computer Design. Practical Digital Logic
CSC9R6 Computer Design Practical Digital Logic 1 References (for this part of CSC9R6) Hamacher et al: Computer Organization App A. In library Floyd: Digital Fundamentals Ch 1, 3-6, 8-10 web page: www.prenhall.com/floyd/
More informationSynchronous Sequential Logic
1 IT 201 DIGITAL SYSTEMS DESIGN MODULE4 NOTES Synchronous Sequential Logic Sequential Circuits - A sequential circuit consists of a combinational circuit and a feedback through the storage elements in
More informationChapter 2 (Lect 2) Canonical and Standard Forms. Standard Form. Other Logic Operators Logic Gates. Sum of Minterms Product of Maxterms
Chapter 2 (Lect 2) Canonical and Standard Forms Sum of Minterms Product of Maxterms Standard Form Sum of products Product of sums Other Logic Operators Logic Gates Basic and Multiple Inputs Positive and
More informationProgrammable Logic Devices
Programmable Logic Devices Mohammed Anvar P.K AP/ECE Al-Ameen Engineering College PLDs Programmable Logic Devices (PLD) General purpose chip for implementing circuits Can be customized using programmable
More informationChapter 2 Boolean Algebra and Logic Gates
Ch1: Digital Systems and Binary Numbers Ch2: Ch3: Gate-Level Minimization Ch4: Combinational Logic Ch5: Synchronous Sequential Logic Ch6: Registers and Counters Switching Theory & Logic Design Prof. Adnan
More informationCPE100: Digital Logic Design I
Professor Brendan Morris, SEB 3216, brendan.morris@unlv.edu CPE100: Digital Logic Design I Midterm02 Review http://www.ee.unlv.edu/~b1morris/cpe100/ 2 Logistics Thursday Nov. 16 th In normal lecture (13:00-14:15)
More informationWORKBOOK. Try Yourself Questions. Electrical Engineering Digital Electronics. Detailed Explanations of
27 WORKBOOK Detailed Eplanations of Try Yourself Questions Electrical Engineering Digital Electronics Number Systems and Codes T : Solution Converting into decimal number system 2 + 3 + 5 + 8 2 + 4 8 +
More informationECEN 248: INTRODUCTION TO DIGITAL SYSTEMS DESIGN. Week 9 Dr. Srinivas Shakkottai Dept. of Electrical and Computer Engineering
ECEN 248: INTRODUCTION TO DIGITAL SYSTEMS DESIGN Week 9 Dr. Srinivas Shakkottai Dept. of Electrical and Computer Engineering TIMING ANALYSIS Overview Circuits do not respond instantaneously to input changes
More informationFundamentals of Computer Systems
Fundamentals of Computer Systems Review for the Midterm Stephen A. Edwards Columbia University Spring 22 The Midterm 75 minutes 4 5 problems Closed book Simple calculators are OK, but unnecessary One double-sided
More informationL2: Combinational Logic Design (Construction and Boolean Algebra)
L2: Combinational Logic Design (Construction and Boolean Algebra) Acknowledgements: Lecture material adapted from Chapter 2 of R. Katz, G. Borriello, Contemporary Logic Design (second edition), Pearson
More informationWritten exam for IE1204/5 Digital Design with solutions Thursday 29/
Written exam for IE4/5 Digital Design with solutions Thursday 9/ 5 9.-. General Information Examiner: Ingo Sander. Teacher: William Sandqvist phone 8-794487 Exam text does not have to be returned when
More informationDigital Logic. CS211 Computer Architecture. l Topics. l Transistors (Design & Types) l Logic Gates. l Combinational Circuits.
CS211 Computer Architecture Digital Logic l Topics l Transistors (Design & Types) l Logic Gates l Combinational Circuits l K-Maps Figures & Tables borrowed from:! http://www.allaboutcircuits.com/vol_4/index.html!
More informationCHAPTER III BOOLEAN ALGEBRA
CHAPTER III- CHAPTER III CHAPTER III R.M. Dansereau; v.. CHAPTER III-2 BOOLEAN VALUES INTRODUCTION BOOLEAN VALUES Boolean algebra is a form of algebra that deals with single digit binary values and variables.
More informationEC-121 Digital Logic Design
EC-121 Digital Logic Design Lecture 2 [Updated on 02-04-18] Boolean Algebra and Logic Gates Dr Hashim Ali Spring 2018 Department of Computer Science and Engineering HITEC University Taxila!1 Overview What
More informationComputer Science Final Examination Friday December 14 th 2001
Computer Science 03 60 265 Final Examination Friday December 14 th 2001 Dr. Robert D. Kent and Dr. Alioune Ngom Last Name: First Name: Student Number: INSTRUCTIONS EXAM DURATION IS 3 HOURs. CALCULATORS,
More informationMAHALAKSHMI ENGINEERING COLLEGE TIRUCHIRAPALLI
MAHALAKSHMI ENGINEERING COLLEGE TIRUCHIRAPALLI 6 DEPARTMENT: EEE QUESTION BANK SUBJECT NAME: DIGITAL LOGIC CIRCUITS SUBJECT CODE: EE55 SEMESTER IV UNIT : Design of Synchronous Sequential Circuits PART
More informationNTE74HC109 Integrated Circuit TTL High Speed CMOS, Dual J K Positive Edge Triggered Flip Flop w/set & Reset
NTE74HC109 Integrated Circuit TTL High Speed CMOS, Dual J K Positive Edge Triggered Flip Flop w/set & Reset Description: The NTE74HC109 is a dual J K flip flip with set and reset in a 16 Lead plastic DIP
More informationSequential Logic. Rab Nawaz Khan Jadoon DCS. Lecturer COMSATS Lahore Pakistan. Department of Computer Science
Sequential Logic Rab Nawaz Khan Jadoon DCS COMSATS Institute of Information Technology Lecturer COMSATS Lahore Pakistan Digital Logic and Computer Design Sequential Logic Combinational circuits with memory
More informationKing Fahd University of Petroleum and Minerals College of Computer Science and Engineering Computer Engineering Department
King Fahd University of Petroleum and Minerals College of Computer Science and Engineering Computer Engineering Department Page of COE 22: Digital Logic Design (3--3) Term (Fall 22) Final Exam Sunday January
More informationELEC Digital Logic Circuits Fall 2014 Sequential Circuits (Chapter 6) Finite State Machines (Ch. 7-10)
ELEC 2200-002 Digital Logic Circuits Fall 2014 Sequential Circuits (Chapter 6) Finite State Machines (Ch. 7-10) Vishwani D. Agrawal James J. Danaher Professor Department of Electrical and Computer Engineering
More informationNumber System conversions
Number System conversions Number Systems The system used to count discrete units is called number system. There are four systems of arithmetic which are often used in digital electronics. Decimal Number
More informationChapter 2. Review of Digital Systems Design
x 2-4 = 42.625. Chapter 2 Review of Digital Systems Design Numbering Systems Decimal number may be expressed as powers of 10. For example, consider a six digit decimal number 987654, which can be represented
More information3. Complete the following table of equivalent values. Use binary numbers with a sign bit and 7 bits for the value
EGC22 Digital Logic Fundamental Additional Practice Problems. Complete the following table of equivalent values. Binary. Octal 35.77 33.23.875 29.99 27 9 64 Hexadecimal B.3 D.FD B.4C 2. Calculate the following
More informationMODULAR CIRCUITS CHAPTER 7
CHAPTER 7 MODULAR CIRCUITS A modular circuit is a digital circuit that performs a specific function or has certain usage. The modular circuits to be introduced in this chapter are decoders, encoders, multiplexers,
More informationUNIT II COMBINATIONAL CIRCUITS:
UNIT II COMBINATIONAL CIRCUITS: INTRODUCTION: The digital system consists of two types of circuits, namely (i) (ii) Combinational circuits Sequential circuits Combinational circuit consists of logic gates
More information74LS195 SN74LS195AD LOW POWER SCHOTTKY
The SN74LS95A is a high speed 4-Bit Shift Register offering typical shift frequencies of 39 MHz. It is useful for a wide variety of register and counting applications. It utilizes the Schottky diode clamped
More informationChapter 4: Designing Combinational Systems Uchechukwu Ofoegbu
Chapter 4: Designing Combinational Systems Uchechukwu Ofoegbu Temple University Gate Delay ((1.1).1) ((1.0).0) ((0.1).1) ((0.1).0) ((1.1) = 1 0 s = sum c out carry-out a, b = added bits C = carry in a
More informationLecture 22 Chapters 3 Logic Circuits Part 1
Lecture 22 Chapters 3 Logic Circuits Part 1 LC-3 Data Path Revisited How are the components Seen here implemented? 5-2 Computing Layers Problems Algorithms Language Instruction Set Architecture Microarchitecture
More informationCPE100: Digital Logic Design I
Professor Brendan Morris, SEB 3216, brendan.morris@unlv.edu CPE100: Digital Logic Design I Final Review http://www.ee.unlv.edu/~b1morris/cpe100/ 2 Logistics Tuesday Dec 12 th 13:00-15:00 (1-3pm) 2 hour
More informationCHAPTER III BOOLEAN ALGEBRA
CHAPTER III- CHAPTER III CHAPTER III R.M. Dansereau; v.. CHAPTER III-2 BOOLEAN VALUES INTRODUCTION BOOLEAN VALUES Boolean algebra is a form of algebra that deals with single digit binary values and variables.
More informationPrinciples of Computer Architecture. Appendix B: Reduction of Digital Logic. Chapter Contents
B-1 Principles of Computer Architecture Miles Murdocca and Vincent Heuring Appendix B: Reduction of Digital Logic B-2 Chapter Contents B.1 Reduction of Combinational Logic and Sequential Logic B.2 Reduction
More informationCombinational Logic Design/Circuits
3 ` Combinational Logic Design/Circuits Chapter-3(Hours : 12 Marks:24 ) Combinational Logic design / Circuits 3.1 Simplification of Boolean expression using Boolean algebra. 3.2 Construction of logical
More informationDigital Electronics. Part A
Digital Electronics Final Examination Part A Winter 2004-05 Student Name: Date: lass Period: Total Points: Multiple hoice Directions: Select the letter of the response which best completes the item or
More informationNumber System. Decimal to binary Binary to Decimal Binary to octal Binary to hexadecimal Hexadecimal to binary Octal to binary
Number System Decimal to binary Binary to Decimal Binary to octal Binary to hexadecimal Hexadecimal to binary Octal to binary BOOLEAN ALGEBRA BOOLEAN LOGIC OPERATIONS Logical AND Logical OR Logical COMPLEMENTATION
More informationStandard & Canonical Forms
1 COE 202- Digital Logic Standard & Canonical Forms Dr. Abdulaziz Y. Barnawi COE Department KFUPM 2 Outline Minterms and Maxterms From truth table to Boolean expression Sum of minterms Product of Maxterms
More informationChapter 2 Combinational Logic Circuits
Logic and Computer Design Fundamentals Chapter 2 Combinational Logic Circuits Part 1 Gate Circuits and Boolean Equations Charles Kime & Thomas Kaminski 2008 Pearson Education, Inc. (Hyperlinks are active
More informationCh 9. Sequential Logic Technologies. IX - Sequential Logic Technology Contemporary Logic Design 1
Ch 9. Sequential Logic Technologies Technology Contemporary Logic Design Overview Basic Sequential Logic Components FSM Design with Counters FSM Design with Programmable Logic FSM Design with More Sophisticated
More informationLogic. Combinational. inputs. outputs. the result. system can
Digital Electronics Combinational Logic Functions Digital logic circuits can be classified as either combinational or sequential circuits. A combinational circuit is one where the output at any time depends
More information