EE40 Lec 15. Logic Synthesis and Sequential Logic Circuits
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1 EE40 Lec 15 Logic Synthesis and Sequential Logic Circuits Prof. Nathan Cheung 10/20/2009 Reading: Hambley Chapters Karnaugh Maps: Read following before reading textbook Slide 1
2 Synthesis of Logic Circuits Suppose we are given a truth table for a logic function. Is there a method to implement the logic function using basic logic gates? Answer: There are lots of ways, but one way is the sum of products (SOP) method: 1) Write the sum of products expression based on the truth table for the logic function 2) Implement this expression using standard logic gates. An alternative way is the product of sums (POS) method. Slide 2
3 Logic Synthesis Example: Adder S 1 = carry, S o =sum Truth Table of Adding Three Inputs : A, B, and C Slide 3 A B C S 1 S
4 Logic Synthesis Example: Adder Input Output Sum-of-products method for S 1 A B C S 1 S 0 1) Find rows where S 1 is ) Write down each product of inputs which create a 1 (invert A B C A B C A B C A B C logic variables that are 0 in that row) 1) Sum all of the products A B C + A B C + A B C + A B C 2) Draw the logic circuit Slide 4
5 Logic Synthesis Example: Adder A B C B C A C A B A B C A B C + A B C + A B C + A B C SOP Logic Circuit Slide 5
6 Creating a Better Circuit What makes a digital circuit better? Fewer number of gates Fewer inputs on each gate multi-input gates are slower Let s see how we can simplify the sum-of- products expression for S 1, to make a better circuit Use the Boolean algebra relations Slide 6
7 Logic Synthesis Example: Adder A B B C A C A B ABC + ABC + ABC + ABC = ABC + ABC + = ABC + ABC + AB(C + C) AB SOP Simplification Can we simplify this digital circuit further? Slide 7
8 Logic Synthesis Example: Adder A B B C A C A B Add in two inversions (signal stays the same) Slide 8
9 Logic Synthesis Example: Adder A B B C A C A B This becomes a NAND Apply DeMorgan s Theorem, i.e. bubble pushing X + Y + Z = XYZ Slide 9
10 NAND Gate Implementation De Morgan s law tells us that is the same as By definition, is the same as All sum-of-products expressions can be implemented with only NAND gates. Slide 10
11 Logic Synthesis Example: Adder Input Output A B C S 1 S Product-of-sums method for S 1 1) Find rows where S 1 is 0 2) Write down each sum of inputs which create a 0 (invert logic variables that are 1 in that row) which create a 0 (invert logic ( A + B + C) ( A + B + C ) ( A + B + C) ( A + B + C) 3) Product of the sums ( A + B + C)(A + B + C)(A + B + C)(A + B + C) 4) Draw the logic circuit Slide 11
12 SOP or POS? The Boolean Expression will appear shorter If the Truth table has less 1 s, SOP If the Truth Table has less 0 s s, POS After Minimization, both methods should give same results, unless there are don t care rows in the Truth Table. Slide 12
13 Notations of Hambley Textbook Sum of Products (SOP) Row # A B C D = (,,, ) D Σ m(0,2,6,7) Product of Sums (POS) D = Π M(1,3,4,5) Slide 13
14 Another Logic Synthesis Example: XOR Sum of Products (SOP) F = Σ m(1,2) F = A B + A B A B F Product of Sums (POS) F = Π M(0,3) F = (A + B)(A + B) Slide 14
15 Karnaugh Maps 2-variable Karnaugh Map 3-variable Karnaugh Map 4-variable Karnaugh Map * Arrows show example locations of logic PRODUCTS Slide 15
16 Comments on Karnaugh Maps Required reading L/Logic/Logic3.html You may find more details there than the textbook. As the number of variables increases (say >4) it becomes more difficult to see patterns, and computer methods start to become more attractive. EE40 will focus only on 3 variables and 4 variables Karnaugh Maps Slide 16
17 Comments on Karnaugh Maps For a 4-variables map 1-cube: 1 square by itself ( logic product of 4 variables) 2-cube: 2 squares that have a common edge ( logic product of 3 variables) 4-cube: 4 squares with common edges ( logic product of 2 variables) 8-cube: 8 squares with common edges ( logic product of 1 variable) Slide 17
18 Comments on Karnaugh Maps In locating cubes on a Karnaugh map, the map should be considered to fold around from top to bottom, and from left to right. Squares on the right-hand side are considered to be adjacent to those on the left-hand side. Squares on the top of the map are considered to be adjacent to those on the bottom. CD Example: The four squares in the map corners form a 4-cube AB Slide 18
19 4-Variables Example From Truth Table and Sum of Products F=Σ m(1,3,4,5,7,10,12,13) Converting the row numbers to binary yields 0001,0011, etc.. Place 1 s into the Karnaugh Map F = ABCD + AD + BC Slide 19
20 3-Variables Example: Adder Input Output t Simplification of expression for S 1 : A B C S 1 S 0 B BC A C BC AC AB S 1 = AB + BC + AC Slide 20
21 Miscellaneous Examples Slide 21
22 3-Variable Exercise Slide 22
23 4-Variable Exercise Slide 23
24 Exercise with Don t Cares Slide 24
25 Sequential Logic Circuits Sequential logic circuits that possess memory because their present output value depends on previous as well as present input values. Slide 25
26 Clock Signals Often, the operation of a sequential circuit is synchronized by a clock signal : V OH 0 v C (t) positive-going edge (leading edge) T C 2T C negative-going edge (trailing edge) time The clock signal regulates when the circuits respond to new inputs, so that operations occur in proper sequence. Sequential circuits that are regulated by a clock signal are said to be synchronous. Slide 26
27 Flip-Flops One of the basic building blocks for sequential circuits is the flip-flop: A simple flip-flop can be constructed using two inverters: Q Q Two possible states: Q = 1, Q = 0 Q = 0, Q = 1 * Circuit can remain in either state indefinitely Slide 27
28 The S-R ( Set - Reset ) Flip-Flop S-R Flip-Flop Symbol: Rule 1: If S = 0 and R = 0, Q does not change. Rule 2: If S = 0 and R = 1, then Q = 0 Rule 3: If S = 1 and R = 0, then Q = 1 Rule 4: S = 1 and R = 1 should never occur. S R Q Q Slide 28
29 Realization of the S-R Flip-Flop S Q R Q R S Q n 0 0 Q n (not allowed) Slide 29
30 XOR and NAND Implementation Slide 30
31 Exercise: Timing Diagram of SR flip-flop R S Q n 0 0 Q n (not allowed) Q Slide 31
32 Clocked S-R Flip-Flop When CK = 0, disables the inputs R and S When CK = 1, enables inputs R and S Slide 32
33 The D ( Delay ) Flip-Flop D Flip-Flop Symbol: D Q CK Q The output terminals Q and Q behave just as in the S-R flip-flop. Q changes only when the clock signal CK makes a positive transition. CK D Q n 0 Q n-1 1 Q n Slide 33
34 D Flip-Flop Example (Timing Diagram) CK D t Q t t Slide 34
35 Registers A register is an array of flip-flops that is used to store or manipulate the bits of a digital word. Example: Serial-In, Parallel-Out Shift Register using D Flipflops Parallel outputs Q 0 Q 1 Q 2 Data input D 0 Q 0 D 1 Q 1 D 2 Q 2 CK CK CK Clock input Slide 35
36 Shift Register Timing Diagram Slide 36
37 J-K Flip Flop Slide 37
38 Ripple Counter Slide 38
39 Conclusion (Logic Circuits) Complex combinational logic functions can be achieved simply by interconnecting NAND gates (or NOR gates). Logic gates can be interconnected to form flipflops. Interconnections of flip-flops form registers. A complex digital system such as a computer consists of many gates, flip-flops, and registers. Thus, logic gates are the basic building blocks for complex digital systems. Slide 39
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