WORKBOOK. Try Yourself Questions. Electrical Engineering Digital Electronics. Detailed Explanations of

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1 27 WORKBOOK Detailed Eplanations of Try Yourself Questions Electrical Engineering Digital Electronics

2 Number Systems and Codes T : Solution Converting into decimal number system = 2(+2) = = ( + 3) ( 7) = = 3, 7 base can t be negative = 7 T2 : Solution (36) 7 = (27) (67) 8 = (55) (98) = (98) (Z) 5 = (Z) 5 (24) 9 = (99) (Z) 5 = (99) (27) (55) (98) (Z) 5 = (9) Z = 34 T6 : Solution Binary No. Gray Code Copyright

3 Workbook 3 T3 : Solution Given that, () r = 4r so, r 2 + r = 4r r 2 = 3r r = 3 so, () 3 = 3 so, the answer is 3 and 3. T4 : Solution (d) Given that, () () = () = 2 and () () = () 2 2 = 4 so, above conditions are valid for all values of. T5 : Solution Since, (23) 5 = (8) y 38 = y + 8y so, the equation has 3 solution. T6 : Solution (d) Given that, 73 = 54 y = 5y + 4 from the above equation we can see that option (d) is correct. Copyright

4 4 Electrical Engineering Digital Electronics T8 : Solution (b) So, the input to adder is y and s complement since carry input in. So, output is complement of +, so output is y. T : Solution The s complement representation of 27 is and 2 s complement representation of 27 is so the answer is 2/. T3 : Solution Let number N is given to the system. Output after s complement = 5 N Output after 2 s complement = N = N + 3 such systems are connected in cascade. So, Final output = Input + (3) = + = T4 : Solution (d) From the figure we can see that, O 3 = I 3 O 2 = I 2 I 3 O = (I 2 + I 3 ) (I 2 I 3 ) I = I 2 I 3 I O = (I + (O 2 (I 2 + I 3 ))) O I = I I I 2 I 3 From this we can see that, if input is gray code then output is its binary. Copyright

5 2 Boolean Algebra & Logic Gates T : Solution f = Σm(,, 3, 5) f 2 = Σm(4, 5) f 3 =? f = Σm(, 4, 5) and f = ((f + f 2 ) + f 3 ) f = (f + f 2 ) f 3 so, Σm(, 4, 5) = (Σm(,, 3, 5) + Σm(4, 5)) f 3 Σm(, 4, 5) = (Σm(,, 3, 4, 5)) f 3 so, f 3 has to be zero for, 3 and should be for, 4, 5 and dont care for 2, 6, 7. So, answer is (c). T2 : Solution From the figure, f = (f f 2 + f 3 ) since, f = + + so, f (w,, y, z) = Σm(2, 4, 6, 9,,, 2, 4) and f = Σm(, 3, 5, 6, 9, 2, 3) since, f = f f 2 + f 3 so, f 3 has to be for, 2, 4, 7, 8,,, 4, 5 and dont care for 6, 9, 2. Copyright

6 6 Electrical Engineering Digital Electronics T3 : Solution (b) ( ) = 2 = 3 Output of odd XOR is. Output of even XOR is. T5 : Solution (a) EXNOR gate on logic in called coincidence logic. So, f = AB + A B so option (a) is correct. T6 : Solution A B C μs Y Frequency of output = 8 μs = μ T7 : Solution (a) Y from the figure is Y = = + + = B + A + C Copyright

7 Workbook 7 T8 : Solution [Ans. : (b)] T9 : Solution (d) y Since complements are not available. y = + y f 2 units. T : Solution (d) Y = = = = = = a + b + c... T2 : Solution Y = + + so, YZ WX so, Gate (3) is redundant. Y = w yz + y z Copyright

8 8 Electrical Engineering Digital Electronics T3 : Solution (b) D will be majority of input is, so D = A B C T4 : Solution (d) BC AB f = so, f = B(A + C) (A + C ) T5 : Solution Let the 3 locks are A, B, C - key not inserted - key inserted A B C Y X The epression for Y is similar to carry in full adder circuit. So, Number of NAND Gates required are = 6. BC A X Y = AB + BC + AC Copyright

9 Workbook 9 T6 : Solution A B C D F F CD AB F = + = A C F T7 : Solution (b) f = A + B C BC A so, f = so, f = Σm(, 4, 5, 6, 7) T8 : Solution (a) Function f is when and y are different. Clearly we can say that, f = y = y + y T9 : Solution The function Y will be when majority of inputs A, B, C is thus Y = A B C Copyright

10 3 Combinational Logic Circuits T : Solution Y = A B EXNOR gate find equality between two bits. T2 : Solution To generate square of 2 bit input. A B W X Y Z Input Output So, input is 2 bit and output is 4 bit W = AB, Y =, X = AB Z = B Copyright

11 Workbook T3 : Solution (a) Z = ( + ) Mapping above terms in Karnaugh map RS PQ Z= + + T4 : Solution (b) a= b= c= d= = c + e... (NOT)... (NOT) e= P +... (OR) f = + P 2... (OR) g= P + P 2... (OR) g= P + P 2 d= = c + e T5 : Solution (d) 2 NOT gates 3 OR gates Copyright

12 2 Electrical Engineering Digital Electronics T6 : Solution T7 : Solution + = + = (c) Since the delay is of μsec the output will a square wave with time period of 2 μsec. So, frequency =.5 MHz T8 : Solution The look ahead block has delay of 2 logic gates but input ot the block is given through XOR gate and for sum we need one gate delay so answer is 4. T9 : Solution (b) Redrawing the circuit D A D D 2 A B C D f X X X B C 3 8 Decoder D 4 D 5 f Enable D 6 D 7 D A BC BC BC BC BC A A f = + T : Solution [Ans. (c)] T : Solution (c) S = C = AB S = = + Copyright

13 Workbook 3 = = + + = A + B C = = + = T2 : Solution (a) I 4 De MUX D D D 2 D 3 X Y C Z 2 4 Decoder 2 3 F A B X = I = (D + D )I = + I = I Y = I = (D 2 + D 3 )I + I = A I = Z = = X + Y = I + I = I F = + = I + I = T3 : Solution (b) To check the output of the adder we need checking circuit that should give output when sum is greater than and when ever Co =. So,. Y = Co + S 3 S 2 + S 2 S T4 : Solution So, Y = I + I+ I + I + I + I + I + I So, Y = = = + + Copyright

14 4 Sequential Circuits T : Solution / a / / b / / c / / / g / d / e / f / / / Considering the input sequence starting from the initial state a. Each input of or produces an output of or and causes the circuit to go the net state. From the state diagram, we obtain the output and state sequence for the given input sequence as follows. With the circuit in initial state a, an input of produces an output of and circuit remains in state a. With present state at a and input of and the output is and the net state is b. With present state b and an input of, the output is and the net state is c. Continuing this process, we find the complete sequence to be as follows: In each column, we have the present state, input value and output value. The net state is written on top of the net column. Copyright

15 Workbook 5 We now proceed to reduce the number of states. Two states are said to be equivalent if, for each member of the set of inputs, they give eactly the same output and send the circuit either to the same state or to an equivalent state. When two states are equivalent one of them can be removed without altering the input-output relationship. State Table: Present state Net state Output = = = = a a b b c d c a d d e f e a f f g f g a f Now apply the statement written above under inverted comma, we look for two present states that go to the same net state and have the same output for both input combinations. Such states are g and e. They both go to states a and f and have outputs of and, for = and = respectively. Therefore states g and e are equivalent, and one of these states can be removed. The row with present state g is removed, and state g is replaced by state e. Reducing State Table: Present state Net state Output = = = = a a b b c d c a d d e f e a f f e f Present state f now has net states e and f and outputs and for = and =, respectively. The same net states and outputs appear in the row with present state d. Therefore states f and d are equivalent, and state f can be removed and replaced by d. The final reduced table is shown below: Copyright

16 6 Electrical Engineering Digital Electronics Reduced State Table: Present state Net state Output = = = = a a b b c d c a d d e d e a d The state diagram for the reduced table consists of only five states. This state diagram satisfies the original input-output specifications and will produce the required output sequence for any given input sequence. Reduced state diagram: a / / / / e / / / b / / d c / T2 : Solution All the counters are positive edge triggered. In clock pulses MSB of counter C goes from low to high once. LSB of counter C goes from low to high 5 times. Output of C C 3 C 2 Copyright

17 Workbook 7 After 7 clock pulse Count of C 2 = 9 Count of C 3 = 9 Minimum 7 clock pulses are required to make A = B high again. T3 : Solution Set Clear Q Q Set Clear Qn ( ) Qn ( + ) Q n Input waveform and output Q waveform. Let us take initial [Q = ] Set Clear Waveform of ' Q' T4 : Solution Q 2 Q Q + Q 2 + Q + Q J 2 K 2 J K J K Copyright

18 8 Electrical Engineering Digital Electronics From the above table For J : QQ QQ QQ QQ For K : QQ QQ QQ QQ Q 2 Q 2 X X X X J = Q2 Q + Q2Q = Q2ε Q Q 2 Q 2 X X X X K = T5 : Solution (d) The epression of Q + = S + R Q S = A B R = B so, Q + = A B + B Q = A B + AB + B Q T6 : Solution (a) When A = and B = X = Y = Now A = and B = Y = X = Now A = and B = X = = Y = = So, the outputs and y will be fied at and respectively. T7 : Solution (a) Given that, if X = Y = then Q + = X = Y = then Q + = X = Y = then Q + = Q X = Y = then Q + = Q Copyright

19 Workbook 9 so, X Y Q Q + YQ X Q + = Q + = X + YQ T8 : Solution (d) i T9 : Solution + + Design of synchronous counter using J-K flip-flop. State diagram State assignment Copyright

20 Copyright 2 Electrical Engineering Digital Electronics Present stage Q 3 Q 2 Q Net stage Q Q 3 Q 2 Q Q J 3 K 3 J 2 K 2 J K J K J 3 Q Q Q 3 2 Q J Q Q Q 3 = 2 K Q 3 = K 3 Q Q Q 3 2 Q J 2 Q Q Q 3 2 Q J Q Q 2 = K 2 Q Q Q 3 2 Q K Q Q 2 =

21 Workbook 2 J Q 3 Q 2 Q Q K Q 3 Q 2 Q Q J= Q Q K = Q 3 J Q 3 Q 2 Q Q K Q 3 Q 2 Q Q J = K = Q Q Q Q 2 Q Q 3 Q Q Q Q 2 Q 3 J J J 2 J 3 K K K 2 K 3 CLK Q Q Q Q Q Q Copyright

22 Copyright 22 Electrical Engineering Digital Electronics T : Solution Ecitation table of (S-R) Flip-Flop. + + Design of mod-6 counter state diagram State diagram State transition table: Present stage Q 2 Q Q Net stage Q 2 Q Q S 2 R 2 S R S R

23 Workbook 23 S 2 Q 2 Q Q R 2 Q 2 Q Q S = Q Q R = Q 2 2 S 2 Q 2 Q Q R 2 Q Q Q 2 S = Q Q R = Q 2 S 2 Q 2 Q Q R 2 Q Q Q 2 S = Q Q R = Q2Q Q Q Q 2 S = Q Q S S S 2 SR - SR - SR - R Q Q R R 2 Q 2 CLK Q 2 Logic diagram Copyright

24 24 Electrical Engineering Digital Electronics T : Solution Ecitation table of T flip-flop: Present state Qt () Qt ( ) T Net state Present state Net state L M Qt () Qt ( ) T (Based on Q( t) & Q( t ) Getting the value of T interms of L, M and Q(t): F M Q() t L 2 3 T = + + = M + (L Q) M L CLK T Q Q Copyright

25 Workbook 25 T5 : Solution Q 9 Q 8 Q 7 Q 6 Q 5 Q 4 Q 3 Q 2 Q Q T7 : Solution Duty cycle of MSB = = 48.8% (c) For NAND gates: Inputs [(,); (,)] Output [(, ) ; (, )] For NOR gates : Inputs [(, ); (,)] Output [(,); (,)] T8 : Solution Clock Q 3 Q 2 Q Q So, after 7 clock we get T9 : Solution (b) Q 2 Q Q = st Clk Q 2 Q Q = = (triggers T ) = (triggers T 2 ) Copyright

26 26 Electrical Engineering Digital Electronics T2 : Solution (c) This is a 3-bit Johnsan counter so it has 6 states. T22 : Solution [Ans. : (d)] T23 : Solution (a) If we draw the state diagram of the system we get, / / / / / / / / To reach from we need input sequence. So answer is (a). T24 : Solution (a) flip-flops initially at. After 248 clocks all flip-flop will be again so after 26 clock count will be 2 i.e.. \ T25 : Solution The frequency of output will be clock frequency i.e. 5 khz. T26 : Solution 8-bit up counter has initial value () 2 =(72) and to reach () 2 = (39) so it need 22 clocks. Copyright

27 5 Memories T : Solution Clearly Y 3 Y 2 Y Y is a 242 code. X X X X Copyright

28 28 Electrical Engineering Digital Electronics T2 : Solution ROM has a decodes and OR gate D D A B C 3 8 Decodes D 2 D 3 D 4 D 5 D 6 D 7 Y 3 Y 2 Y Y T3 : Solution BCD to ecess 3 converter X 3 X 2 X X Y 3 Y 2 Y Y D X 3 X 2 X X 4 6 Decodes D D 2 D 3 D 4 D 5 D 6 D 7 D 8 D 9 D D D 2 D 3 D 4 D 5 Y 3 Y 2 Y Y Copyright

29 6 Integrated-Circuit Logic Families T : Solution I Fanout is I I I I min {, 5} = 5 T2 : Solution (c) I = I C = ma = = I R. kω =.75 ma I R ( BJT is in saturation) Copyright

30 7 ADC and DAC T : Solution (b) C/P Counter Decoder D 2 is connected to ground and Q 2 to D 3. T2 : Solution (a) 8-bit ADC have full scale value of 2.56 V. So, LSB = Resolution =. V So, V will be equal to () i.e. () 2 T3 : Solution Input Gray code Input to Digital to Analog converter = 2 Analog voltage = = 3.45 V Copyright

31 Workbook 3 T4 : Solution (c) S = C = AB S = = + = = + + = A + B C = = + = Copyright

04. What is the Mod number of the counter circuit shown below? Assume initially reset.

04. What is the Mod number of the counter circuit shown below? Assume initially reset. . Which of the following is the state diagram for the Meale machine shown below. 4. What is the Mod number of the counter circuit shown below? Assume initiall reset. input CLK D output D D a. b. / / /