EECS150 - Digital Design Lecture 22 - Arithmetic Blocks, Part 1

Transcription

1 EECS150 - igital esign Lecture 22 - Arithmetic Blocks, Part 1 April 10, 2011 John Wawrzynek Spring 2011 EECS150 - Lec23-arith1 Page 1 Each cell: r i = a i XOR b i XOR c in Carry-ripple Adder Revisited c out = a i c in + a i b i + b i c in = c in (a i + b i ) + a i b i 4-bit adder: Full adder cell What about subtraction? Spring 2010 EECS150 - Lec23-arith1 Page 2

2 Subtractor A - B = A + (-B) How do we form -B? 1. complement B 2. add 1 Spring 2010 EECS150 - Lec23-arith1 Page 3 elay in Ripple Adders Ripple delay amount is a function of the data inputs: t t t 3 t 1 However, we usually only consider the worst case delay on the critical path. There is usually at least one set of input data that exposes the worst case delay. Spring 2010 EECS150 - Lec23-arith1 Page 4

3 Adders (cont.) Ripple Adder Ripple adder is inherently slow because, in general s7 must wait for c7 which must wait for c6 T α n, Cost α n How do we make it faster, perhaps with more cost? Spring 2010 EECS150 - Lec23-arith1 Page 5 Carry Select Adder T = T ripple_adder / 2 + T MUX COST = 1.5 * COST ripple_adder + (n/2 + 1) * COST MUX Spring 2010 EECS150 - Lec23-arith1 Page 6

4 Carry Select Adder Extending Carry-select to multiple blocks What is the optimal # of blocks and # of bits/block? If # blocks too large delay dominated by total mux delay If # blocks too small delay dominated by adder delay T α sqrt(n), Cost 2*ripple + muxes Spring 2010 EECS150 - Lec23-arith1 Page 7 Carry Select Adder Compare to ripple adder delay: T total = 2 sqrt(n) T FA T FA, assuming T FA = T MUX For ripple adder T total = N T FA cross-over at N=3, Carry select faster for any value of N>3. Is sqrt(n) really the optimum? From right to left increase size of each block to better match delays Ex: 64-bit adder, use block sizes [ ] How about recursively defined carry select? Spring 2010 EECS150 - Lec23-arith1 Page 8

5 Carry Look-ahead Adders In general, for n-bit addition best we can achieve is delay α log(n) How do we arrange this? (think trees) First, reformulate basic adder stage: a b c i c i+1 s carry kill k i = a i b i carry propagate p i = a i b i carry generate g i = a i b i c i+1 = g i + p i c i s i = p i c i Spring 2010 EECS150 - Lec23-arith1 Page 9 Carry Look-ahead Adders Ripple adder using p and g signals: p i = a i b i g i = a i b i a 0 b 0 p 0 g 0 s 0 = p 0 c 1 = g 0 + p 0 s 0 a 1 b 1 p 1 g 1 s 0 = p 1 c 1 c 2 = g 1 + p 1 c 1 s 1 a 2 b 2 p 2 g 2 s 2 = p 2 c 2 c 3 = g 2 + p 2 c 2 s 2 a 3 b 3 p 3 g 3 s 3 = p 3 c 3 c 4 = g 3 + p 3 c 3 s 3 c 4 So far, no advantage over ripple adder: T α N Spring 2010 EECS150 - Lec23-arith1 Page 10

6 Expand carries: c 1 = g 0 + p 0 Carry Look-ahead Adders c 2 = g 1 + p 1 c 1 = g 1 + p 1 g 0 + p 1 p 0 c 3 = g 2 + p 2 c 2 = g 2 + p 2 g 1 + p 1 p 2 g 0 + p 2 p 1 p 0 c 4 = g 3 + p 3 c 3 = g 3 + p 3 g 2 + p 3 p 2 g Why not implement these equations directly to avoid ripple delay? Lots of gates. Redundancies (full tree for each). Gate with high # of inputs. Let s reorganize the equations. Spring 2010 EECS150 - Lec23-arith1 Page 11 Carry Look-ahead Adders Group propagate and generate signals: p i c in g i p i+1 g i+1 P = p i p i+1 p i+k G = g i+k + p i+k g i+k (p i+1 p i+2 p i+k )g i p i+k g i+k c out P true if the group as a whole propagates a carry to c out G true if the group as a whole generates a carry c out = G + Pc in Group P and G can be generated hierarchically. Spring 2010 EECS150 - Lec23-arith1 Page 12

7 a 0 b 0 a 1 b 1 a 2 b 2 a 3 b 3 a 4 b 4 a 5 b 5 a b Carry Look-ahead Adders P a G a c 3 = G a + P a P b G b c 6 = G b + P b c 3 9-bit Example of hierarchically generated P and G signals: P = P a P b P c a 6 b 6 a 7 b 7 a 8 b 8 c P c G c c 9 = G + P G = G c + P c G b + P b P c G a Spring 2010 EECS150 - Lec23-arith1 Page 13 a 0 b 0s0 c 1 a 1 b 1s1 p,g c 2 P,G a i b isi c i c i+1 p,g p = a b g = ab s = p c i c i+1 = g + c i p a 2 b 2s2 c 3 a 3 b 3s3 a 4 b 4s4 c 4 P,G 8-bit Carry Lookahead Adder c 5 a 5 b 5s5 c 8 c in a 6 b 6s6 c 6 P a,g a P,G P = P a P b G = G b + G a P b c 7 a 7 b 7s7 P b,g b c out C out = G + c in P Spring 2011 EECS150 - Lec23-arith1 Page 14

8 p 0 g0 s0 p 1 g1 s1 c p 2 1 g2 s2 p 3 g3 s3 c 1 = g 0 +p 0 c 3 = g 2 +p 2 c 2 c 2 =G 8 +P 8 P 8 =p 0 p 1 G 8 =g 1 +p 1 g 0 P 9 =p 2 p 3 G 9 =g 3 +p 3 g 2 c 4 8-bit Carry Look-ahead Adder with 2-input gates. c 4 =G c +P c P c =P 8 P 9 G c =G 9 +P 9 G 8 P e =P c P d G e =G d +P d G c c p 4 4 g4 P a =p 4 p 5 c 8 =G e +P e s 4 c 5 = g 4 +p 4 c 4 G a =g 5 +p 5 g 4 p 5 s g5 5 c 6 =G a +P a c 4 P d =P a P b c p 6 6 g6 P b =p 6 p 7 G d =G b +P b G a s 6 p 7 s g7 7 c 7 = g 6 +p 6 c 6 G b =g 7 +p 7 g 6 c 8 Spring 2011 EECS150 - Lec23-arith1 Page 15 Carry look-ahead Wrap-up Adder delay O(logN) (up then down the tree). Cost? Energy per add? Can be applied with other techniques. Group P & G signals can be generated for sub-adders, but another carry propagation technique (for instance ripple) used within the group. For instance on FPGA. Ripple carry up to 32 bits is fast (1.25ns), CLA used to extend to large adders. CLA tree quickly generates carry-in for upper blocks. Other more complex techniques exist that can bring the delay down below O(logN), but are only efficient for very wide adders. Spring 2011 EECS150 - Lec23-arith1 Page 16

9 Bit-serial Adder A, B, and R held in shift-registers. Shift right once per clock cycle. Reset is asserted by controller. Addition of 2 n-bit numbers: takes n clock cycles, uses 1 FF, 1 FA cell, plus registers the bit streams may come from or go to other circuits, therefore the registers might not be needed. Spring 2010 EECS150 - Lec23-arith1 Page 17 Adders on the Xilinx Virtex-5 COUT Reset Type Sync edicated carry logic provides fast arithmetic carry capability for highspeed arithmetic functions. Cin to Cout (per bit) delay = 40ps, versus 900ns for F to X delay. 64-bit add delay = 2.5ns X C6 C5 C4 C3 C2 C1 CX B6 B5 B4 B3 B2 B1 BX A6 A5 A4 A3 A2 A1 AX SR CE A6 A5 A4 A3 A2 A1 A6 A5 A4 A3 A2 A1 A6 A5 A4 A3 A2 A1 A6 A5 A4 A3 A2 A1 LUT ROM LUT ROM LUT ROM LUT ROM O6 O5 O6 O5 O6 O5 O6 O5 Spring 2010 CLK EECS150 - Lec23-arith1 Page 18 0/1 X C CX B BX A AX CE CK CE CK CE CK CE CK Async FF LATCH INIT1 INIT0 SRHIGH SRLOW SR FF LATCH INIT1 INIT0 SRHIGH SRLOW SR FF LATCH INIT1 INIT0 SRHIGH SRLOW SR FF LATCH INIT1 INIT0 SRHIGH SRLOW SR Q REV Q REV Q REV Q REV MUX Q CMUX C CQ BMUX B BQ AMUX A AQ CIN UG190_5_04_032606

10 UG190_5_24_ O6 From LUT O5 From LUT X p3 a3 S3 COUT (To Next Slice) I3 MUXCY Virtex 5 Vertical Logic Carry Chain Block (CARRY4) CO3 O3 Q MUX/Q* MUX Q We can map ripple-carry addition onto carry-chain block. p (Optional) O6 From LUTC p2 S2 MUXCY CO2 CMUX/CQ* O5 From LUTC CX a2 I2 O2 Q CMUX CQ O6 From LUTB p1 S1 MUXCY CO1 (Optional) BMUX/BQ* a b c i c i+1 s O5 From LUTB BX O6 From LUTA p0 a1 I1 S0 MUXCY O1 CO0 Q BMUX BQ (Optional) AMUX/AQ* cout = pi cin + ai bi cout = pi? cin : ai pi = ai xor bi O5 From LUTA AX a0 I0 O0 Q AMUX AQ CYINIT CIN 0 1 CIN (From Previous Slice) (Optional) * Can be used if unregistered/registered outputs are free. The carry-chain block also useful for speeding up other adder structures and counters. Adder Final Words Type Cost elay Ripple O(N) O(N) Carry-select O(N) O(sqrt(N)) Carry-lookahead O(N) O(log(N)) ynamic energy per addition for all of these is O(n). O notation hides the constants. Watch out for this! The cost of the carry-select is at least 2X the cost of the ripple. Cost of the CLA is probably at least 2X the cost of the carry-select. The actual multiplicative constants depend on the implementation details and technology. FPGA and ASIC synthesis tools will try to choose the best adder architecture automatically assuming you specify addition using the + operator, as in assign A = B + C Spring 2009 EECS150 - Lec03-FPGA Page 20