L8/9: Arithmetic Structures

Transcription

1 L8/9: Arithmetic Structures Acknowledgements: Materials in this lecture are courtesy of the following sources and are used with permission. Rex Min Kevin Atkinson Prof. Randy Katz (Unified Microelectronics Corporation Distinguished Professor in Electrical Engineering and Computer Science at the University of California, Berkeley) and Prof. Gaetano Borriello (University of Washington Department of Computer Science & Engineering) from Chapter 2 of R. Katz, G. Borriello. Contemporary Logic Design. 2nd ed. Prentice-Hall/Pearson Education, 25. J. Rabaey, A. Chandrakasan, B. Nikolic, Digital Integrated Circuits: A Design Perspective Prentice Hall/Pearson, 23. L8/9: 6. Spring 26 Introductory Digital Systems Laboratory

2 Number Systems Basics How to represent negative numbers? Three common schemes: sign-magnitude, ones complement, twos complement Sign-magnitude: MSB = for positive, for negative Range: -(2 N- ) to (2 N- ) Two representations for zero: & Simple multiplication but complicated addition/subtraction _ Ones complement: if N is positive then its negative is N Example: = 7, = -7 Range: -(2 N- ) to (2 N- ) Two representations for zero: & Subtraction implemented as addition and negation L8/9: 6. Spring 26 Introductory Digital Systems Laboratory 2

3 Twos Complement Representation Twos complement = bitwise complement = = -7 = = 7 Asymmetric range: -2 N- to 2 N- - Only one representation for zero Simple addition and subtraction Most common representation (-3) [Katz5] L8/9: 6. Spring 26 Introductory Digital Systems Laboratory 3

4 Overflow Conditions Add two positive numbers to get a negative number or two negative numbers to get a positive number = -8! -7-2 = 7! If carry in to sign equals carry out then can ignore carry out, otherwise have overflow L8/9: 6. Spring 26 Introductory Digital Systems Laboratory 4

5 Binary Full Adder A B C i A Full Adder B S CI S C o CO S = A B C i = ABC i ABC i ABC i ABC i C o = AB C i (AB) S CI CI A B A B CO L8/9: 6. Spring 26 Introductory Digital Systems Laboratory 5

6 Ripple Carry Adder Structure B 3 A 3 B 2 A 2 B A B A C o,3 Full C o,2 Full C o, Full C o, Adder Adder Adder Full Adder C i, S 3 S 2 S S Worst case propagation delay linear with the number of bits t adder = (N-)t carry t sum L8/9: 6. Spring 26 Introductory Digital Systems Laboratory 6

7 Extension to Subtraction Under twos complement, subtracting B is the same as adding the bitwise complement of B then adding Combination addition/subtraction system: _ mux selects B for addition, B for subtraction B 3 B 3 B 2 B 2 B B B B A 3 A 2 A A C o,3 C o,2 C o, C o, Add/Subtract S 3 S 2 S S Add for subtraction using carry in Overflow occurs if carry in to sign bit differs from final carry out overflow L8/9: 6. Spring 26 Introductory Digital Systems Laboratory 7

8 Comparator (one approach) B 3 B 3 B 2 B 2 B B B B A 3 A 2 A A C o,3 C o,2 C o, C o, S 3 S 2 S S N true if negative result Z true if zero result A < B = N A = B = Z A B = Z N L8/9: 6. Spring 26 Introductory Digital Systems Laboratory 8

9 Alternate Adder Logic Formulation How to Speed up the Critical (Carry) Path? (How to Build a Fast Adder?) A B C in Full Adder C o S Generate (G) = AB Propagate (P) = A B Note: can also use P = A B for C o L8/9: 6. Spring 26 Introductory Digital Systems Laboratory 9

10 Carry Bypass Adder A B A B A 2 B 2 A 3 B 3 P G P G P 2 G 2 P 3 G 3 Can compute P, G in parallel for all bits C i, C o, C o, C o,2 C o,3 BP= P P P 2 P 3 P G P 2 G 2 P 3 G 3 P G C i, Co, C o, C o,2 C o,3 Key Idea: if (P P P 2 P 3 ) then C o,3 = C i, L8/9: 6. Spring 26 Introductory Digital Systems Laboratory

11 6-bit Carry Bypass Adder BP= P P P 2 P 3 BP= P 4 P 5 P 6 P 7 BP= P 8 P 9 P P BP= P 2 P 3 P 4 P 5 C i, C o, C o, C o,2 C o,3 C o,4 C o,5 C o,6 C o,7 C o,8 C o, C o,9 C o, C o,2 C o,3 C o,4 C o,5 Assume the following for delay each gate: P, G from A, B: delay unit P, G, C i to C o or Sum for a : delay unit 2: mux delay: delay unit What is the worst case propagation delay for the 6-bit adder? L8/9: 6. Spring 26 Introductory Digital Systems Laboratory

12 Critical Path Analysis BP= P P P 2 P 3 BP2= P 4 P 5 P 6 P 7 BP3= P 8 P 9 P P BP4= P 2 P 3 P 4 P 5 C i, C o, C o, C o,2 C o,3 C o,4 C o,5 C o,6 C o,7 C o,8 C o, C o,9 C o, C o,2 C o,3 C o,4 C o,5 For the second stage, is the critical path: BP2 = or BP2 =? Message: Timing Analysis is Very Tricky Must Carefully Consider Data Dependencies For False Paths L8/9: 6. Spring 26 Introductory Digital Systems Laboratory 2

13 Carry Lookahead Adder C = G P C Re-express the carry logic as follows: C2 = G P C = G P G P P C C3 = G2 P2 C2 = G2 P2 G P2 P G P2 P P C C4 = G3 P3 C3 = G3 P3 G2 P3 P2 G P3 P2 P G P3 P2 P P C Each of the carry equations can be implemented in a two-level logic network Variables are the adder inputs and carry in to stage Ripple effect has been eliminated! L8/9: 6. Spring 26 Introductory Digital Systems Laboratory 3

14 Carry Lookahead Logic Ai Bi Ci Pi Si Gi Adder with propagate and generate outputs Later stages have increasingly complex logic C P G C P P G P G C C2 C P P P2 G P P2 G P2 G2 C3 C P P P2 P3 G P P2 P3 G P2 P3 G2 P3 C4 G3 L8/9: 6. Spring 26 Introductory Digital Systems Laboratory 4

15 Block Generate and Propagate G j:i and P j:i denote the Generate and Propagate functions, respectively, for a group of bits from positions i to j. We call them Block Generate and Block Propagate. G j:i equals if the group generates a carry independent of the incoming carry. P j:i equals if an incoming carry propagates through the entire group. For example, G 3:2 is equal to if a carry is generated at bit position 3, or if a carry out is generated at bit position 2 and propagates through position 3. G 3:2 = G 3 P 3 G 2. P 3:2 is true if an incoming carry propagates through both bit positions 2 and 3. P 3:2 = P 3 P 2 C 2 = (G P G ) (P P )C = G : P : C C 4 = G 3 P 3 G 2 P 3 P 2 G P 3 P 2 P G P 3 P 2 P P C = (G 3 P 3 G 2 ) (P 3 P 2 )C o, = G 3:2 P 3:2 C 2 = G 3:2 P 3:2 (G : P : C ) = G 3: P 3: C The carry out of a 4-bit block can thus be computed using only the block generate and propagate signals for each 2-bit section, plus the carry in to bit. The same formulation will be used to generate the carry out signals for a 6-bit adder using the block generate and propagate from 4-bit sections. L8/9: 6. Spring 26 Introductory Digital Systems Laboratory 5

16 More Definitions ( gp, ) ( g', p' ) = ( g pg', pp' ) The above dot operator obeys the associative property, but it is not commutative (G 3:2,P 3:2 ) = (G 3,P 3 ) (G 2,P 2 ) ( C o3,, ) = (( G 3, P 3 ) ( G 2, P 2 ) ( G, P ) ( G, P )) ( C i,, ) ( G 3:, P 3: ) = [( G 3, P 3 ) ( G 2, P 2 )] [( G, P ) ( G, P )] = ( G 3:2, P 3:2 ) ( G :, P : ) ( C ok, ), = (( G, k P ) ( k G, k P ) ( k G, P )) C i (, ), L8/9: 6. Spring 26 Introductory Digital Systems Laboratory 6

17 Logarithmic Look-Ahead Adder A F A A 2 A 3 A 4 A 5 A 6 A 7 t p : O(N) A A A 2 A 3 F A 4 A 5 A 6 t p :O(log 2 N) A 7 L8/9: 6. Spring 26 Introductory Digital Systems Laboratory 7

18 6-bit Kogge-Stone Tree Adder Sum Logic (A, B ) (A, B ) (A2, B 2 ) (A3, B 3 ) (A4, B 4 ) (A5, B 5 ) (A6, B 6 ) (A7, B 7 ) (A8, B 8 ) (A9, B 9 ) (A, B ) (A, B ) (A2, B 2 ) (A3, B 3 ) (A4, B 4 ) (A5, B 5 ) S S S2 S3 S4 S5 S6 S7 S8 S9 S S S2 S3 S4 S5 Propagate, Generate Logic L8/9: 6. Spring 26 Introductory Digital Systems Laboratory 8

19 Adder Performance Ripple Bypass Select Lookahead Delay vs. number of bits L8/9: 6. Spring 26 Introductory Digital Systems Laboratory 9

20 Addition of M, N-bit N Numbers IN N- IN N- IN2 N- IN3 N- INM- N- IN N-2 IN N-2 IN2 N-2 IN3 N-2 INM- N-2 IN IN IN2 IN3 INM- IN IN IN2 IN3 INM- C in = C in = C in = C in = L8/9: 6. Spring 26 Introductory Digital Systems Laboratory 2

21 6-bit Carry Lookahead Schematic 8 configured for AB: M =, S 3- = A 3: B 3: A 7:4 B 7:4 A :8 B :8 A 5:2 B 5:2 C n C 8 n4 C n C 8 n4 C n C 8 n4 C n C 8 n4 P G P G P G P G S 3: P 3: S 7:4 S :8 S 5:2 C in G 3: P G P G P2 G2 P3 G3 82 C n Cnx Cny Cnz G P 82 computes C in for later stages, using block G & P from earlier stages L8/9: 6. Spring 26 Introductory Digital Systems Laboratory 2

22 Binary Multiplication x 3 x 2 x x y Partial product computation is simple (single and gate) x 3 x 2 x x y z HA HA x 3 x 2 x x y 2 z HA x 3 x 2 x x y 3 z 2 HA z 7 z 6 z 5 z 4 z 3 L8/9: 6. Spring 26 Introductory Digital Systems Laboratory 22

23 A Serial (Magnitude) Multiplier Shift/LD D D D D Q Q Q Q xbus [7] [6] [5] [4] xbus 8 add_out 8 Shift rst D Q acc_out x 3 D Q [3] 8 Shift x 2 x x D Q D Q D Q CLK [2] [] [] Shift/LD D Q Y yreg D Q D Q Y Y 2 D Q Y 3 CLK CLK LD D Q CLK XY L8/9: 6. Spring 26 Introductory Digital Systems Laboratory 23

24 Timing Diagram CLK Shift xreg x3 x2 x x x3 x2 x x x3 x2 x x x3 x2 x x x3 x2 x x yreg y y y2 y3 y y2 y3 X y2 y3 X X y3 X X X y y y2 y3 Acc_out Accum_ Accum_2 Accum_3 X*Y PRODUCT PRODUCT L8/9: 6. Spring 26 Introductory Digital Systems Laboratory 24

25 Verilog of Serial Multiplier module serialmult(shift, clk, x, y, xy); input shift, clk; input [3:] x, y; output [7:] xy; reg [7:] xreg; reg [3:] yreg; reg [7:] xbus, acc_out, xy_int; wire[7:] add_out; assign add_out = xbus acc_out; assign xy = xy_int; (yreg[] or xreg) begin if (yreg[] == 'b) xbus = 8'b; else xbus = xreg; end (posedge clk) begin if (shift == 'b) begin xreg <= {4'b, x}; yreg <= y; acc_out <= 8'b; xy_int <= add_out; end else begin xreg <= {xreg[6:], 'b}; yreg <= {y[3], yreg[3:]}; acc_out <= add_out; xy_int <= xy; end // if shift end // always endmodule L8/9: 6. Spring 26 Introductory Digital Systems Laboratory 25

26 Simulation L8/9: 6. Spring 26 Introductory Digital Systems Laboratory 26

27 Twos Complement Multiplication x 3 x 2 x x y x 3 x 2 x x y z HA x 3 x 2 x x y 2 z HA x 3 x 2 x x y 3 z 2 HA HA z 7 z 6 z 5 z 4 z 3 L8/9: 6. Spring 26 Introductory Digital Systems Laboratory 27

28 Summary Performance of arithmetic blocks dictate the performance of a digital system Architectural and logic transformations can enable significant speed up (e.g., adder delay from O(N) to O(log 2 (N)) Similar concepts and formulation can be applied at the system level Timing analysis is tricky: watch out for false paths! Area-Delay trade-offs (serial vs. parallel implementations) L8/9: 6. Spring 26 Introductory Digital Systems Laboratory 28