CSE477 VLSI Digital Circuits Fall Lecture 20: Adder Design

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1 CSE477 VLSI Digital Circuits Fall 22 Lecture 2: Adder Design Mary Jane Irwin ( ) [Adapted from Rabaey s Digital Integrated Circuits, 22, J. Rabaey et al.] CSE477 L2 Adder Design.1 Irwin&Vijay, PSU, 22

2 Review: Basic Building Blocks Datapath Execution units - Adder, multiplier, divider, shifter, etc. Register file and pipeline registers Multiplexers, decoders Control Finite state machines (PLA, ROM, random logic) Interconnect Switches, arbiters, buses Memory Caches (SRAMs), TLBs, DRAMs, buffers CSE477 L2 Adder Design.2 Irwin&Vijay, PSU, 22

3 The 1-bit Binary Adder A B C out S carry status A B 1-bit Full Adder (FA) S kill kill propagate propagate propagate C out G = A&B P = A B K =!A &!B propagate generate generate S = A B = P C out = A&B A& B& (majority function) = G P& How can we use it to build a 64-bit adder? How can we modify it easily to build an adder/subtractor? How can we make it better (faster, lower power, smaller)? CSE477 L2 Adder Design.3 Irwin&Vijay, PSU, 22

4 FA Gate Level Implementations The way you learned to design in CSE271 and CSE471 A B A B t1 t t2 t2 t1 t C out S C out S CSE477 L2 Adder Design.4 Irwin&Vijay, PSU, 22

5 Review: XOR FA A B S C out 16 transistors CSE477 L2 Adder Design.5 Irwin&Vijay, PSU, 22

6 Review: CPL FA!B B! A!S!A S B!B! A!C out B!A C out!b! 2+8 transistors, dual rail beware of threshold drops CSE477 L2 Adder Design.6 Irwin&Vijay, PSU, 22

7 Delay Balanced FA B!B!P Identical Delays for Carry and Sum B P P A p A P!C out S!B A!P P!P!P Sum generation Carry generation Signal set-up 2+2 transistors CSE477 L2 Adder Design.7 Irwin&Vijay, PSU, 22

8 Review: Mirror Adder 24+4 transistors A -propagate 1-propagate A 8 B B 8 B 8 A 8 6 C!C out!s in 4 A B 8 kill 4 A generate A 4 B B B A A B C out = A&B B& A& SUM = A&B& C OUT &(A B ) Sizing: Each input in the carry circuit has a logical effort of 2 so the optimal fan-out for each is also 2. Since!C out drives 2 internal and 2 inverter transistor gates (to form for the nms bit adder) should oversize the carry circuit. PMOS/NMOS ratio of 2. CSE477 L2 Adder Design.8 Irwin&Vijay, PSU, 22

9 Mirror Adder Features The NMOS and PMOS chains are completely symmetrical with a maximum of two series transistors in the carry circuitry, guaranteeing identical rise and fall transitions if the NMOS and PMOS devices are properly sized. When laying out the cell, the most critical issue is the minimization of the capacitances at node!c out (four diffusion capacitances, two internal gate capacitances, and two inverter gate capacitances). Shared diffusions can reduce the stack node capacitances. The transistors connected to are placed closest to the output. Only the transistors in the carry stage have to be optimized for optimal speed. All transistors in the sum stage can be minimal size. CSE477 L2 Adder Design.9 Irwin&Vijay, PSU, 22

10 A 64-bit Adder/Subtractor Ripple Carry Adder (RCA) built out of 64 FAs add/subt A C = 1-bit FA S Subtraction complement all subtrahend bits (xor gates) and set the low order carry-in RCA B B 1 A1 A 2 C 1 1-bit FA S 1 C 2 1-bit FA S 2 advantage: simple logic, so small (low cost) B 2... C 3 disadvantage: slow (O(N) for N bits) and lots of glitching (so lots of energy consumption) B 63 A 63 C 63 1-bit FA S 63 C 64 =C out CSE477 L2 Adder Design.1 Irwin&Vijay, PSU, 22

11 Ripple Carry Adder (RCA) A 3 B 3 A 2 B 2 A 1 B 1 A B C out =C 4 FA FA FA FA C = S 3 S 2 S 1 S T adder T FA (A,B C out ) + (N-2)T FA ( C out ) + T FA ( S) T = O(N) worst case delay Real Goal: Make the fastest possible carry path CSE477 L2 Adder Design.11 Irwin&Vijay, PSU, 22

12 Inversion Property Inverting all inputs to a FA results in inverted values for all outputs A B A B C out FA C out FA S S!S (A, B, ) = S(!A,!B,! )!C out (A, B, ) = C out (!A,!B,! ) CSE477 L2 Adder Design.12 Irwin&Vijay, PSU, 22

13 Exploiting the Inversion Property A 3 B 3 A 2 B 2 A 1 B 1 A B C out =C 4 FA FA FA FA C = S 3 S 2 S 1 S inverted cell regular cell Minimizes the critical path (the carry chain) by eliminating inverters between the FAs (will need to increase the transistor sizing on the carry chain portion of the mirror adder). Now need two flavors of FAs CSE477 L2 Adder Design.13 Irwin&Vijay, PSU, 22

14 Fast Carry Chain Design The key to fast addition is a low latency carry network What matters is whether in a given position a carry is generated G i = A i & B i = A i B i propagated P i = A i B i (sometimes use A i B i ) annihilated (killed) K i =!A i &!B i Giving a carry recurrence of C i+1 = G i P i C i C 1 = C 2 = C 3 = C 4 = CSE477 L2 Adder Design.14 Irwin&Vijay, PSU, 22

15 Fast Carry Chain Design The key to fast addition is a low latency carry network What matters is whether in a given position a carry is generated G i = A i & B i = A i B i propagated P i = A i B i (sometimes use A i B i ) annihilated (killed) K i =!A i &!B i Giving a carry recurrence of C i+1 = G i P i C i C 1 = G P C C 2 = G 1 P 1 G P 1 P C C 3 = G 2 P 2 G 1 P 2 P 1 G P 2 P 1 P C C 4 = G 3 P 3 G 2 P 3 P 2 G 1 P 3 P 2 P 1 G P 3 P 2 P 1 P C CSE477 L2 Adder Design.15 Irwin&Vijay, PSU, 22

16 Manchester Carry Chain Switches controlled by G i and P i!c i+1 G i Pi!C i clk Total delay of time to form the switch control signals G i and P i setup time for the switches signal propagation delay through N switches in the worst case CSE477 L2 Adder Design.16 Irwin&Vijay, PSU, 22

17 4-bit Sliced MCC Adder A 3 B 3 A 2 B 2 A 1 B 1 A B clk & G P & G P & G P & G P!C 4!C!C 3!C 2!C 1 S 3 S 2 S 1 S CSE477 L2 Adder Design.17 Irwin&Vijay, PSU, 22

18 Domino Manchester Carry Chain Circuit P 3 P 2 P 1 P clk C i, G 3 2 G 2 3 G 1 4 G 5 C i, clk!(g 2 P 2 G 1 P 2 P 1 G P 2 P 1 P C i, )!(G P C i, )!(G 1 P 1 G P 1 P C i, )!(G 3 P 3 G 2 P 3 P 2 G 1 P 3 P 2 P 1 G P 3 P 2 P 1 P C i, ) CSE477 L2 Adder Design.18 Irwin&Vijay, PSU, 22

19 Binary Adder Landscape synchronous word parallel adders ripple carry adders (RCA) T = O(N), A = O(N) carry prop min adders signed-digit fast carry prop residue adders adders adders T = O(1), A = O(N) Manchester carry parallel conditional carry carry chain select prefix sum skip T = O(N) A = O(N) T = O(log N) A = O(N log N) T = O( N), A = O(N) CSE477 L2 Adder Design.19 Irwin&Vijay, PSU, 22

20 Carry-Skip (Carry-Bypass) Adder A 3 B 3 A 2 B 2 A 1 B 1 A B C o,3 FA FA FA FA C i, C o,3 S 3 S 2 S 1 S BP = P P 1 P 2 P 3 Block Propagate If (P & P 1 & P 2 & P 3 = 1) then C o,3 = C i, otherwise the block itself kills or generates the carry internally CSE477 L2 Adder Design.2 Irwin&Vijay, PSU, 22

21 Carry-Skip Chain Implementation carry-out block carry-out BP block carry-in P 3 P 2 P 1 P!C out G 3 G 2 G 1 G BP CSE477 L2 Adder Design.21 Irwin&Vijay, PSU, 22

22 4-bit Block Carry-Skip Adder bits 12 to 15 bits 8 to 11 bits 4 to 7 bits to 3 Carry Propagation Carry Propagation Carry Propagation Carry Propagation C i, Sum Sum Sum Sum Worst-case delay carry from bit to bit 15 = carry generated in bit, ripples through bits 1, 2, and 3, skips the middle two groups (B is the group size in bits), ripples in the last group from bit 12 to bit 15 T add = t setup + B t carry + ((N/B) -1) t skip +B t carry + t sum CSE477 L2 Adder Design.22 Irwin&Vijay, PSU, 22

23 Optimal Block Size and Time Assuming one stage of ripple (t carry ) has the same delay as one skip logic stage (t skip ) and both are 1 T CSkA = 1 + B + (N/B-1) + B + 1 t setup ripple in skips ripple in t sum block last block = 2B + N/B + 1 So the optimal block size, B, is And the optimal time is dt CSkA /db = (N/2) = B opt Optimal T CSkA = 2( (2N)) + 1 CSE477 L2 Adder Design.23 Irwin&Vijay, PSU, 22

24 Carry-Skip Adder Extensions Variable block sizes A carry that is generated in, or absorbed by, one of the inner blocks travels a shorter distance through the skip blocks, so can have bigger blocks for the inner carries without increasing the overall delay C out Multiple levels of skip logic C out skip level 1 skip level 2 AND of the first level skip signals (BP s) CSE477 L2 Adder Design.24 Irwin&Vijay, PSU, 22

25 Carry-Skip Adder Comparisons RCA B=2 B=3 B=4 B=5 B=6 CSkA VSkA 8 bits 16 bits 32 bits 48 bits 64 bits CSE477 L2 Adder Design.25 Irwin&Vijay, PSU, 22

26 Carry Select Adder A s B s Precompute the carry out of each block for both carry_in = and carry_in = 1 (can be done for all blocks in parallel) and then select the correct one C out 4-b P s G s carry propagation 1 carry propagation 1 multiplexer C s Sum generation S s CSE477 L2 Adder Design.26 Irwin&Vijay, PSU, 22

27 Carry Select Adder: Critical Path bits 12 to 15 A s B s A s bits 8 to 1 B s A s bits 4 to 7 B s A s bits to 3 B s P s G s P s G s P s G s P s G s carry carry carry carry 1 carry 1 carry 1 carry 1 carry 1 C out mux C s mux C s mux C s mux C s Sum gen Sum gen Sum gen Sum gen S s S s S s S s CSE477 L2 Adder Design.27 Irwin&Vijay, PSU, 22

28 Carry Select Adder: Critical Path bits 12 to 15 A s B s A s bits 8 to 1 B s A s bits 4 to 7 B s A s bits to 3 B s P s G s P s G s P s G s 1 P s G s carry carry carry carry +4 1 carry 1 carry 1 carry 1 carry 1 C out +1 mux C s +1 mux C s +1 mux C s +1 mux C s +1 Sum gen Sum gen Sum gen Sum gen S s S s S s S s T add = t setup + B t carry + N/B t mux + t sum CSE477 L2 Adder Design.28 Irwin&Vijay, PSU, 22

29 Square Root Carry Select Adder bits 14 to 19 A s B s bits 9 to 13 A s B s A s bits 5 to 8 B s bits 2 to 4 A s B s bits to 1 A s B s P s G s P s G s P s G s P s G s P sg s carry carry carry carry carry 1 carry 1 carry 1 carry 1 carry 1 carry 1 C out mux C s mux C s mux C s mux C s mux Cin C s Sum gen Sum gen Sum gen Sum gen Sum gen S s S s S s S s S s CSE477 L2 Adder Design.29 Irwin&Vijay, PSU, 22

30 Square Root Carry Select Adder bits 14 to 19 A s B s bits 9 to 13 A s B s A s bits 5 to 8 B s bits 2 to 4 A s Bs bits to 1 As B s P s G s P s G s P s G s P s G s 1 P sg s carry +6 carry +5 carry +4 carry +3 carry +2 1 carry 1 carry 1 1 carry 1 1 carry 1 1 carry 1 C out +1 mux C s +1 mux C s +1 mux C s +1 mux C s +1 mux Cin C s +1 Sum gen Sum gen Sum gen Sum gen Sum gen S s S s S s S s S s T add = t setup + 2 t carry + vn t mux + t sum CSE477 L2 Adder Design.3 Irwin&Vijay, PSU, 22

31 Parallel Prefix Adders (PPAs) Define carry operator on (G,P) signal pairs (G,P ) (G,P ) G (G,P) where G = G P = P P P G G!G P is associative, i.e., [(g,p ) (g,p )] (g,p ) = (g,p ) [(g,p ) (g,p )] CSE477 L2 Adder Design.31 Irwin&Vijay, PSU, 22

32 PPA General Structure Given P and G terms for each bit position, computing all the carries is equal to finding all the prefixes in parallel (G,P ) (G 1,P 1 ) (G 2,P 2 ) (G N-2,P N-2 ) (G N-1,P N-1 ) Since is associative, we can group them in any order but note that it is not commutative P i, G i logic (1 unit delay) C i parallel prefix logic tree (1 unit delay per level) S i logic (1 unit delay) Measures to consider number of cells tree cell depth (time) tree cell area cell fan-in and fan-out max wiring length wiring congestion delay path variation (glitching) CSE477 L2 Adder Design.32 Irwin&Vijay, PSU, 22

33 T = log 2 N - 2 A = 2log 2 N T = log 2 N Brent-Kung PPA G 15 p 15 G 14 p 14 G 13 p 13 G 12 P 12 G 11 p 11 G 1 P 1 G 9 p 9 G 8 P 8 G 7 P 7 G 6 P 6 G 5 P 5 G 4 P 4 G 3 P 3 G 2 p 2 G 1 P 1 G P Parallel Prefix Computation C 16 C 15 C 14 C 13 C 12 C 11 C 1 C 9 C 8 A = N/2 C 7 C 6 C 5 C 4 C 3 C 2 C 1 CSE477 L2 Adder Design.33 Irwin&Vijay, PSU, 22

34 T = log 2 N - 2 A = 2log 2 N T = log 2 N Brent-Kung PPA G 15 p 15 G 14 p 14 G 13 p 13 G 12 P 12 G 11 p 11 G 1 P 1 G 9 p 9 G 8 P 8 G 7 P 7 G 6 P 6 G 5 P 5 G 4 P 4 G 3 P 3 G 2 p 2 G 1 P 1 G P Parallel Prefix Computation C 16 C 15 C 14 C 13 C 12 C 11 C 1 C 9 C 8 A = N/2 C 7 C 6 C 5 C 4 C 3 C 2 C 1 CSE477 L2 Adder Design.34 Irwin&Vijay, PSU, 22

35 T = log 2 N A = log 2 N Kogge-Stone PPF Adder G 15 P 15 G 14 P 14 G 13 P 13 G 12 P 12 G 11 P 11 G 1 P 1 G 9 P 9 G 8 P 8 G 7 P 7 G 6 P 6 G 5 P 5 G 4 P 4 G 3 P 3 G 2 P 2 G 1 P 1 G P Parallel Prefix Computation C 16 C 15 C 14 C 13 C 12 C 11 C 1 C 9 C 8 A = N C 7 C 6 C 5 C 4 C 3 C 2 C 1 T add = t setup + log 2 N t + t sum CSE477 L2 Adder Design.35 Irwin&Vijay, PSU, 22

36 More Adder Comparisons RCA CSkA VSkA KS PPA 1 8 bits 16 bits 32 bits 48 bits 64 bits CSE477 L2 Adder Design.36 Irwin&Vijay, PSU, 22

37 Adder Speed Comparisons RCA MCC CCSkA VCSkA CCSlA B&K bits 32 bits 64 bits CSE477 L2 Adder Design.37 Irwin&Vijay, PSU, 22

38 Adder Average Power Comparisons RCA MCC CCSkA VCSkA CCSlA B&K 5 16 bits 32 bits 64 bits CSE477 L2 Adder Design.38 Irwin&Vijay, PSU, 22

39 PDP of Adder Comparisons RCA MCCA CCSkA VCSkA CCSlA BKA 8 bits 16 bits 32 bits 48 bits 64 bits From Nagendra, 1996 CSE477 L2 Adder Design.39 Irwin&Vijay, PSU, 22

40 Next Lecture and Reminders Next lecture Multiplier Design Reminders - Reading assignment Rabaey, et al, 11.4 Project final reports due December 5 th HW5 (last one!) due November 19 th Final grading negotiations/correction (except for the final exam) must be concluded by December 1 th Final exam scheduled - Monday, December 16 th from 1:1 to noon in 118 and 121 Thomas CSE477 L2 Adder Design.4 Irwin&Vijay, PSU, 22

VLSI Design. [Adapted from Rabaey s Digital Integrated Circuits, 2002, J. Rabaey et al.] ECE 4121 VLSI DEsign.1

VLSI Design. [Adapted from Rabaey s Digital Integrated Circuits, 2002, J. Rabaey et al.] ECE 4121 VLSI DEsign.1 VLSI Design Adder Design [Adapted from Rabaey s Digital Integrated Circuits, 2002, J. Rabaey et al.] ECE 4121 VLSI DEsign.1 Major Components of a Computer Processor Devices Control Memory Input Datapath