Arithmetic Circuits-2

Size: px
Start display at page:

Download "Arithmetic Circuits-2"

Transcription

1 Arithmetic Circuits-2 Multipliers Array multipliers Shifters Barrel shifter Logarithmic shifter ECE 261 Krish Chakrabarty 1 Binary Multiplication M-1 X = X i 2 i i=0 Multiplicand N-1 Y = Y i 2 i i=0 Multiplier Product Z = X * Y N-1 M-1 = ( X i Y j 2 i+j ) i=0 j=0 Partial products Product = Sum of partial products ECE 261 Krish Chakrabarty 2 1

2 Multiplication Example: ECE 261 Krish Chakrabarty 3 Example: Multiplication ECE 261 Krish Chakrabarty 4 2

3 Multiplication Example: ECE 261 Krish Chakrabarty 5 Example: Multiplication ECE 261 Krish Chakrabarty 6 3

4 Multiplication Example: ECE 261 Krish Chakrabarty 7 Example: Multiplication ECE 261 Krish Chakrabarty 8 4

5 Multiplication Example: M x N-bit multiplication Produce N M-bit partial products Sum these to produce M+N-bit product ECE 261 Krish Chakrabarty 9 The Binary Multiplication Multiplicand Multiplier A N D o p e r a t i o n P a r t i a l P r o d u c t s ECE 261 Krish Chakrabarty 10 5

6 General Form Multiplicand: Y = (y M-1, y M-2,, y 1, y 0 ) Multiplier: X = (x N-1, x N-2,, x 1, x 0 ) Product: ECE 261 Krish Chakrabarty 11 Dot Diagram Each dot represents a bit ECE 261 Krish Chakrabarty 12 6

7 x 3 The Array Multiplier x 3 x 3 H A F A F A H A Z 1 x 2 x 3 x 2 x 1 F A F A F A H A x 2 x 1 x 0 Z 2 F A F A F A H A Z 7 Z 6 Z 5 Z 4 Z 3 ECE 261 Krish Chakrabarty 13 y 3 x 2 x 1 x 0 y 2 x 1 x 0 y 1 x 0 Z 0 y 0 FA: Full adder HA: Half adder (two inputs) Propagation delay =? The MxN Array Multiplier Critical Path H A F A F A H A F A F A F A F A F A F A H A H A C r i t i c a l P a t h 1 C r i t i c a l P a t h 2 Critical Path 1 & 2 ECE 261 Krish Chakrabarty 14 7

8 Carry-Save Multiplier H A H A H A H A H A F A F A H A F A F A F A H A F A F A H A F A Carries saved for next adder stage Unique critical path Trade offs? ECE 261 Krish Chakrabarty 15 Adder Cells in Array Multiplier V D D A A A P V D D B A P B C i C i A I d e n t i c a l D e l a y s f o r C a r r y a n d S u m P C i P C i P A P C i P V D D S V D D C o ECE 261 Krish Chakrabarty 16 8

9 Y 0 Y 1 Y 2 Y 3 Z 7 X 3 Z 6 Multiplier Floorplan X 2 Z 5 X 1 Z 4 X 0 Z 3 Z 0 Z 1 Z 2 H A M u l t i p l i e r C e l l F A M u l t i p l i e r C e l l V e c t o r M e r g i n g C e l l X a n d Y s i g n a l s a r e b r o a d c a s t e d t h r o u g h t h e c o m p l e t e a r r a y. ECE 261 Krish Chakrabarty 17 Multipliers Summary O p t i m i z a t i o n G o a l s D i f f e r e n t V s B i n a r y A d d e r O n c e A g a i n : I d e n t i f y C r i t i c a l P a t h O t h e r p o s s i b l e t e c h n i q u e s - L o g a r i t h m i c v e r s u s L i n e a r - D a t a e n c o d i n g ( B o o t h ) - P i p e l i n i n g (Wallace tree multiplier) ECE 261 Krish Chakrabarty 18 9

10 Comparators 0 s detector: A = s detector: A = Equality comparator: A = B Magnitude comparator: A < B ECE 261 Krish Chakrabarty 19 1 s & 0 s Detectors 1 s detector: N-input AND gate 0 s detector: NOTs + 1 s detector (N-input NOR) ECE 261 Krish Chakrabarty 20 10

11 Equality Comparator Check if each bit is equal (XNOR, aka equality gate) 1 s detect on bitwise equality ECE 261 Krish Chakrabarty 21 Magnitude Comparator Compute B-A and look at sign B-A = B + ~A + 1 For unsigned numbers, carry out is sign bit ECE 261 Krish Chakrabarty 22 11

12 Shifters Logical Shift: Shifts number left or right and fills with 0 s 1011 LSR 1 = LSL1 = 0110 Arithmetic Shift: Shifts number left or right. Rt shift sign extends 1011 ASR1 = ASL1 = 0110 Rotate: Shifts number left or right and fills with lost bits 1011 ROR1 = ROL1 = 0111 ECE 261 Krish Chakrabarty 23 The Binary Shifter R i g h t n o p L e f t One-bit shifts A i B i A i - 1 B i - 1 B i t - S l i c e i ECE 261 Krish Chakrabarty 24 12

13 Multi-bit Shifters Cascade one-bit shifters? Complex, unwieldy, slow for larger number of shifts Two other types of shifters Barrel shifter Logarithmic shifter ECE 261 Krish Chakrabarty 25 A 3 A 2 A 1 A 0 S h 1 S h 2 S h 3 The Barrel Shifter B 3 B 2 B 1 B 0 Shift by 0 to 3 bits : D a t a W i r e : C o n t r o l W i r e S h 0 S h 1 S h 2 S h 3 ECE 261 Krish Chakrabarty 26 13

14 The Barrel Shifter Area dominated by wiring Propagation delay is theoretically constant (at most one transmission gate), independent of shifter size, no. of shifts Reality: Capacitance on buffer input maximum shift width ECE 261 Krish Chakrabarty 27 A 3 A 2 A 1 A 0 4x4 barrel shifter S h 0 S h 1 S h 2 Width barrel ~ 2 p m M S h 3 B u f f e r p m = metal/poly pitch M = no. of shifts ECE 261 Krish Chakrabarty 28 14

15 Logarithmic Shifter Staged approach, e.g. 7 = , 5 = Shifter with maximum shift width M consists of log 2 M stages S h 1 S h 1 S h 2 S h 2 S h 4 S h 4 A 3 B 3 A 2 A 1 A 0 B 2 B 1 B 0 ECE 261 Krish Chakrabarty bit Logarithmic Shifter A 3 Out3 A 2 Out2 A 1 Out1 A 0 Out0 ECE 261 Krish Chakrabarty 30 15

16 Funnel Shifter A funnel shifter can do all six types of shifts Selects N-bit field Y from 2N-bit input Shift by k bits (0 k < N) ECE 261 Krish Chakrabarty 31 Funnel Shifter Operation Computing N-k requires an adder ECE 261 Krish Chakrabarty 32 16

17 Funnel Shifter Design 1 N N-input multiplexers Use 1-of-N hot select signals for shift amount nmos pass transistor design (V t drops!) ECE 261 Krish Chakrabarty 33 Funnel Shifter Design 2 Log N stages of 2-input muxes No select decoding needed ECE 261 Krish Chakrabarty 34 17

Arithmetic Circuits-2

Arithmetic Circuits-2 Arithmetic Circuits-2 Multipliers Array multipliers Shifters Barrel shifter Logarithmic shifter ECE 261 Krish Chakrabarty 1 Binary Multiplication M-1 X = X i 2 i i=0 Multiplicand N-1 Y = Y i 2 i i=0 Multiplier

More information

Arithmetic Circuits-2

Arithmetic Circuits-2 Arithmetic ircuits-2 Multipliers Array multipliers hifters Barrel shifter Logarithmic shifter EE 261 Krish hakrabarty 1 Binary Multiplication X = Σ X i 2 i i=0 Multiplicand M-1 N-1 Y = Σ Y i 2 i i=0 Multiplier

More information

9. Datapath Design. Jacob Abraham. Department of Electrical and Computer Engineering The University of Texas at Austin VLSI Design Fall 2017

9. Datapath Design. Jacob Abraham. Department of Electrical and Computer Engineering The University of Texas at Austin VLSI Design Fall 2017 9. Datapath Design Jacob Abraham Department of Electrical and Computer Engineering The University of Texas at Austin VLSI Design Fall 2017 October 2, 2017 ECE Department, University of Texas at Austin

More information

Lecture 18: Datapath Functional Units

Lecture 18: Datapath Functional Units Lecture 8: Datapath Functional Unit Outline Comparator Shifter Multi-input Adder Multiplier 8: Datapath Functional Unit CMOS VLSI Deign 4th Ed. 2 Comparator 0 detector: A = 00 000 detector: A = Equality

More information

Lecture 12: Datapath Functional Units

Lecture 12: Datapath Functional Units Lecture 2: Datapath Functional Unit Slide courtey of Deming Chen Slide baed on the initial et from David Harri CMOS VLSI Deign Outline Comparator Shifter Multi-input Adder Multiplier Reading:.3-4;.8-9

More information

Lecture 12: Datapath Functional Units

Lecture 12: Datapath Functional Units Introduction to CMOS VLSI Deign Lecture 2: Datapath Functional Unit David Harri Harvey Mudd College Spring 2004 Outline Comparator Shifter Multi-input Adder Multiplier 2: Datapath Functional Unit CMOS

More information

Digital Integrated Circuits A Design Perspective. Arithmetic Circuits. Jan M. Rabaey Anantha Chandrakasan Borivoje Nikolic.

Digital Integrated Circuits A Design Perspective. Arithmetic Circuits. Jan M. Rabaey Anantha Chandrakasan Borivoje Nikolic. Digital Integrated Circuits A Design Perspective Jan M. Rabaey Anantha Chandrakasan Borivoje Nikolic Arithmetic Circuits January, 2003 1 A Generic Digital Processor MEM ORY INPUT-OUTPUT CONTROL DATAPATH

More information

Chapter 5 Arithmetic Circuits

Chapter 5 Arithmetic Circuits Chapter 5 Arithmetic Circuits SKEE2263 Digital Systems Mun im/ismahani/izam {munim@utm.my,e-izam@utm.my,ismahani@fke.utm.my} February 11, 2016 Table of Contents 1 Iterative Designs 2 Adders 3 High-Speed

More information

CSE140: Components and Design Techniques for Digital Systems. Decoders, adders, comparators, multipliers and other ALU elements. Tajana Simunic Rosing

CSE140: Components and Design Techniques for Digital Systems. Decoders, adders, comparators, multipliers and other ALU elements. Tajana Simunic Rosing CSE4: Components and Design Techniques for Digital Systems Decoders, adders, comparators, multipliers and other ALU elements Tajana Simunic Rosing Mux, Demux Encoder, Decoder 2 Transmission Gate: Mux/Tristate

More information

Digital Integrated Circuits A Design Perspective. Arithmetic Circuits. Jan M. Rabaey Anantha Chandrakasan Borivoje Nikolic.

Digital Integrated Circuits A Design Perspective. Arithmetic Circuits. Jan M. Rabaey Anantha Chandrakasan Borivoje Nikolic. Digital Integrated Circuits A Design Perspective Jan M. Rabaey Anantha Chandrakasan Borivoje Nikolic Arithmetic Circuits January, 2003 1 A Generic Digital Processor MEMORY INPUT-OUTPUT CONTROL DATAPATH

More information

CS 140 Lecture 14 Standard Combinational Modules

CS 140 Lecture 14 Standard Combinational Modules CS 14 Lecture 14 Standard Combinational Modules Professor CK Cheng CSE Dept. UC San Diego Some slides from Harris and Harris 1 Part III. Standard Modules A. Interconnect B. Operators. Adders Multiplier

More information

Hardware Design I Chap. 4 Representative combinational logic

Hardware Design I Chap. 4 Representative combinational logic Hardware Design I Chap. 4 Representative combinational logic E-mail: shimada@is.naist.jp Already optimized circuits There are many optimized circuits which are well used You can reduce your design workload

More information

Lecture 8: Sequential Multipliers

Lecture 8: Sequential Multipliers Lecture 8: Sequential Multipliers ECE 645 Computer Arithmetic 3/25/08 ECE 645 Computer Arithmetic Lecture Roadmap Sequential Multipliers Unsigned Signed Radix-2 Booth Recoding High-Radix Multiplication

More information

EECS150 - Digital Design Lecture 24 - Arithmetic Blocks, Part 2 + Shifters

EECS150 - Digital Design Lecture 24 - Arithmetic Blocks, Part 2 + Shifters EECS150 - Digital Design Lecture 24 - Arithmetic Blocks, Part 2 + Shifters April 15, 2010 John Wawrzynek 1 Multiplication a 3 a 2 a 1 a 0 Multiplicand b 3 b 2 b 1 b 0 Multiplier X a 3 b 0 a 2 b 0 a 1 b

More information

ECE 545 Digital System Design with VHDL Lecture 1. Digital Logic Refresher Part A Combinational Logic Building Blocks

ECE 545 Digital System Design with VHDL Lecture 1. Digital Logic Refresher Part A Combinational Logic Building Blocks ECE 545 Digital System Design with VHDL Lecture Digital Logic Refresher Part A Combinational Logic Building Blocks Lecture Roadmap Combinational Logic Basic Logic Review Basic Gates De Morgan s Law Combinational

More information

CSE 140 Lecture 11 Standard Combinational Modules. CK Cheng and Diba Mirza CSE Dept. UC San Diego

CSE 140 Lecture 11 Standard Combinational Modules. CK Cheng and Diba Mirza CSE Dept. UC San Diego CSE 4 Lecture Standard Combinational Modules CK Cheng and Diba Mirza CSE Dept. UC San Diego Part III - Standard Combinational Modules (Harris: 2.8, 5) Signal Transport Decoder: Decode address Encoder:

More information

Digital Integrated Circuits A Design Perspective

Digital Integrated Circuits A Design Perspective rithmetic ircuitsss dapted from hapter 11 of Digital Integrated ircuits Design Perspective Jan M. Rabaey et al. opyright 2003 Prentice Hall/Pearson 1 Generic Digital Processor MEMORY INPUT-OUTPUT ONTROL

More information

EE141. Lecture 28 Multipliers. Lecture #20. Project Phase 2 Posted. Sign up for one of three project goals today

EE141. Lecture 28 Multipliers. Lecture #20. Project Phase 2 Posted. Sign up for one of three project goals today EE141-pring 2008 igital Integrated ircuits Lecture 28 Multipliers 1 Announcements Project Phase 2 Posted ign up for one of three project goals today Graded Phase 1 and Midterm 2 will be returned next Fr

More information

Arithmetic Building Blocks

Arithmetic Building Blocks rithmetic uilding locks Datapath elements dder design Static adder Dynamic adder Multiplier design rray multipliers Shifters, Parity circuits ECE 261 Krish Chakrabarty 1 Generic Digital Processor Input-Output

More information

ECE 545 Digital System Design with VHDL Lecture 1A. Digital Logic Refresher Part A Combinational Logic Building Blocks

ECE 545 Digital System Design with VHDL Lecture 1A. Digital Logic Refresher Part A Combinational Logic Building Blocks ECE 545 Digital System Design with VHDL Lecture A Digital Logic Refresher Part A Combinational Logic Building Blocks Lecture Roadmap Combinational Logic Basic Logic Review Basic Gates De Morgan s Laws

More information

CSE140: Components and Design Techniques for Digital Systems. Logic minimization algorithm summary. Instructor: Mohsen Imani UC San Diego

CSE140: Components and Design Techniques for Digital Systems. Logic minimization algorithm summary. Instructor: Mohsen Imani UC San Diego CSE4: Components and Design Techniques for Digital Systems Logic minimization algorithm summary Instructor: Mohsen Imani UC San Diego Slides from: Prof.Tajana Simunic Rosing & Dr.Pietro Mercati Definition

More information

Digital Integrated Circuits A Design Perspective. Arithmetic Circuits

Digital Integrated Circuits A Design Perspective. Arithmetic Circuits Digital Integrated Circuits Design Perspective rithmetic Circuits Reference: Digital Integrated Circuits, 2nd edition, Jan M. Rabaey, nantha Chandrakasan and orivoje Nikolic Disclaimer: slides adapted

More information

Serial Parallel Multiplier Design in Quantum-dot Cellular Automata

Serial Parallel Multiplier Design in Quantum-dot Cellular Automata Serial Parallel Multiplier Design in Quantum-dot Cellular Automata Heumpil Cho and Earl E. Swartzlander, Jr. Application Specific Processor Group Department of Electrical and Computer Engineering The University

More information

ECE/CS 552: Introduction To Computer Architecture 1. Instructor:Mikko H Lipasti. Fall 2010 University i of Wisconsin-Madison

ECE/CS 552: Introduction To Computer Architecture 1. Instructor:Mikko H Lipasti. Fall 2010 University i of Wisconsin-Madison ECE/CS 552: Arithmetic I Instructor:Mikko H Lipasti Fall 2010 Univsity i of Wisconsin-Madison i Lecture notes partially based on set created by Mark Hill. Basic Arithmetic and the ALU Numb representations:

More information

Fundamentals of Digital Design

Fundamentals of Digital Design Fundamentals of Digital Design Digital Radiation Measurement and Spectroscopy NE/RHP 537 1 Binary Number System The binary numeral system, or base-2 number system, is a numeral system that represents numeric

More information

Chapter 4. Combinational: Circuits with logic gates whose outputs depend on the present combination of the inputs. elements. Dr.

Chapter 4. Combinational: Circuits with logic gates whose outputs depend on the present combination of the inputs. elements. Dr. Chapter 4 Dr. Panos Nasiopoulos Combinational: Circuits with logic gates whose outputs depend on the present combination of the inputs. Sequential: In addition, they include storage elements Combinational

More information

Static CMOS Circuits. Example 1

Static CMOS Circuits. Example 1 Static CMOS Circuits Conventional (ratio-less) static CMOS Covered so far Ratio-ed logic (depletion load, pseudo nmos) Pass transistor logic ECE 261 Krish Chakrabarty 1 Example 1 module mux(input s, d0,

More information

Adders, subtractors comparators, multipliers and other ALU elements

Adders, subtractors comparators, multipliers and other ALU elements CSE4: Components and Design Techniques for Digital Systems Adders, subtractors comparators, multipliers and other ALU elements Instructor: Mohsen Imani UC San Diego Slides from: Prof.Tajana Simunic Rosing

More information

DIGITAL TECHNICS. Dr. Bálint Pődör. Óbuda University, Microelectronics and Technology Institute

DIGITAL TECHNICS. Dr. Bálint Pődör. Óbuda University, Microelectronics and Technology Institute DIGITAL TECHNICS Dr. Bálint Pődör Óbuda University, Microelectronics and Technology Institute 4. LECTURE: COMBINATIONAL LOGIC DESIGN: ARITHMETICS (THROUGH EXAMPLES) 2016/2017 COMBINATIONAL LOGIC DESIGN:

More information

Logic and Computer Design Fundamentals. Chapter 5 Arithmetic Functions and Circuits

Logic and Computer Design Fundamentals. Chapter 5 Arithmetic Functions and Circuits Logic and Computer Design Fundamentals Chapter 5 Arithmetic Functions and Circuits Arithmetic functions Operate on binary vectors Use the same subfunction in each bit position Can design functional block

More information

Review for Final Exam

Review for Final Exam CSE140: Components and Design Techniques for Digital Systems Review for Final Exam Mohsen Imani CAPE Please submit your evaluations!!!! RTL design Use the RTL design process to design a system that has

More information

CMPEN 411 VLSI Digital Circuits Spring Lecture 21: Shifters, Decoders, Muxes

CMPEN 411 VLSI Digital Circuits Spring Lecture 21: Shifters, Decoders, Muxes CMPEN 411 VLSI Digital Circuits Spring 2011 Lecture 21: Shifters, Decoders, Muxes [Adapted from Rabaey s Digital Integrated Circuits, Second Edition, 2003 J. Rabaey, A. Chandrakasan, B. Nikolic] Sp11 CMPEN

More information

Chapter 5. Digital Design and Computer Architecture, 2 nd Edition. David Money Harris and Sarah L. Harris. Chapter 5 <1>

Chapter 5. Digital Design and Computer Architecture, 2 nd Edition. David Money Harris and Sarah L. Harris. Chapter 5 <1> Chapter 5 Digital Design and Computer Architecture, 2 nd Edition David Money Harris and Sarah L. Harris Chapter 5 Chapter 5 :: Topics Introduction Arithmetic Circuits umber Systems Sequential Building

More information

Design of Sequential Circuits

Design of Sequential Circuits Design of Sequential Circuits Seven Steps: Construct a state diagram (showing contents of flip flop and inputs with next state) Assign letter variables to each flip flop and each input and output variable

More information

Combinational Logic Design Arithmetic Functions and Circuits

Combinational Logic Design Arithmetic Functions and Circuits Combinational Logic Design Arithmetic Functions and Circuits Overview Binary Addition Half Adder Full Adder Ripple Carry Adder Carry Look-ahead Adder Binary Subtraction Binary Subtractor Binary Adder-Subtractor

More information

CSEE 3827: Fundamentals of Computer Systems. Combinational Circuits

CSEE 3827: Fundamentals of Computer Systems. Combinational Circuits CSEE 3827: Fundamentals of Computer Systems Combinational Circuits Outline (M&K 3., 3.3, 3.6-3.9, 4.-4.2, 4.5, 9.4) Combinational Circuit Design Standard combinational circuits enabler decoder encoder

More information

Adders, subtractors comparators, multipliers and other ALU elements

Adders, subtractors comparators, multipliers and other ALU elements CSE4: Components and Design Techniques for Digital Systems Adders, subtractors comparators, multipliers and other ALU elements Adders 2 Circuit Delay Transistors have instrinsic resistance and capacitance

More information

CMPEN 411 VLSI Digital Circuits Spring Lecture 19: Adder Design

CMPEN 411 VLSI Digital Circuits Spring Lecture 19: Adder Design CMPEN 411 VLSI Digital Circuits Spring 2011 Lecture 19: Adder Design [Adapted from Rabaey s Digital Integrated Circuits, Second Edition, 2003 J. Rabaey, A. Chandrakasan, B. Nikolic] Sp11 CMPEN 411 L19

More information

Lecture 7: Logic design. Combinational logic circuits

Lecture 7: Logic design. Combinational logic circuits /24/28 Lecture 7: Logic design Binary digital circuits: Two voltage levels: and (ground and supply voltage) Built from transistors used as on/off switches Analog circuits not very suitable for generic

More information

Combinational Logic. By : Ali Mustafa

Combinational Logic. By : Ali Mustafa Combinational Logic By : Ali Mustafa Contents Adder Subtractor Multiplier Comparator Decoder Encoder Multiplexer How to Analyze any combinational circuit like this? Analysis Procedure To obtain the output

More information

KINGS COLLEGE OF ENGINEERING DEPARTMENT OF ELECTRONICS AND COMMUNICATION ENGINEERING QUESTION BANK

KINGS COLLEGE OF ENGINEERING DEPARTMENT OF ELECTRONICS AND COMMUNICATION ENGINEERING QUESTION BANK KINGS COLLEGE OF ENGINEERING DEPARTMENT OF ELECTRONICS AND COMMUNICATION ENGINEERING QUESTION BANK SUBJECT CODE: EC 1354 SUB.NAME : VLSI DESIGN YEAR / SEMESTER: III / VI UNIT I MOS TRANSISTOR THEORY AND

More information

EECS150. Arithmetic Circuits

EECS150. Arithmetic Circuits EE5 ection 8 Arithmetic ircuits Fall 2 Arithmetic ircuits Excellent Examples of ombinational Logic Design Time vs. pace Trade-offs Doing things fast may require more logic and thus more space Example:

More information

A COMBINED 16-BIT BINARY AND DUAL GALOIS FIELD MULTIPLIER. Jesus Garcia and Michael J. Schulte

A COMBINED 16-BIT BINARY AND DUAL GALOIS FIELD MULTIPLIER. Jesus Garcia and Michael J. Schulte A COMBINED 16-BIT BINARY AND DUAL GALOIS FIELD MULTIPLIER Jesus Garcia and Michael J. Schulte Lehigh University Department of Computer Science and Engineering Bethlehem, PA 15 ABSTRACT Galois field arithmetic

More information

Looking at a two binary digit sum shows what we need to extend addition to multiple binary digits.

Looking at a two binary digit sum shows what we need to extend addition to multiple binary digits. A Full Adder The half-adder is extremely useful until you want to add more that one binary digit quantities. The slow way to develop a two binary digit adders would be to make a truth table and reduce

More information

Computer organization

Computer organization Computer organization Levels of abstraction Assembler Simulator Applications C C++ Java High-level language SOFTWARE add lw ori Assembly language Goal 0000 0001 0000 1001 0101 Machine instructions/data

More information

Class Website:

Class Website: ECE 20B, Winter 2003 Introduction to Electrical Engineering, II LECTURE NOTES #5 Instructor: Andrew B. Kahng (lecture) Email: abk@ece.ucsd.edu Telephone: 858-822-4884 office, 858-353-0550 cell Office:

More information

Lecture 8. Sequential Multipliers

Lecture 8. Sequential Multipliers Lecture 8 Sequential Multipliers Required Reading Behrooz Parhami, Computer Arithmetic: Algorithms and Hardware Design Chapter 9, Basic Multiplication Scheme Chapter 10, High-Radix Multipliers Chapter

More information

Systems I: Computer Organization and Architecture

Systems I: Computer Organization and Architecture Systems I: Computer Organization and Architecture Lecture 6 - Combinational Logic Introduction A combinational circuit consists of input variables, logic gates, and output variables. The logic gates accept

More information

ALUs and Data Paths. Subtitle: How to design the data path of a processor. 1/8/ L3 Data Path Design Copyright Joanne DeGroat, ECE, OSU 1

ALUs and Data Paths. Subtitle: How to design the data path of a processor. 1/8/ L3 Data Path Design Copyright Joanne DeGroat, ECE, OSU 1 ALUs and Data Paths Subtitle: How to design the data path of a processor. Copyright 2006 - Joanne DeGroat, ECE, OSU 1 Lecture overview General Data Path of a multifunction ALU Copyright 2006 - Joanne DeGroat,

More information

Digital Design for Multiplication

Digital Design for Multiplication Digital Design for Multiplication Norman Matloff October 15, 2003 c 2003, N.S. Matloff 1 Overview A cottage industry exists in developing fast digital logic to perform arithmetic computations. Fast addition,

More information

Where are we? Data Path Design

Where are we? Data Path Design Where are we? Subsystem Design Registers and Register Files dders and LUs Simple ripple carry addition Transistor schematics Faster addition Logic generation How it fits into the datapath Data Path Design

More information

EE141- Spring 2004 Digital Integrated Circuits

EE141- Spring 2004 Digital Integrated Circuits EE141- pring 2004 Digital Integrated ircuits Lecture 19 Dynamic Logic - Adders (that is wrap-up) 1 Administrative tuff Hw 6 due on Th No lab this week Midterm 2 next week Project 2 to be launched week

More information

Lecture 2 Review on Digital Logic (Part 1)

Lecture 2 Review on Digital Logic (Part 1) Lecture 2 Review on Digital Logic (Part 1) Xuan Silvia Zhang Washington University in St. Louis http://classes.engineering.wustl.edu/ese461/ Grading Engagement 5% Review Quiz 10% Homework 10% Labs 40%

More information

VLSI Arithmetic. Lecture 9: Carry-Save and Multi-Operand Addition. Prof. Vojin G. Oklobdzija University of California

VLSI Arithmetic. Lecture 9: Carry-Save and Multi-Operand Addition. Prof. Vojin G. Oklobdzija University of California VLSI Arithmetic Lecture 9: Carry-Save and Multi-Operand Addition Prof. Vojin G. Oklobdzija University of California http://www.ece.ucdavis.edu/acsel Carry-Save Addition* *from Parhami 2 June 18, 2003 Carry-Save

More information

Where are we? Data Path Design. Bit Slice Design. Bit Slice Design. Bit Slice Plan

Where are we? Data Path Design. Bit Slice Design. Bit Slice Design. Bit Slice Plan Where are we? Data Path Design Subsystem Design Registers and Register Files dders and LUs Simple ripple carry addition Transistor schematics Faster addition Logic generation How it fits into the datapath

More information

Digital System Design Combinational Logic. Assoc. Prof. Pradondet Nilagupta

Digital System Design Combinational Logic. Assoc. Prof. Pradondet Nilagupta Digital System Design Combinational Logic Assoc. Prof. Pradondet Nilagupta pom@ku.ac.th Acknowledgement This lecture note is modified from Engin112: Digital Design by Prof. Maciej Ciesielski, Prof. Tilman

More information

CMPUT 329. Circuits for binary addition

CMPUT 329. Circuits for binary addition CMPUT 329 Parallel Adder with Carry Lookahead and ALU Ioanis Nikolaidis (Katz & Borriello) rcuits for binary addition Full adder (carry-in to cascade for multi-bit adders) Sum = xor A xor B Cout = B +

More information

ECE380 Digital Logic. Positional representation

ECE380 Digital Logic. Positional representation ECE380 Digital Logic Number Representation and Arithmetic Circuits: Number Representation and Unsigned Addition Dr. D. J. Jackson Lecture 16-1 Positional representation First consider integers Begin with

More information

Tree and Array Multipliers Ivor Page 1

Tree and Array Multipliers Ivor Page 1 Tree and Array Multipliers 1 Tree and Array Multipliers Ivor Page 1 11.1 Tree Multipliers In Figure 1 seven input operands are combined by a tree of CSAs. The final level of the tree is a carry-completion

More information

VLSI Design. [Adapted from Rabaey s Digital Integrated Circuits, 2002, J. Rabaey et al.] ECE 4121 VLSI DEsign.1

VLSI Design. [Adapted from Rabaey s Digital Integrated Circuits, 2002, J. Rabaey et al.] ECE 4121 VLSI DEsign.1 VLSI Design Adder Design [Adapted from Rabaey s Digital Integrated Circuits, 2002, J. Rabaey et al.] ECE 4121 VLSI DEsign.1 Major Components of a Computer Processor Devices Control Memory Input Datapath

More information

COE 202: Digital Logic Design Combinational Circuits Part 4. Dr. Ahmad Almulhem ahmadsm AT kfupm Phone: Office:

COE 202: Digital Logic Design Combinational Circuits Part 4. Dr. Ahmad Almulhem   ahmadsm AT kfupm Phone: Office: COE 202: Digital Logic Design Combinational Circuits Part 4 Dr. Ahmad Almulhem Email: ahmadsm AT kfupm Phone: 860-7554 Office: 22-324 Objectives Magnitude comparator Design of 4-bit magnitude comparator

More information

ECE 341. Lecture # 3

ECE 341. Lecture # 3 ECE 341 Lecture # 3 Instructor: Zeshan Chishti zeshan@ece.pdx.edu October 7, 2013 Portland State University Lecture Topics Counters Finite State Machines Decoders Multiplexers Reference: Appendix A of

More information

Homework 4 due today Quiz #4 today In class (80min) final exam on April 29 Project reports due on May 4. Project presentations May 5, 1-4pm

Homework 4 due today Quiz #4 today In class (80min) final exam on April 29 Project reports due on May 4. Project presentations May 5, 1-4pm EE241 - Spring 2010 Advanced Digital Integrated Circuits Lecture 25: Digital Arithmetic Adders Announcements Homework 4 due today Quiz #4 today In class (80min) final exam on April 29 Project reports due

More information

1 Short adders. t total_ripple8 = t first + 6*t middle + t last = 4t p + 6*2t p + 2t p = 18t p

1 Short adders. t total_ripple8 = t first + 6*t middle + t last = 4t p + 6*2t p + 2t p = 18t p UNIVERSITY OF CALIFORNIA College of Engineering Department of Electrical Engineering and Computer Sciences Study Homework: Arithmetic NTU IC54CA (Fall 2004) SOLUTIONS Short adders A The delay of the ripple

More information

ECE 250 / CPS 250 Computer Architecture. Basics of Logic Design Boolean Algebra, Logic Gates

ECE 250 / CPS 250 Computer Architecture. Basics of Logic Design Boolean Algebra, Logic Gates ECE 250 / CPS 250 Computer Architecture Basics of Logic Design Boolean Algebra, Logic Gates Benjamin Lee Slides based on those from Andrew Hilton (Duke), Alvy Lebeck (Duke) Benjamin Lee (Duke), and Amir

More information

CprE 281: Digital Logic

CprE 281: Digital Logic CprE 28: Digital Logic Instructor: Alexander Stoytchev http://www.ece.iastate.edu/~alexs/classes/ Code Converters CprE 28: Digital Logic Iowa State University, Ames, IA Copyright Alexander Stoytchev HW

More information

CSE477 VLSI Digital Circuits Fall Lecture 20: Adder Design

CSE477 VLSI Digital Circuits Fall Lecture 20: Adder Design CSE477 VLSI Digital Circuits Fall 22 Lecture 2: Adder Design Mary Jane Irwin ( www.cse.psu.edu/~mji ) www.cse.psu.edu/~cg477 [Adapted from Rabaey s Digital Integrated Circuits, 22, J. Rabaey et al.] CSE477

More information

Combinational Logic Design Combinational Functions and Circuits

Combinational Logic Design Combinational Functions and Circuits Combinational Logic Design Combinational Functions and Circuits Overview Combinational Circuits Design Procedure Generic Example Example with don t cares: BCD-to-SevenSegment converter Binary Decoders

More information

ARITHMETIC COMBINATIONAL MODULES AND NETWORKS

ARITHMETIC COMBINATIONAL MODULES AND NETWORKS ARITHMETIC COMBINATIONAL MODULES AND NETWORKS 1 SPECIFICATION OF ADDER MODULES FOR POSITIVE INTEGERS HALF-ADDER AND FULL-ADDER MODULES CARRY-RIPPLE AND CARRY-LOOKAHEAD ADDER MODULES NETWORKS OF ADDER MODULES

More information

Carry Look Ahead Adders

Carry Look Ahead Adders Carry Look Ahead Adders Lesson Objectives: The objectives of this lesson are to learn about: 1. Carry Look Ahead Adder circuit. 2. Binary Parallel Adder/Subtractor circuit. 3. BCD adder circuit. 4. Binary

More information

Total Time = 90 Minutes, Total Marks = 50. Total /50 /10 /18

Total Time = 90 Minutes, Total Marks = 50. Total /50 /10 /18 University of Waterloo Department of Electrical & Computer Engineering E&CE 223 Digital Circuits and Systems Midterm Examination Instructor: M. Sachdev October 23rd, 2007 Total Time = 90 Minutes, Total

More information

Bit-Sliced Design. EECS 141 F01 Arithmetic Circuits. A Generic Digital Processor. Full-Adder. The Binary Adder

Bit-Sliced Design. EECS 141 F01 Arithmetic Circuits. A Generic Digital Processor. Full-Adder. The Binary Adder it-liced Design Control EEC 141 F01 rithmetic Circuits Data-In Register dder hifter it 3 it 2 it 1 it 0 Data-Out Tile identical processing elements Generic Digital Processor Full-dder MEMORY Cin Full adder

More information

Logic. Combinational. inputs. outputs. the result. system can

Logic. Combinational. inputs. outputs. the result. system can Digital Electronics Combinational Logic Functions Digital logic circuits can be classified as either combinational or sequential circuits. A combinational circuit is one where the output at any time depends

More information

Boolean Algebra and Digital Logic 2009, University of Colombo School of Computing

Boolean Algebra and Digital Logic 2009, University of Colombo School of Computing IT 204 Section 3.0 Boolean Algebra and Digital Logic Boolean Algebra 2 Logic Equations to Truth Tables X = A. B + A. B + AB A B X 0 0 0 0 3 Sum of Products The OR operation performed on the products of

More information

Number System. Decimal to binary Binary to Decimal Binary to octal Binary to hexadecimal Hexadecimal to binary Octal to binary

Number System. Decimal to binary Binary to Decimal Binary to octal Binary to hexadecimal Hexadecimal to binary Octal to binary Number System Decimal to binary Binary to Decimal Binary to octal Binary to hexadecimal Hexadecimal to binary Octal to binary BOOLEAN ALGEBRA BOOLEAN LOGIC OPERATIONS Logical AND Logical OR Logical COMPLEMENTATION

More information

CHAPTER VI COMBINATIONAL LOGIC BUILDING BLOCKS

CHAPTER VI COMBINATIONAL LOGIC BUILDING BLOCKS CHAPTR VI- CHAPTR VI CHAPTR VI BUILDING BLOCKS R.M. Dansereau; v.. CHAPTR VI- COMBINAT. LOGIC INTRODUCTION -INTRODUCTION Combinational logic Output at any time is determined completely by the current input.

More information

EECS150 - Digital Design Lecture 25 Shifters and Counters. Recap

EECS150 - Digital Design Lecture 25 Shifters and Counters. Recap EECS150 - Digital Design Lecture 25 Shifters and Counters Nov. 21, 2013 Prof. Ronald Fearing Electrical Engineering and Computer Sciences University of California, Berkeley (slides courtesy of Prof. John

More information

CMP 334: Seventh Class

CMP 334: Seventh Class CMP 334: Seventh Class Performance HW 5 solution Averages and weighted averages (review) Amdahl's law Ripple-carry adder circuits Binary addition Half-adder circuits Full-adder circuits Subtraction, negative

More information

Fundamentals of Computer Systems

Fundamentals of Computer Systems Fundamentals of omputer Systems ombinational Logic Stephen. Edwards olumbia University Fall 2012 Encoders and Decoders Decoders Input: n-bit binary number Output: 1-of-2 n one-hot code 2-to-4 in out 00

More information

L8/9: Arithmetic Structures

L8/9: Arithmetic Structures L8/9: Arithmetic Structures Acknowledgements: Materials in this lecture are courtesy of the following sources and are used with permission. Rex Min Kevin Atkinson Prof. Randy Katz (Unified Microelectronics

More information

CS61C : Machine Structures

CS61C : Machine Structures CS 61C L15 Blocks (1) inst.eecs.berkeley.edu/~cs61c/su05 CS61C : Machine Structures Lecture #15: Combinational Logic Blocks Outline CL Blocks Latches & Flip Flops A Closer Look 2005-07-14 Andy Carle CS

More information

Adders - Subtractors

Adders - Subtractors Adders - Subtractors Lesson Objectives: The objectives of this lesson are to learn about: 1. Half adder circuit. 2. Full adder circuit. 3. Binary parallel adder circuit. 4. Half subtractor circuit. 5.

More information

We are here. Assembly Language. Processors Arithmetic Logic Units. Finite State Machines. Circuits Gates. Transistors

We are here. Assembly Language. Processors Arithmetic Logic Units. Finite State Machines. Circuits Gates. Transistors CSC258 Week 3 1 Logistics If you cannot login to MarkUs, email me your UTORID and name. Check lab marks on MarkUs, if it s recorded wrong, contact Larry within a week after the lab. Quiz 1 average: 86%

More information

CMSC 313 Lecture 18 Midterm Exam returned Assign Homework 3 Circuits for Addition Digital Logic Components Programmable Logic Arrays

CMSC 313 Lecture 18 Midterm Exam returned Assign Homework 3 Circuits for Addition Digital Logic Components Programmable Logic Arrays MS 33 Lecture 8 Midterm Exam returned Assign Homework 3 ircuits for Addition Digital Logic omponents Programmable Logic Arrays UMB, MS33, Richard hang MS 33, omputer Organization & Assembly

More information

XI STANDARD [ COMPUTER SCIENCE ] 5 MARKS STUDY MATERIAL.

XI STANDARD [ COMPUTER SCIENCE ] 5 MARKS STUDY MATERIAL. 2017-18 XI STANDARD [ COMPUTER SCIENCE ] 5 MARKS STUDY MATERIAL HALF ADDER 1. The circuit that performs addition within the Arithmetic and Logic Unit of the CPU are called adders. 2. A unit that adds two

More information

Design and Comparison of Wallace Multiplier Based on Symmetric Stacking and High speed counters

Design and Comparison of Wallace Multiplier Based on Symmetric Stacking and High speed counters International Journal of Engineering Research and Advanced Technology (IJERAT) DOI:http://dx.doi.org/10.31695/IJERAT.2018.3271 E-ISSN : 2454-6135 Volume.4, Issue 6 June -2018 Design and Comparison of Wallace

More information

S No. Questions Bloom s Taxonomy Level UNIT-I

S No. Questions Bloom s Taxonomy Level UNIT-I GROUP-A (SHORT ANSWER QUESTIONS) S No. Questions Bloom s UNIT-I 1 Define oxidation & Classify different types of oxidation Remember 1 2 Explain about Ion implantation Understand 1 3 Describe lithography

More information

3. Combinational Circuit Design

3. Combinational Circuit Design CSEE 3827: Fundamentals of Computer Systems, Spring 2 3. Combinational Circuit Design Prof. Martha Kim (martha@cs.columbia.edu) Web: http://www.cs.columbia.edu/~martha/courses/3827/sp/ Outline (H&H 2.8,

More information

CS61C : Machine Structures

CS61C : Machine Structures inst.eecs.berkeley.edu/~cs61c/su05 CS61C : Machine Structures Lecture #15: Combinational Logic Blocks 2005-07-14 CS 61C L15 Blocks (1) Andy Carle Outline CL Blocks Latches & Flip Flops A Closer Look CS

More information

Karnaugh Maps (K-Maps)

Karnaugh Maps (K-Maps) Karnaugh Maps (K-Maps) Boolean expressions can be minimized by combining terms P + P = P K-maps minimize equations graphically Put terms to combine close to one another B C C B B C BC BC BC BC BC BC BC

More information

COSC3330 Computer Architecture Lecture 2. Combinational Logic

COSC3330 Computer Architecture Lecture 2. Combinational Logic COSC333 Computer rchitecture Lecture 2. Combinational Logic Instructor: Weidong Shi (Larry), PhD Computer Science Department University of Houston Today Combinational Logic oolean lgebra Mux, DeMux, Decoder

More information

Midterm Exam Two is scheduled on April 8 in class. On March 27 I will help you prepare Midterm Exam Two.

Midterm Exam Two is scheduled on April 8 in class. On March 27 I will help you prepare Midterm Exam Two. Announcements Midterm Exam Two is scheduled on April 8 in class. On March 27 I will help you prepare Midterm Exam Two. Chapter 5 1 Chapter 3: Part 3 Arithmetic Functions Iterative combinational circuits

More information

Computer Architecture 10. Fast Adders

Computer Architecture 10. Fast Adders Computer Architecture 10 Fast s Ma d e wi t h Op e n Of f i c e. o r g 1 Carry Problem Addition is primary mechanism in implementing arithmetic operations Slow addition directly affects the total performance

More information

E40M. Binary Numbers. M. Horowitz, J. Plummer, R. Howe 1

E40M. Binary Numbers. M. Horowitz, J. Plummer, R. Howe 1 E40M Binary Numbers M. Horowitz, J. Plummer, R. Howe 1 Reading Chapter 5 in the reader A&L 5.6 M. Horowitz, J. Plummer, R. Howe 2 Useless Box Lab Project #2 Adding a computer to the Useless Box alows us

More information

Introduction to Digital Logic

Introduction to Digital Logic Introduction to Digital Logic Lecture 15: Comparators EXERCISES Mark Redekopp, All rights reserved Adding Many Bits You know that an FA adds X + Y + Ci Use FA and/or HA components to add 4 individual bits:

More information

CprE 281: Digital Logic

CprE 281: Digital Logic CprE 28: Digital Logic Instructor: Alexander Stoytchev http://www.ece.iastate.edu/~alexs/classes/ Decoders and Encoders CprE 28: Digital Logic Iowa State University, Ames, IA Copyright Alexander Stoytchev

More information

An Optical Parallel Adder Towards Light Speed Data Processing

An Optical Parallel Adder Towards Light Speed Data Processing An Optical Parallel Adder Towards Light Speed Data Processing Tohru ISHIHARA, Akihiko SHINYA, Koji INOUE, Kengo NOZAKI and Masaya NOTOMI Kyoto University NTT Nanophotonics Center / NTT Basic Research Laboratories

More information

Computer Science 324 Computer Architecture Mount Holyoke College Fall Topic Notes: Digital Logic

Computer Science 324 Computer Architecture Mount Holyoke College Fall Topic Notes: Digital Logic Computer Science 324 Computer Architecture Mount Holyoke College Fall 2007 Topic Notes: Digital Logic Our goal for the next few weeks is to paint a a reasonably complete picture of how we can go from transistor

More information

Numbers & Arithmetic. Hakim Weatherspoon CS 3410, Spring 2012 Computer Science Cornell University. See: P&H Chapter , 3.2, C.5 C.

Numbers & Arithmetic. Hakim Weatherspoon CS 3410, Spring 2012 Computer Science Cornell University. See: P&H Chapter , 3.2, C.5 C. Numbers & Arithmetic Hakim Weatherspoon CS 3410, Spring 2012 Computer Science Cornell University See: P&H Chapter 2.4-2.6, 3.2, C.5 C.6 Example: Big Picture Computer System Organization and Programming

More information

Binary addition by hand. Adding two bits

Binary addition by hand. Adding two bits Chapter 3 Arithmetic is the most basic thing you can do with a computer We focus on addition, subtraction, multiplication and arithmetic-logic units, or ALUs, which are the heart of CPUs. ALU design Bit

More information